JP2009225580A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit that reduces step-up time and prevents a drop of a step-up voltage that is finally obtained. <P>SOLUTION: Before the start of step-up operation, a capacitance element 1 is initially charged via a rectifying device 3 and a transistor 4 respectively for initial charging. After the start of step-up operation, a voltage higher than a power supply voltage is applied to a gate of the transistor 4 for initial charging. Therefore, an OFF-leakage current of the transistor 4 for initial charging is reduced. As a result, it is possible to prevent a drop of a step-up voltage that is finally obtained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a charge pump circuit for boosting a power supply voltage.

  2. Description of the Related Art Conventionally, in a semiconductor nonvolatile memory device, a voltage higher than a power supply voltage is required at the time of signal writing or erasing, and therefore a booster circuit (charge pump circuit) in which a plurality of booster cells are connected in series has been used. (For example, refer to JP-A-60-251598 (Patent Document 1)).

  Each booster cell of the booster circuit includes a transfer transistor for charge transfer and a capacitor for charge / discharge. The drain and gate of the transmission transistor are connected to each other and used as the input of the booster cell, and the source is used as the output of the booster cell. A power supply voltage is supplied to the input of the booster cell in the first stage. One end of the capacitor is connected to the source of the transmission transistor, and a clock is input to the other end of the capacitor.

  Further, an initial charging transistor is provided in each boosting cell. The initial charging transistor has a power supply connected to its drain and gate, and a source of the transmission transistor connected to its source. As a result, before starting the boosting operation, the source of the transmission transistor is given a voltage that is lower than the power supply voltage by the threshold voltage of the transistor for initial charging. Therefore, the booster circuit does not need to be charged up to that voltage in the initial stage of boosting (see, for example, JP-A-11-283392 (Patent Document 2)).

  The booster circuit has a problem of increasing the boosting efficiency and increasing the boosting speed. For example, in the technique disclosed in Japanese Patent Laid-Open No. 11-283392 (Patent Document 2), in order to reduce the influence of the back gate bias characteristic, the transfer transistor of each booster cell is formed of a triple well semiconductor. Further, in the booster circuit disclosed in Japanese Patent Application Laid-Open No. 2000-149582 (Patent Document 3), the portion from the intermediate node to the output is parallelized in order to increase the boosting speed. In this case, the capacity of the booster circuit is switched according to the output potential.

Note that the negative voltage can be boosted by a configuration similar to that of the charge pump circuit for boosting to a positive voltage (see, for example, JP-A-7-177729 (Patent Document 4)).
JP-A-60-251598 Japanese Patent Laid-Open No. 11-283392 JP 2000-149582 A JP-A-7-177729

  By the way, as a recent trend, the power supply voltage has been lowered, and in many cases, a power supply voltage lower than a threshold voltage of a normally used MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) is used. In order to operate a semiconductor circuit efficiently even with such a low power supply voltage, it is necessary to use a MOSFET having a lower threshold voltage.

  However, the inventors of the present invention, when the threshold voltage is lowered in the charge pump circuit using the initial charging transistor described in the above-mentioned JP-A-11-283392 (Patent Document 2), It has been found that the following problems occur.

  In the charge pump circuit, the voltage charged in the capacitor element of each boosting cell increases as the boosting operation proceeds. Accordingly, the voltage between the drain and source of the MOS transistor for initial charging increases. Therefore, the off-leakage of the initial charge MOS transistor increases, and the charge charged in the capacitor element of each boosting cell is discharged to the power supply node through the initial charge MOS transistor.

  In particular, when a MOS transistor having a low threshold voltage is used, the off-leakage current that flows when the drain-source voltage increases is larger than that of a normal threshold voltage MOS transistor. For this reason, the off-leakage current cannot be ignored with respect to the current flowing through the charge pump circuit, and the finally obtained boosted voltage is lowered.

  Accordingly, an object of the present invention is to provide a charge pump circuit that can shorten the boosting time and prevent the finally obtained boosted voltage from being lowered.

  In summary, the present invention is a charge pump circuit including a plurality of first transistors, a plurality of capacitor elements, a plurality of rectifier elements, a plurality of second transistors, and a control circuit. Here, the plurality of first transistors are connected in series between an input terminal that receives the first power supply voltage and an output terminal. Each first transistor transfers charge from the input terminal to the output terminal. The plurality of capacitor elements are provided corresponding to the plurality of first transistors, respectively. Each capacitive element is connected to the output node of the corresponding first transistor, and accumulates the transferred charge. The plurality of rectifying elements are provided corresponding to the plurality of first transistors, respectively. Each cathode of the plurality of rectifying elements is connected to the output node of the corresponding first transistor. The plurality of second transistors are P-channel MOS transistors provided corresponding to the plurality of rectifying elements, respectively. Each drain of the plurality of second transistors is connected to the anode of the corresponding rectifying element. Each source of the plurality of second transistors receives a first power supply voltage. The control circuit receives a second power supply voltage higher than the first power supply voltage, and outputs the second power supply voltage to each gate of the plurality of second transistors after the start of charge transfer by the plurality of first transistors. .

  According to another aspect of the present invention, the present invention is a charge pump circuit including a plurality of first transistors, a plurality of capacitive elements, a plurality of rectifier elements, and a plurality of second transistors. . Here, the plurality of first transistors are connected in series between an input terminal that receives the first power supply voltage and an output terminal. Each first transistor transfers charge from the input terminal to the output terminal. The plurality of capacitor elements are provided corresponding to the plurality of first transistors, respectively. Each capacitive element is connected to the output node of the corresponding first transistor, and accumulates the transferred charge. The plurality of rectifying elements are provided corresponding to the plurality of first transistors, respectively. Each cathode of the plurality of rectifying elements is connected to the output node of the corresponding first transistor. The plurality of second transistors are P-channel MOS transistors provided corresponding to the plurality of rectifying elements, respectively. Each drain of the plurality of second transistors is connected to the anode of the corresponding rectifying element. Each source of the plurality of second transistors receives a first power supply voltage. Each gate of the plurality of second transistors is connected to the output terminal.

  According to the present invention, each capacitor element is initially charged through the rectifier element and the second transistor before the boost operation is started, so that the boost time can be shortened. Furthermore, since the voltage higher than the first power supply voltage is applied to the gate of the second transistor after the start of the boosting operation, the off-leak current of the second transistor can be reduced. Accordingly, it is possible to prevent the finally obtained boosted voltage from being lowered.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a charge pump circuit 30 according to the first embodiment of the present invention. Referring to FIG. 1, charge pump circuit 30 includes a capacitive element 1 (1.1 to 1.n) for charging charges, and a transfer NMOS (N-channel MOS) transistor 2 (2 for transferring charges). 0.1 to 2.n), NMOS transistor 3 (3.1 to 3.n) and PMOS (P channel MOS) transistor 4 (4.1 to 4.n) for initial charging, and gate voltage control circuit 5 Including. A power supply voltage VDD is input to the input terminal Vin, and a voltage obtained by boosting the power supply voltage VDD is output from the output terminal Vout. The gate voltage control circuit 5 is supplied with a second power supply voltage VCC that is higher than the first power supply voltage VDD.

  FIG. 2 is a circuit diagram showing a configuration of one boosting cell Ck included in charge pump circuit 30 of FIG. FIG. 2 also shows an example of the configuration of the gate voltage control circuit 5 of FIG.

  Referring to FIGS. 1 and 2, charge pump circuit 30 includes n booster cells Ck between input terminal Vin and output terminal Vout (where n is an integer and k is an integer from 1 to n). Yes, the same applies hereinafter.) Can be considered to be connected in series. Each booster cell Ck includes capacitive elements 1. k and a transfer NMOS transistor. k and an NMOS transistor for initial charging; 3. k and PMOS transistor4. k. First, these connections will be described.

  1. NMOS transistor for transmission As for k, the gate, the drain, and the back gate are mutually connected. NMOS transistor 2. The source of k is connected to the boost node Pk. NMOS transistor 2. The drain of k is connected to the boost node Pk-1 of the previous boost cell Ck-1 (however, when k = 1, the input terminal Vin). Note that the boost node Pn in the final stage (k = n) corresponds to the output terminal Vout.

  Capacitance element 1. One end of k is connected to the boost node Pk. Capacitance element 1. k at the other end of the capacitive element 1. Except n, one of the clock signal CLK for driving the charge pump and the inverted clock signal CLKB having the opposite phase obtained by inverting the clock signal CLK is applied. Specifically, the other ends of the capacitive elements 1.1, 1.3,... Provided in the odd-numbered boost cells C1, C3,... Are input with the inverted clock signal CLKB (first clock signal). Connected to the terminal. The other ends of the capacitive elements 1.2, 1.4,... Provided in the even-numbered boost cells C2, C4,... Are connected to the input terminal of the clock signal CLK (second clock signal). Further, the capacitor (1) of the last stage (k = n) 1. The other end of n is connected to the ground node GND.

  2. NMOS transistor for initial charging As for k, the drain, the gate, and the back gate are connected to each other. Such a connection is called a diode connection. k source corresponds to the cathode of the rectifying element, and NMOS transistor 3. The drain of k corresponds to the anode of the rectifying element. 2. NMOS transistor The source of k is connected to the boost node Pk. In the case of a diode-connected NMOS transistor, a current flows from the drain to the source when the drain-source voltage is higher than the threshold voltage Vth.

  PMOS transistor4. The drain of k is the NMOS transistor 3. connected to the drain of k. PMOS transistor4. The source of k is connected to the input terminal Vin, and the power supply voltage VDD is applied. PMOS transistor 4. The k back gate and drain are connected to each other. PMOS transistor4. The gate of k is connected to the gate voltage control circuit 5. Note that the initial stage (k = 1) has almost no effect on the effect of the initial charging even if the PMOS transistor 4.1 is removed. In this case, the drain of the NMOS transistor 3.1 is connected to the input terminal Vin.

  The gate voltage control circuit 5 supplies the ground voltage to the PMOS transistor 4. PMOS transistor 4. by applying to the gate of k. Turn k on. At this time, the NMOS node 3. k and PMOS transistor4. The power supply voltage VDD is supplied via k. Therefore, the capacitive elements 1. k is initially charged to a voltage VDD−Vth obtained by subtracting the threshold voltage Vth of the NMOS transistor 3.1 from the power supply voltage VDD.

  After starting the boosting operation, the gate voltage control circuit 5 applies the external power supply voltage VCC higher than the power supply voltage VDD to the PMOS transistor 4. to the gate of k. In this case, the power supply voltage VCC is applied to the PMOS transistor 4. The gate voltage is sufficient to turn off k. As a result, the PMOS transistor 4. The k off-leakage current can be reduced.

  The gate voltage control circuit 5 can be composed of a comparator as shown in FIG. 2, for example. The comparator monitors the voltage at the output terminal Vout and the voltage at the input terminal Vin. When the voltage at the output terminal Vout becomes larger than the voltage at the input terminal Vin, the PMOS transistor 4. A voltage VCC is applied to the gate of k.

  FIG. 3 shows a transfer NMOS transistor 2. It is sectional drawing which shows the structure of k typically. In the charge pump circuit 30 of FIGS. 1 and 2, in order to suppress the back gate bias effect, the NMOS transistor 2. The k drain and the back gate are connected. For this reason, it is necessary to electrically isolate the back gates of the NMOS transistors 2 from each other. Therefore, NMOS transistor 2. k has a triple well structure as shown in FIG.

  Referring to FIG. 3, in the triple well structure, an N well 110 is provided on a P-type substrate 100, and a P well 120 is further provided on the N well 110. NMOS transistor 2. k is formed on the P-well 120. N + diffusion layers 122 and 123 in the P well 120 are used as a drain and a source. N + diffusion layer 122 which is a drain region is connected to P + diffusion layer 121 in P well 120 and N + diffusion layer 111 in N well 110. As a result, the NMOS transistor 2. The drain of k and the back gate are connected. At the time of boosting, the boosted N well 110 and the grounded P type substrate 100 are reversely biased, so that the N well 110 and the P well 120 are electrically separated from the P type substrate 100.

  FIG. 4 is a timing diagram schematically showing the waveforms of the clock signal CLK and the inverted clock signal CLKB applied to the charge pump circuit 30. The upper waveform of FIG. 4 shows the waveform of the clock signal CLK, and the lower waveform shows the waveform of the inverted clock signal CLKB. As shown in FIG. 4, both the clock signal CLK and the inverted clock signal CLKB are rectangular waves that oscillate between 0 and the power supply voltage VDD.

  Next, before describing the operation of the charge pump circuit 30 having the above-described configuration, the basic operation of the charge pump circuit will be described.

  FIG. 5 is a diagram for explaining the basic operation of the charge pump circuit. FIG. 6 is a circuit diagram showing a configuration of one booster cell CCk included in the charge pump circuit 40 of FIG.

  The charge pump circuit 40 shown in FIGS. 5 and 6 is a charge pump circuit described in IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, June 1976, p. 374-378, and is generally Dickson. It is called a charge pump circuit. The charge pump circuit 40 shows a basic configuration of the charge pump circuit, and includes a capacitive element 12 (12.1 to 12.n) for charging charges and a transfer NMOS transistor 13 (for transferring charges) ( 13.1-13.n). The capacitive element 12 and the NMOS transistor 13 correspond to the capacitive element 1 and the transmission NMOS transistor 2 in FIG. 1, respectively. Hereinafter, the configuration and operation of the Dickson charge pump circuit 40 will be described with reference to FIGS. 5 and 6.

  The charge pump circuit 40 has a configuration in which n booster cells CCk (where k is an integer from 1 to n) in FIG. 6 are connected in series between an input terminal Vin and an output terminal Vout. Each booster cell Ck includes a capacitive element 12. k and a transfer NMOS transistor 13. k. Transmission NMOS transistor 13. The gate and drain of k are connected, and the source is connected to the boost node Pk. Transmission NMOS transistor 13. The drain of k is connected to the boost node Pk-1 of the previous boost cell CCk-1 (however, when k = 1, the input terminal Vin).

  Further, the booster node Pk includes the capacitive elements 12. One end of k is connected. 11. Capacitance element at the final stage (k = n) capacitive elements excluding n 12.1-12. To drive the charge pump, the other end of n−1 is applied with a clock signal CLK as shown in FIG. 4 and an inverted clock signal CLKB obtained by inverting CLK. Clock signals CLK and CLKB are alternately applied to booster cells CC1 to CCn connected in series. The charge pump circuit 40 sequentially transmits the input charges to the boosting cells CC1 to CCn, so that the capacitive element 12. Charges n to obtain a boosted voltage.

  Next, the operation of the charge pump circuit 40 will be described with reference to FIGS. The power supply voltage VDD is input to the input terminal Vin of the charge pump circuit 40.

  First, at time t1 in FIG. 4, the inverted clock signal CLKB applied to the boosting node P1 of the boosting cell CC1 in the first stage (k = 1) becomes L level (0V). At this time, the capacitive element 12.1 is charged to the voltage VDD−Vth which is the difference between the power supply voltage VDD and the threshold voltage Vth of the transfer NMOS transistor 13 via the transfer NMOS transistor 13.1.

Next, at time t2 in FIG. 4, the inverted clock signal CLKB becomes H level (VDD), thereby raising the voltage of the boost node P1. The raised voltage Vclk at this time is given by assuming that the capacitance of each capacitive element 12 is Cp and the stray capacitance of each boosting node Pk is Cf.
Vclk = VDD × Cp / (Cp + Cf) (1)
It is expressed as

  The raised voltage is charged to the second stage (k = 2) capacitive element 12.2 via the transfer NMOS transistor 13.2, and the first stage capacitive element 12.1 and the second stage capacitive element 12.2. The charge is transferred until the two voltages are balanced. By repeating the same operation, the voltage at the second boosting node P2 finally becomes VDD−Vth + Vclk−Vth. After time t3, the above-described operation is repeated in each boost cell CCk, whereby the voltage of each boost node Pk rises, and the capacitive element 12.n of the final stage (k = n) of the n-stage charge pump. n is charged with a voltage of (VDD−Vth + (Vclk−Vth) × n).

  Next, the operation of the charge pump circuit 30 of the first embodiment will be described. Referring to FIGS. 1 and 2, the charge pump circuit 30 is configured by adding an initial charge NMOS transistor 3 and a PMOS transistor 4 to the charge pump circuit 40 of FIG. Therefore, the charge pump circuit 30 has the following function in addition to the function of the charge pump circuit 40 of FIG.

  First, immediately after the power is turned on, the capacitor elements 1. k is an NMOS transistor for initial charging; k and PMOS transistor4. When a charging current flows through k, the battery is charged to VDD-Vth. This eliminates the need for boosting to VDD-Vth in the initial stage of boosting operation, thereby shortening the boosting time in the initial stage of boosting.

  Further, in the charge pump circuit 30, when the output voltage increases due to the boosting operation, the capacitance elements 1.. k to the input terminal Vin is a PMOS transistor 4. Limited by k. As a result, a potential difference is generated between the drain and source of the PMOS transistor 4, so that an increase in voltage between the drain and source of the initial charging NMOS transistor 3 can be suppressed. Therefore, even when a MOSFET having a low threshold voltage Vth is used, the capacitive element 1. The movement of charges from k to the input terminal Vin is suppressed. Therefore, the charge pump circuit 30 can prevent the finally obtained boosted voltage from being lowered.

  Here, at the time of initial charging, electric charge is charged to the capacitive element 1 via the PMOS transistor 4 and the NMOS transistor 3. At this time, the gate width of the PMOS transistor 4 is set larger than the gate width of the NMOS transistor 3 for initial charging so that the initial charge does not deteriorate the function of initial charging due to the on-resistance of the PMOS transistor 4. Preferably, the gate width of the PMOS transistor 4 is 10 times or more that of the NMOS transistor 3.

[Modification of Embodiment 1]
FIG. 7 is a circuit diagram showing a configuration of a charge pump circuit 31 which is a modification of the charge pump circuit 30 of FIG. The charge pump circuit 31 of FIG. 7 includes a PMOS transistor 6 (6.1 to 6.n) in place of the transmission NMOS transistor 2 (2.1 to 2.n) of FIG. Different from the charge pump circuit 30 of FIG. Further, the charge pump circuit 31 includes a PMOS transistor 7 (7.1 to 7.n) instead of the NMOS transistor 3 (3.1 to 3.n) for initial charging shown in FIG. 1 different from the charge pump circuit 30 of FIG. As described above, even if the NMOS transistor is changed to the PMOS transistor, the charge pump circuit 31 operates in the same manner as the charge pump circuit 30 of FIG. 1 and has the same effect.

  In the case of FIG. k (where k is an integer from 1 to n), the drain, the gate, and the back gate are connected to each other and each PMOS transistor 6. The drain of k is also connected to the boost node Pk. PMOS transistor 6. The source of k is connected to the previous boost node Pk−1 (when k = 1, it is connected to the input terminal Vin). Each PMOS transistor 7. k drain, gate and back gate are connected to each other and each PMOS transistor 7. The drain of k is also connected to the boost node Pk. 6. Each PMOS transistor The source of k is a PMOS transistor 4. connected to the drain of k. Since the other points of FIG. 7 are the same as those of charge pump circuit 30 of FIG. 1, common portions are denoted by the same reference numerals and description thereof will not be repeated.

  8 shows a transfer PMOS transistor 6. It is sectional drawing which shows the structure of k typically. In the charge pump circuit 30 of FIG. 7, in order to avoid the back gate bias effect, the PMOS transistor 6. The k drain and the back gate are connected. Therefore, in order to electrically isolate the back gates of the PMOS transistors 6 from each other, the PMOS transistors 6. k has an N-well structure as shown in FIG.

  Referring to FIG. 8, N well 110 is provided on P type substrate 100, and PMOS transistor 6. k is formed on the N well 110. The P + diffusion layers 112 and 113 in the N well 110 are used as a drain and a source. The P + diffusion layer 112 which is a drain region is connected to the N + diffusion layer 111 in the N well 110. As a result, the PMOS transistor 6. The drain of k and the back gate are connected. At the time of boosting, the boosted N-well 110 and the grounded P-type substrate 100 are reverse-biased, so that the N-well 110 is electrically isolated from the P-type substrate 100.

[Embodiment 2]
FIG. 9 is a circuit diagram showing a configuration of the charge pump circuit 32 according to the second embodiment of the present invention. Referring to FIG. 9, charge pump circuit 32 includes capacitive element 1 (1.1 to 1.n) for charging charges, and transfer NMOS transistor 2 (2.1 to 2) for transferring charges. N), and NMOS transistor 3 (3.1 to 3.n) for initial charging and PMOS transistor 4 (4.1 to 4.n). The charge pump circuit 32 does not include the gate voltage control circuit shown in FIG. 1, but instead differs from the charge pump circuit 30 shown in FIG. 1 in that each gate of the PMOS transistor 4 is connected to the output terminal. Since the configuration and connection of capacitive element 1, transmission NMOS transistor 2, and initial charging NMOS transistor 3 are the same as those in the first embodiment, description thereof will not be repeated.

  As in the first embodiment, each PMOS transistor 4. The source of k (where k is an integer from 1 to n) is connected to the input terminal Vin. Each PMOS transistor 4. The k drain and the back gate are connected to each other. 3. Each PMOS transistor The drain of k is an NMOS transistor for initial charging. connected to the drain of k.

  The difference from the first embodiment is that each PMOS transistor 4. The gate of k is connected to the output terminal Vout. Therefore, in the initial state before the start of the boost operation, the voltage at the output terminal Vout is 0. The gate voltage of k becomes 0. As a result, the PMOS transistor 4. Since k is turned on, the capacitive element 1 is initially charged via the PMOS transistor 4 and the NMOS transistor 3. In order not to deteriorate the function of initial charging, the gate width of the PMOS transistor 4 is preferably larger than the gate width of the NMOS transistor 3, preferably 10 times or more.

  On the other hand, when the voltage at the output terminal Vout becomes higher than the voltage at the input terminal Vin after the boost operation starts, the PMOS transistor 4. k goes off. Thus, by using the voltage of the output terminal Vout of the final stage (k = n) having the highest voltage in the charge pump circuit 32 as the gate voltage, the PMOS transistor 4 can be reliably turned off. Therefore, it is possible to reduce off-leakage current. Further, since the gate voltage control circuit 5 of FIG. 1 is not required, the circuit scale can be reduced as compared with the first embodiment.

[Modification of Embodiment 2]
FIG. 10 is a circuit diagram showing a configuration of a charge pump circuit 33 which is a modification of the charge pump circuit 32 of FIG. The charge pump circuit 33 of FIG. 10 includes a PMOS transistor 6 (6.1 to 6.n) instead of the transmission NMOS transistor 2 (2.1 to 2.n) of FIG. Different from the charge pump circuit 32 of FIG. Further, the charge pump circuit 33 includes a PMOS transistor 7 (7.1-7.n) in place of the NMOS transistor 3 (3.1-3.n) for initial charging shown in FIG. Different from the second charge pump circuit 32. As described above, even if the NMOS transistor is changed to the PMOS transistor, the charge pump circuit 33 operates in the same manner as the charge pump circuit 32 in FIG.

  In the case of FIG. k (where k is an integer from 1 to n), the drain, the gate, and the back gate are connected to each other and each PMOS transistor 6. The drain of k is also connected to the boost node Pk. PMOS transistor 6. The source of k is connected to the previous boost node Pk−1 (when k = 1, it is connected to the input terminal Vin). Each PMOS transistor 7. k drain, gate and back gate are connected to each other and each PMOS transistor 7. The drain of k is also connected to the boost node Pk. 6. Each PMOS transistor The source of k is a PMOS transistor 4. connected to the drain of k. The other points of FIG. 10 are the same as those of charge pump circuit 32 of FIG. 9, and therefore, common portions are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 3]
FIG. 11 is a circuit diagram showing a configuration of charge pump circuit 34 according to the third embodiment of the present invention. A charge pump circuit 34 in FIG. 11 is obtained by applying the configuration of the second embodiment of the present invention to a charge pump circuit driven by a four-phase clock.

  Referring to FIG. 11, charge pump circuit 34 transfers capacitance to capacitive element 1 and capacitive element 1 (1.1 to 1.n) for charging the charge, as in the second embodiment. Transfer NMOS transistor 2 (2.1-2.n), initial charging NMOS transistor 3 (3.1-3.n) and PMOS transistor 4 (4.1-4.n) Including. On the other hand, unlike the case of the second embodiment, the charge pump circuit 34 further includes capacitive elements 21 (21.1 to 21.2) connected to the gates of the transmission NMOS transistors 2 (2.1 to 2.n), respectively. n) and an auxiliary transmission NMOS transistor 22 (21.1 to 21.n) for transferring charges to the capacitive element 21.

  The charge pump circuit 34 can be considered as a configuration in which n booster cells are connected in series between the input terminal Vin and the output terminal Vout. The kth booster cell (where k is an integer from 1 to n) k, NMOS transistor 2. k, NMOS transistor 3, PMOS transistor 4. k, capacitive element 21. k, and NMOS transistor 22. including k. First, these connections will be described.

  1. NMOS transistor for transmission The drain and back gate of k are connected to the previous boost node Pk−1 (where k = 1, the input terminal Vin). NMOS transistor 2. The source of k is connected to the boost node Pk.

  Auxiliary transmission NMOS transistor 22. The drain and back gate of k are connected to the previous boost node Pk−1 (where k = 1, the input terminal Vin). NMOS transistor 22. The source of k is the NMOS transistor 22. connected to k gates. The NMOS transistor 22. The gate of k is connected to the boost node Pk.

  Capacitance element 1. One end of k is connected to the boost node Pk. A clock signal # 1 (first clock signal) is supplied to the other end of the odd-numbered capacitive element 1 except for the final stage (k = n), and a clock signal is supplied to the other end of the even-numbered capacitive element 1. # 3 (second clock signal) is supplied. Final stage capacitive element 1. The other end of n is grounded.

  Capacitive element 21. k is connected to the transfer NMOS transistor 2. connected to k gates. The other end of the odd-numbered capacitive element 21 is supplied with a clock signal # 4 (third clock signal), and the other end of the even-numbered capacitive element 21 is supplied with the clock signal # 2 (fourth clock signal). Is supplied.

  2. NMOS transistor for initial charging k and PMOS transistor4. Since the connection of k is the same as that of the second embodiment, description thereof will not be repeated.

Next, the operation of the charge pump circuit 34 of the third embodiment will be described.
FIG. 12 is a timing chart schematically showing waveforms of clock signals # 1 to # 4 applied to the charge pump circuit 34. As shown in FIG. FIG. 12 shows clock signals # 1, # 2, # 3, and # 4 in order from the top. The clock signals # 1 to # 4 are all rectangular waves that vibrate between 0 and the power supply voltage VDD. The clock signal # 1 has an opposite phase to the clock signal # 4, and the clock signal # 2 has an opposite phase to the clock signal # 3. The clock signal # 1 has the same cycle as the clock signal # 2, rises before the clock signal # 2 rises, and falls after the clock signal # 4 falls.

  Referring to FIGS. 11 and 12, it is assumed that capacitor element 1.1 at the first stage is charged before time t1. Further, since the clock signal # 3 is at the H level, the NMOS transistor 22.2 is on. In this state, clock signal # 1 becomes H level at time t1, so that the voltage of capacitive element 1.1 is raised and capacitive element 21.2 for gate charging is charged.

  At the next time t2, the clock signal # 1 is at the H level, the clock signal # 2 is at the H level, and the clock signal # 3 is at the L level. As a result, the gate voltage of the NMOS transistor 2.2 is raised, so that the NMOS transistor 2.2 becomes conductive. Then, the charge of the capacitive element 1.1 is transferred to the second-stage capacitive element 1.2 through the NMOS transistor 2.2.

  At the next time t3, while the clock signal # 1 is at the H level, the clock signal # 2 is at the L level and the clock signal # 3 is at the H level. As a result, the voltage of the capacitor element 1.2 in the second stage is raised, and the capacitor element 21.3 for gate charging is charged.

  At the next time t4, while the clock signal # 3 is at the H level, the clock signal # 1 is at the H level and the clock signal # 4 is at the L level. As a result, the gate voltage of the NMOS transistor 2.3 is raised, so that the NMOS transistor 2.3 becomes conductive. Then, the electric charge of the capacitive element 1.2 is transferred to the third-stage capacitive element 1.3 through the NMOS transistor 2.3.

  At the next time t5, while the clock signal # 3 is at the H level, the clock signal # 1 is at the L level and the clock signal # 4 is at the H level. As a result, the voltage 1.3 of the capacitor element at the third stage is raised, and the capacitor element 21.4 for gate charging is charged. Thereafter, by repeating the same operation, the power supply voltage can be boosted with higher efficiency than in the case of the two-phase clock system of the second embodiment.

  Here, as in the case of the second embodiment, each capacitor element 1... Immediately after the power is turned on via the NMOS transistor 3 and the PMOS transistor 4 for initial charging. k is charged to VDD-Vth. For this reason, it is not necessary to boost to VDD-Vth at the beginning of the boosting operation, and the boosting time at the initial boosting time is shortened.

  Further, when the output voltage rises after the charge pump circuit 34 starts boosting, each capacitor element 1. A leak current flowing from k to the input terminal Vin is limited by the PMOS transistor 4. As described above, even when the threshold voltage Vth of the MOSFET is low, the off-leakage current is suppressed. Therefore, as in the case of the second embodiment, it is possible to prevent the finally obtained boosted voltage from being lowered.

[Comparison with comparative example]
FIG. 13 is a circuit diagram showing a configuration of a charge pump circuit 41 which is a comparative example of the charge pump circuit 32 of the second embodiment.

  FIG. 14 is a circuit diagram showing a configuration of one booster cell CCCk included in the charge pump circuit 41 of FIG. In the charge pump circuit 41, a plurality of booster cells CCCk (where k is an integer from 1 to n) are connected in series between an input terminal Vin and an output terminal Vout.

  Referring to FIG. 13 and FIG. 14, the charge pump circuit 41 includes a capacitive element 12 (12.1 to 12.n) for charging a charge and a transfer NMOS transistor 14 (14. 1 to 14.n) and an initial charge NMOS transistor 15 (15.1 to 15.n). The charge pump circuit 41 is the charge pump circuit 32 of FIG. 9 and does not include the PMOS transistor 4. That is, each NMOS transistor 15. The drain of k is different from that of FIG. It is directly connected to the input terminal Vin without going through k. Therefore, in the case of FIG. 13, an off-leakage current 19 flows from the capacitive element 12 to the input terminal Vin via the NMOS transistor 15 at the time of boosting. The off-leakage current 19 increases as the output voltage becomes higher.

  Since the connection of other NMOS transistors 15 is the same as that of NMOS transistor 3 of FIG. 9, description thereof will not be repeated. Also, the configuration and connection of capacitive element 12 and NMOS transistor 14 are similar to those of corresponding capacitive element 1 and NMOS transistor 2 of FIG. 9, and therefore description thereof will not be repeated. Hereinafter, the simulation result of the charge pump circuit 32 according to the second embodiment in FIG. 9 and the simulation result of the charge pump circuit 41 in the comparative example in FIG. 13 will be compared with reference to FIGS.

  FIG. 15 is a graph showing the leakage current of the initial charging NMOS transistor of each boosting cell with respect to the boosting voltage. The horizontal axis in FIG. 15 represents the boosted voltage (the voltage at the output terminal Vout in FIGS. 9 and 15), and the vertical axis in FIG. 15 represents the initial charge NMOS transistor (reference numeral 3 in FIG. 9 and reference numeral 15 in FIG. 15). Represents the leakage current. As shown in FIG. 15, the leakage current (solid line 8 in FIG. 15) when the charge pump circuit 32 of the second embodiment is used is the leakage current (broken line 9 in FIG. 15) in the charge pump circuit 41 of the comparative example. ). In particular, the difference between the two becomes more significant as the boosted voltage increases.

  FIG. 16 is a graph showing the time change of the boosted voltage of the charge pump circuit from the start of boosting to the completion of boosting. As shown in FIG. 16, when comparing the boosting speed when the boosted voltage rises, the boosting speed when the charge pump circuit 32 of the second embodiment is used (solid line 10 in FIG. 16) is the charge pump circuit of the comparative example. This is equivalent to the boosting speed when 41 is used (broken line 11 in FIG. 16). On the other hand, with regard to the reached voltage when boosting is completed, the reached voltage when the charge pump circuit 32 of the second embodiment is used (solid line 10 in FIG. 16) is the same as when the charge pump circuit 41 of the comparative example is used (FIG. 16). Is larger than the ultimate voltage of the broken line 11). Thus, it can be seen that the charge pump circuit 32 of the second embodiment can prevent the finally obtained boosted voltage from being lowered.

  FIG. 17 is a graph showing the time change of the boosted voltage of the charge pump circuit from the start of boosting to the completion of boosting. 17, the simulation result of the Dickson charge pump circuit 40 in FIG. 5 (solid line 16 in FIG. 17) and the simulation result of the charge pump circuit 41 in the comparative example in FIG. 13 (broken line 17 in FIG. 17) are compared. .

  As shown in FIG. 17, with respect to the boosting speed when the boosted voltage rises, the boosting speed of the charge pump circuit 41 of the comparative example (broken line 17 in FIG. 17) is the same as that of the Dickson charge pump circuit 40 (solid line 16 in FIG. 17). Faster than the pressurization speed. This is because in the charge pump circuit 41 of the comparative example, the capacitor element 1 is initially charged before the start of boosting. On the other hand, regarding the reached voltage at the completion of boosting, the reached voltage of the charge pump circuit 41 (broken line 17 in FIG. 17) of the comparative example is lower than the reached voltage of the Dickson charge pump circuit 40 (solid line 16 in FIG. 17). This is because in the charge pump circuit 41 of the comparative example, the off-leakage current 19 via the initial charge NMOS transistor 15 cannot be ignored. Therefore, according to the present invention, it is understood that the boosting speed equivalent to that of the charge pump circuit 41 of the comparative example can be achieved, and the decrease of the boosted voltage observed in the charge pump circuit 41 of the comparative example can be prevented.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a circuit diagram showing a configuration of a charge pump circuit 30 according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of one booster cell Ck included in the charge pump circuit 30 of FIG. 1. 1. NMOS transistor for transmission It is sectional drawing which shows the structure of k typically. 4 is a timing chart schematically showing waveforms of a clock signal CLK and an inverted clock signal CLKB applied to the charge pump circuit 30. FIG. It is a figure for demonstrating the basic operation | movement of a charge pump circuit. FIG. 6 is a circuit diagram showing a configuration of one booster cell CCk included in the charge pump circuit 40 of FIG. 5. FIG. 3 is a circuit diagram showing a configuration of a charge pump circuit 31 which is a modification of the charge pump circuit 30 of FIG. 1. 5. Transmission PMOS transistor It is sectional drawing which shows the structure of k typically. It is a circuit diagram which shows the structure of the charge pump circuit 32 of Embodiment 2 of this invention. FIG. 10 is a circuit diagram showing a configuration of a charge pump circuit 33 which is a modification of the charge pump circuit 32 of FIG. 9. It is a circuit diagram which shows the structure of the charge pump circuit 34 of Embodiment 3 of this invention. 4 is a timing chart schematically showing waveforms of clock signals # 1 to # 4 applied to the charge pump circuit 34. FIG. FIG. 6 is a circuit diagram showing a configuration of a charge pump circuit 41 which is a comparative example of the charge pump circuit 32 of the second embodiment. FIG. 14 is a circuit diagram showing a configuration of one booster cell CCCk included in the charge pump circuit 41 of FIG. 13. It is a graph showing the leakage current of the NMOS transistor for initial charge of each boosting cell with respect to a boosting voltage. It is a graph showing the time change of the boost voltage of the charge pump circuit from the boost start to the boost completion. It is a graph showing the time change of the boost voltage of the charge pump circuit from the boost start to the boost completion.

Explanation of symbols

  1,21 Capacitance element, 2 transfer NMOS transistor, 3 initial charge NMOS transistor, 4 initial charge amount PMOS transistor, 5 gate voltage control circuit, 6 transfer PMOS transistor, 7 initial charge NMOS transistor, 22 auxiliary transfer NMOS Transistor, 30 to 34 charge pump circuit, CLK clock signal, CLKB inverted clock signal, GND ground node, Pk boost node, VCC external power supply voltage, VDD power supply voltage, Vin input terminal, Vout output terminal, Vth threshold voltage.

Claims (8)

A plurality of first transistors connected in series between an input terminal receiving a first power supply voltage and an output terminal, each transferring charge from the input terminal toward the output terminal;
A plurality of capacitance elements provided corresponding to the plurality of first transistors, each connected to an output node of the corresponding first transistor, and storing transferred charges;
A plurality of rectifying elements provided corresponding to the plurality of first transistors, each cathode being connected to an output node of the corresponding first transistor;
Each of the plurality of rectifying elements is provided correspondingly, each drain is connected to the anode of the corresponding rectifying element, and each source has a plurality of second P-channel MOS type receiving the first power supply voltage. A transistor,
The second power supply voltage higher than the first power supply voltage is received, and after the start of charge transfer by the plurality of first transistors, the second power supply voltage is output to each gate of the plurality of second transistors. A charge pump circuit comprising a control circuit.   The control circuit detects a voltage of the output terminal, and when the voltage of the output terminal is larger than the first power supply voltage, the control circuit supplies the second power supply voltage to each gate of the plurality of second transistors. The charge pump circuit according to claim 1, which outputs the charge pump circuit. A plurality of first transistors connected in series between an input terminal receiving a first power supply voltage and an output terminal, each transferring charge from the input terminal toward the output terminal;
A plurality of capacitance elements provided corresponding to the plurality of first transistors, each connected to an output node of the corresponding first transistor, and storing transferred charges;
A plurality of rectifying elements provided corresponding to the plurality of first transistors, each cathode being connected to an output node of the corresponding first transistor;
Provided corresponding to each of the plurality of rectifying elements, each drain being connected to an anode of the corresponding rectifying element, each source receiving the first power supply voltage, and each gate being connected to the output terminal. A charge pump circuit comprising a plurality of P-channel MOS type second transistors. Each of the plurality of rectifying elements is a MOS transistor in which a gate and a drain are connected to each other,
4. The charge pump circuit according to claim 1, wherein gate widths of the plurality of second transistors are larger than gate widths of the plurality of rectifying elements. 5. Each of the plurality of first transistors is a MOS transistor in which a gate and a drain are connected to each other,
The plurality of capacitive elements include a first capacitive element corresponding to a first transistor connected to the output terminal, and a plurality of second capacitive elements other than the first capacitive element,
The other end of the second capacitor element, one end of which is connected to the output node of the odd-numbered first transistor, receives the first clock signal,
5. The second capacitor element having one end connected to the output node of the even-numbered first transistor receives a second clock signal having a phase opposite to that of the first clock signal. Charge pump circuit.   The charge pump circuit according to claim 5, wherein a back gate and a drain of each of the plurality of first and second transistors and the plurality of rectifying elements are connected to each other. The charge pump circuit receives first to fourth clock signals,
The first clock signal is in anti-phase with the third clock signal;
The second clock signal is in anti-phase with the fourth clock signal;
The first clock signal has the same period as the fourth clock signal, rises before the fourth clock signal rises, falls after the fourth clock signal falls,
Each of the plurality of first transistors is an N-channel MOS transistor,
The plurality of capacitive elements include a first capacitive element corresponding to a first transistor connected to the output terminal, and a plurality of second capacitive elements other than the first capacitive element,
The other end of the second capacitor having one end connected to the output node of the odd-numbered first transistor receives the first clock signal,
The other end of the second capacitor element having one end connected to the output node of the even-numbered first transistor receives the second clock signal,
The charge pump circuit
N provided corresponding to each of the plurality of first transistors, each connected between the gate and drain of the corresponding first transistor, and each gate connected to the source of the corresponding first transistor A plurality of third MOS transistors of the channel;
A plurality of third capacitors provided corresponding to the plurality of first transistors, respectively.
One end of the third capacitive element corresponding to the odd-numbered first transistor is connected to the gate of the corresponding first transistor, and the other end receives the third clock signal,
5. The charge according to claim 4, wherein one end of the third capacitor element corresponding to the even-numbered first transistor is connected to the gate of the corresponding first transistor, and the other end receives the fourth clock signal. Pump circuit.   The charge pump circuit according to claim 7, wherein a back gate and a drain of each of the plurality of first to third transistors and the plurality of rectifying elements are connected to each other.

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