JP2008198985A - Booster circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a low power consumption and a layout area reduction in a booster circuit by suppressing degradation in charge transfer efficiency, and controlling an n-well electric potential of a triple-well structured switching element. <P>SOLUTION: The booster circuit has first booster cell arrays 102, 103, 104, second booster cell arrays 105, 106, 107, and analog comparators 117, 118, 119 comparing each of potentials in the same steps of the booster cells to select and output the lower potential or the higher potential. The n-well electric potential is controlled by the output potentials of these analog comparators. Consequently, the n-well electric potential can be controlled and the layout can be made common in the n-well region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a booster circuit using a switching element having a triple well structure.

  In recent years, a flash memory, which is one of nonvolatile semiconductor memory devices, has been required to read and rewrite data at a single power supply voltage or a low power supply voltage, and on-chip when performing each operation. There is a need for a boost circuit that supplies a positive or negative boost voltage. Also in the CMOS process, the power supply voltage generated by the booster circuit is used to improve the characteristics of the analog circuit.

  Conventionally, a booster circuit using a switching element having a triple well structure is known (see Patent Documents 1 to 3).

  FIG. 25 shows an example of a conventional booster circuit. In FIG. 25, reference numeral 901 denotes a booster circuit for generating an output terminal voltage (boosted voltage) Vpump by inputting a two-phase clock signal CLK1 and CLK2 and performing a boosting operation. Reference numerals 902, 903, and 904 are three-stage configuration examples, a booster cell in which CLK1 is input to the odd-numbered stage and CLK2 is input to the even-numbered stage, 905 is a backflow prevention circuit that prevents backflow of the boosted voltage Vpump, 906 Is a charge transfer transistor functioning as a switching element, 907 is a P well (PW) of the charge transfer transistor 906, 908 is a deep N well (NT) including the P well 907, 909 is between the P well 907 and the N well 908 The parasitic diode 910 is a boosting capacitor that boosts the output terminals of the boosting cells 902, 903, and 904, and 911, 912, 913, and 914 are input / output terminals of the boosting cell. As shown in FIG. 25, the P well 907 and the N well 908 of each charge transfer transistor 906 of the boost cells 902 to 904 are connected to the source of each charge transfer transistor 906, and these are set to the same potential.

  FIG. 26 is a waveform diagram of the two-phase clock signals CLK1 and CLK2 in the booster circuit 901 of FIG. The operation of the booster circuit 901 in FIG. 25 will be briefly described with reference to FIG.

  First, in the state at time T1, CLK1 becomes “H” (power supply voltage Vdd), CLK2 becomes “L” (ground voltage Vss), and the potentials of the input / output terminals 912 and 914 are boosted. At the same time, charges are transferred from the input / output terminal 912 to the input / output terminal 913 and from the input / output terminal 914 to the output terminal of the booster circuit 901 via the charge transfer transistors 906 of the booster cell 903 and the backflow prevention circuit 905, respectively. The output terminal voltage Vpump of the input / output terminal 913 and the booster circuit 901 rises. At this time, since the P well 907 of each of the booster cell 903 and the backflow prevention circuit 905 has the same potential as the source terminal of the charge transfer transistor 906, the substrate bias effect of the charge transfer transistor 906 is suppressed, and the charge transfer efficiency is reduced. Can be suppressed.

  When the charge transfer period Ttrans elapses from time T1 and the state becomes time T2, CLK2 becomes “H” and CLK1 becomes “L”, and the potential of the input / output terminal 913 is boosted. At the same time, charge is transferred from the input / output terminal 913 to the input / output terminal 914 via the charge transfer transistor 906 of the booster cell 904. At this time, since the P well 907 of the booster cell 904 is set to the same potential as the source terminal of the charge transfer transistor 906, the substrate bias effect of the charge transfer transistor 906 can be suppressed, and the decrease in charge transfer efficiency can be suppressed.

  When entering the state at time T3, the operation is the same as at time T1.

As described above, according to the booster circuit 901 of FIG. 25, the substrate bias effect can be suppressed, and the decrease in charge transfer efficiency during the boosting operation can be suppressed.
JP-A-8-125133 Japanese Patent Laid-Open No. 11-283392 US Pat. No. 6,100,357

  However, since the conventional booster circuit 901 connects the source of the charge transfer transistor 906 and the N-well 908, the parasitic capacitance formed by the N-well 908 according to the voltage transition of the clock signals CLK1 and CLK2 is changed to the clock signal CLK1. As a result of charging and discharging with the voltage transition width of CLK2, there is a problem that current consumption increases.

  Further, since the charge supplied by the clock signals CLK1 and CLK2 is used as the charge / discharge charge of the N well 908, there is a problem that the boosting efficiency is lowered.

  Further, in order to connect the source of the charge transfer transistor 906 and the N well 908, it is necessary to separate the N well 908 between the charge transfer transistors 906, resulting in an increase in layout area.

  An object of the present invention is to provide a booster circuit that can suppress the substrate bias effect of the switching element used in each booster cell, and can suppress current consumption and layout area.

  In order to achieve the above object, the booster circuit according to the present invention fixes the charge / discharge charge amount between the N well and the substrate by fixing the potential of the N well of each boost cell to the input potential or output potential of each stage of the boost cell. The boosting efficiency is thus reduced.

  More specifically, according to the first aspect of the present invention, the first well region of the first conductivity type is provided on the substrate, and the second well region of the second conductivity type is provided in the first well region. One or more switching elements are provided in the first well region or the second well region, and the one or more switching elements are turned on between the first terminal and the second terminal. In a booster circuit including a booster cell that is turned off and transfers charges from the first terminal to the second terminal, a first booster cell array that includes the booster cells in N stages (N ≧ 1) And an output potential of the second boost cell array composed of the M booster cells (M ≧ 1) and the i booster cell (1 ≦ i ≦ N) of the first boost cell column. And the output potential of the booster cell at the i-th stage (1 ≦ i ≦ M) of the second booster cell row Or an analog comparison circuit that outputs a lower potential, and the output potential of the analog comparison circuit is set to the (i + 1) th step-up cell or the i-th step of the first and second step-up cell columns. The voltage is applied to the first well region of the one or more switching elements provided in one or more of the boosting cells or the boosting cells before the i-th stage.

  According to a second aspect of the present invention, the first well region of the first conductivity type is provided on the substrate, the second well region of the second conductivity type is provided in the first well region, and the first well region is provided. One or more switching elements are provided in one or both of the well region and the second well region, and the one or more switching elements are provided between the first terminal and the second terminal. In a booster circuit including a booster cell that transfers charge from the first terminal to the second terminal by turning on / off the first booster configured from the booster cells in N stages (N ≧ 1) A cell column, a second boost cell column composed of M booster cells (M ≧ 1), and the i booster cell (1 ≦ i ≦ N) of the first boost cell column. Of the input potential and the input potential of the booster cell in the i-th stage (1 ≦ i ≦ M) of the second booster cell row An analog comparison circuit that outputs a high-side potential or a low-side potential, and outputs the output potential of the analog comparison circuit from the i + 1-th boost cell or i-th stage of the first and second boost cell arrays The voltage is applied to the first well region of the one or more switching elements provided in one or more of the boosting cells or the boosting cells before the i-th stage.

  According to a third aspect of the present invention, the first well region of the first conductivity type is provided on the substrate, the second well region of the second conductivity type is provided in the first well region, and the first well region is provided. One or more switching elements are provided in the well region or the second well region, and the first terminal and the second terminal are turned on and off by the one or more switching elements, and the first terminal is turned on and off. In a booster circuit including a booster cell for transferring charge from one terminal to the second terminal and a backflow prevention circuit, a first circuit composed of N stages (N ≧ 1) of the booster cells and the backflow prevention circuit. , The second booster cell row composed of the M booster cells (M ≧ 1) and the backflow prevention circuit, and the i-th (1 ≦ 1) of the first booster cell row, respectively. The output potential of the booster cell at i ≦ N and the i-th stage (1 ≦ i ≦ M) of the second booster cell row And an analog comparison circuit that outputs a higher potential or a lower potential among the output potentials of the booster cells, and the output potential of the analog comparison circuit is set to the first and second booster cell rows. The first of the one or more switching elements provided in one or more of the backflow prevention circuit, the (i + 1) th booster cell, the ith booster cell, or the booster cell prior to the ith stage. It was decided to apply to one well region.

  According to a fourth aspect of the present invention, the first well region of the first conductivity type is provided on the substrate, the second well region of the second conductivity type is provided in the first well region, and the first well region is provided. One or more switching elements are provided in one or both of the well region and the second well region, and the one or more switching elements are provided between the first terminal and the second terminal. In a booster circuit having a booster cell and a backflow prevention circuit for transferring charge from the first terminal to the second terminal by turning on / off the N-stage (N ≧ 1) booster cell and the backflow prevention A first booster cell array composed of a circuit, a second booster cell array composed of M stages (M ≧ 1) of the booster cells and the backflow prevention circuit, and each of the first booster cells. The intermediate potential of the backflow prevention circuit of the column and the backflow prevention circuit of the second boosting cell row An analog comparison circuit that outputs a high-side potential or a low-side potential among the inter-potentials, and outputs the output potential of the analog comparison circuit to the backflow prevention circuit of the first and second boosting cell rows or Applying to the first well region of the one or more switching elements provided in one or more of the boosting cells included in the first boosting cell row and the second boosting cell row; did.

  According to a fifth aspect of the present invention, the first well region of the first conductivity type is provided on the substrate, the second well region of the second conductivity type is provided in the first well region, and the first well region is provided. One or more switching elements are provided in one or both of the well region and the second well region, and the one or more switching elements are provided between the first terminal and the second terminal. In a booster circuit having a booster cell and a backflow prevention circuit for transferring charge from the first terminal to the second terminal by turning on / off the N-stage (N ≧ 1) booster cell and the backflow prevention A first booster cell array composed of a circuit, a second booster cell array composed of the M booster cells (M ≧ 1) and the backflow prevention circuit, and the first and second booster cells, respectively. Booster cells in the i-th stage (1 ≦ i ≦ N) of the booster cell rows or backflow prevention circuits An analog comparison circuit that compares the input potentials of the first and second output potentials of the input potentials, and outputs the higher potential or the lower potential of the input potentials. The one or more switching elements provided in one or more of the backflow prevention circuit of the cell row, the booster cell at the (i + 1) th stage, the booster cell at the ith stage, or the booster cell before the ith stage. The voltage was applied to the first well region.

  According to a sixth aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, the second well region and the second well region are arranged such that the second well region and the first terminal have the same potential. And the first terminal were connected to each other.

  According to a seventh aspect of the present invention, in the booster circuit according to any of the first to fifth aspects, the second well region and the first well region have the same potential so that the second well region and the first well region have the same potential. The region and the first well region were connected to each other.

  According to an eighth aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, the analog comparison circuit includes a first well region of a first conductivity type on the substrate, and the first A second well region of the second conductivity type in the well region, and one or more switching elements in the first well region or in the second well region, and the boosting step It is provided for each stage of the cell.

  According to a ninth aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, the analog comparison circuit includes a first well region of a first conductivity type on the substrate, and the first A second well region of a second conductivity type in the well region, and one or more switching elements in the first well region or in the second well region. One or more second booster cell columns are provided, and are provided for each arbitrary number of booster cells.

  According to a tenth aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, a diode means is provided between the first terminal of the booster cell and the first well region.

  According to an eleventh aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, the first well region of the first and second booster cell columns has the same potential. The layout of the first well region of the above switching elements is shared.

  According to a twelfth aspect of the present invention, in the booster circuit according to any one of the first to fifth aspects, the first well region in the first and second booster cell columns has the same potential. The layout of the first well region of the switching element and the layout of the first well region of the analog comparison circuit are made common.

  According to a thirteenth aspect of the invention, in the booster circuit according to any one of the first to fifth aspects, the first of the one or more switching elements of the i-th boost cell in the first boost cell row. The layout of the well region and the layout of the first well region of the first element of the analog comparison circuit are shared, and the one or more switching elements of the i-th boost cell in the second boost cell row The layout of the first well region and the layout of the first well region of the second element of the analog comparison circuit are made common.

  According to the first aspect of the present invention, the charge / discharge charge amount of the first well type first well region can be made smaller than the voltage swing of the clock signal signal, and the apparent parasitic capacitance between the first well region and the substrate can be reduced. Since it can be reduced, current consumption during the boosting operation can be suppressed. Further, since the apparent parasitic capacitance between the first well region and the substrate can be reduced, the boosting efficiency can be improved. Further, by controlling the potentials of the first well regions of the plurality of booster cells with one analog comparison circuit, an increase in layout area due to the analog comparison circuit can be suppressed.

  According to the second aspect of the present invention, well control using the input potential of the first stage booster cell is possible, and the load capacitance connected to the booster capacitor of each stage can be equalized. As a result, a more stable boosting operation is possible.

  According to the invention of claim 3, it is possible to control the potential of the first well region of the backflow prevention circuit, and it is possible to suppress a decrease in charge transfer efficiency in the backflow prevention circuit.

  According to the fourth aspect of the invention, the well control using the intermediate potential of the backflow prevention circuit is possible, and the load capacitance connected to the boosting capacitance of each stage can be equalized. As a result, a more stable boosting operation is possible.

  According to the fifth aspect of the present invention, well control using the input potential of the first-stage booster cell is possible, and the load capacitance connected to the booster capacitor at each stage can be equalized. As a result, a more stable boosting operation is possible.

  According to the sixth aspect of the present invention, by connecting the input terminal of the charge transfer transistor (switching element) in the boosting cell and the second well region, a decrease in the current drive capability of the switching element due to the substrate bias effect is suppressed. be able to.

  According to the invention of claim 7, since the well region of the N-channel transistor and the P-channel transistor can be made common by setting the first well region and the second well region to the same potential, the layout area can be reduced. Is possible.

  According to the eighth aspect of the present invention, by providing the analog comparison circuits in all the stages, it is possible to make the parasitic capacitances of the boosting cells the same and to improve the design easiness.

  According to the ninth aspect of the present invention, by providing the analog comparison circuit in an arbitrary number of stages, it is possible to suppress an increase in circuit area while securing a breakdown voltage margin between the second well region and the first well region. it can.

  According to the invention of claim 10, by supplying the input potential of the booster cell to the first well region via the diode means, the potential rise of the first well region follows each boosted cell potential when the booster circuit is activated. Therefore, the occurrence of latch-up can be suppressed.

  According to the inventions of claims 11 and 12, the layout area can be reduced by sharing the layout of the first well region.

  According to the thirteenth aspect of the present invention, the charge / discharge charge amount in the first well region is reduced and the pumping between the first boosting cell column and the second boosting cell column pumped by clocks having different phases is performed. Noise interference can be reduced.

  Hereinafter, a booster circuit according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration example of a booster circuit according to the present invention. In FIG. 1, reference numeral 101 denotes a two-parallel booster circuit that generates an output terminal voltage (boosted voltage) Vpump by inputting a two-phase clock signal CLK1, CLK2 and performing a boosting operation. 102, 103, 104, 105, 106, and 107 have a first column and a second column. CLK1 is input to the odd-numbered stage of the first column, and CLK2 is input to the even-numbered stage of the first column. A booster cell in which CLK2 is input to the odd-numbered stage of the second column and CLK1 is input to the even-numbered stage of the second column, 108 and 109 are backflow prevention circuits for preventing backflow of the boosted voltage Vpump, 110 , 111, 112, 113, 114, 115, 116 are input / output terminals of the booster cells 102 to 107, and 117, 118, 119 are input / output terminals of the booster cells in the same stage of the first column and the second column. 1 is an example of a low-voltage output analog comparison circuit that outputs a lower voltage of the voltages; 120 and 121 are Nch (N-channel) transistors used in the low-voltage output analog comparison circuits 117, 118, and 119; , 123 and 124 are output terminals of low voltage output analog comparison circuits 117 to 119 connected to the N well of each booster cell, and 125 is the third booster cell 104 in the first column and the third booster cell in the second column. It is an example of a high voltage output analog comparison circuit that outputs a higher voltage among the voltages of the input / output terminals 113 and 116 with respect to the booster cell 107, and 126 and 127 are Pch used for the high voltage output analog comparison circuit 125. A (P channel) transistor 128 is an output terminal of a high voltage output analog comparison circuit connected to the N well of the backflow prevention circuits 108 and 109. Note that elements having the same reference numerals as in the conventional example are the same as those in the conventional example. Further, the number of series connection of the booster circuit 101 is an example.

  The waveforms of the two-phase clock signals CLK1 and CLK2 in the booster circuit 101 in FIG. 1 are the same as those in FIG. The operation of the booster circuit 101 in FIG. 1 will be described with reference to FIG.

  When CLK1 transits from “L” to “H” and CLK2 transits from “H” to “L” at the time T1, the potentials of the input / output terminals 111, 113, and 115 of the booster cells 102, 104, and 106 are changed. The boosted charge is supplied to the input / output terminal 112, the output terminal of the booster circuit 101, and the input / output terminal 116 via the charge transfer transistors 906 of the booster cell 103, the backflow prevention circuit 108, and the booster cell 107, respectively. Transferred. At this time, in the low voltage output analog comparison circuit 117, the Nch transistor 120 is turned off and the Nch transistor 121 is turned on due to the potential relationship between the boosted input / output terminal 111 and the unboosted input / output terminal 114. The potential of the input / output terminal 114 is output to the output terminal 122 of the low voltage output analog comparison circuit 117 and supplied to the N wells of the booster cell 102 and the booster cell 105. Similarly, the potential of the input / output terminal 112 is output to the output terminal 123 of the low voltage output analog comparison circuit 118 and supplied to the N wells of the booster cell 103 and the booster cell 106. The potential of the input / output terminal 116 is output to the output terminal 124 and supplied to the N wells of the booster cell 104 and the booster cell 107. Further, in the high voltage output analog comparison circuit 125, the Pch transistor 126 is turned on and the Pch transistor 127 is turned off depending on the potential relationship between the boosted input / output terminal 113 and the unboosted input / output terminal 116. The potential of the input / output terminal 113 is output to the output terminal 128 of the voltage output analog comparison circuit 125 and supplied to the N well of the backflow prevention circuit 108 and the backflow prevention circuit 109.

  When CLK1 changes from “H” to “L” and CLK2 changes from “L” to “H” at the time T2, the potentials of the input / output terminals 112, 114, and 116 of the boosting cells 103, 105, and 107 are changed. The boosted charges are transferred to the input / output terminals 113 and 115 and the output terminal of the booster circuit 101 via the charge transfer transistors 906 of the booster cells 104 and 106 and the backflow prevention circuit 109, respectively. At this time, in the low voltage output analog comparison circuit 117, the Nch transistor 120 is turned on and the Nch transistor 121 is turned off according to the potential relationship between the boosted input / output terminal 114 and the unboosted input / output terminal 111. The potential of the input / output terminal 111 is output to the output terminal 122 of the low voltage output analog comparison circuit 117 and supplied to the N wells of the booster cell 102 and the booster cell 105. Similarly, the potential of the input / output terminal 115 is output to the output terminal 123 of the low voltage output analog comparison circuit 118 and supplied to the N wells of the booster cell 103 and the booster cell 106. The potential of the input / output terminal 113 is output to the output terminal 124 and supplied to the N wells of the booster cell 104 and the booster cell 107. Further, in the high voltage output analog comparison circuit 125, the Pch transistor 126 is turned off and the Pch transistor 127 is turned on due to the potential relationship between the boosted input / output terminal 116 and the unboosted input / output terminal 113. The potential of the input / output terminal 116 is output to the output terminal 128 of the voltage output analog comparison circuit 125 and supplied to the N well of the backflow prevention circuit 108 and the backflow prevention circuit 109.

  As described above, according to the booster circuit 101 of FIG. 1, the potentials of the N wells of the booster cells 102 to 107 and the backflow prevention circuits 108 and 109 can be fixed to the input potential or the output potential of each stage of the booster cell. Thus, the amount of charge / discharge charge between the N well and the substrate can be reduced, and current consumption can be reduced. Further, by reducing the charge / discharge charge amount between the N well and the substrate, it is possible to increase the charge amount transferred to the next stage, and the boosting efficiency can be expected to be improved.

  As shown in FIGS. 2 and 3, the low voltage output analog comparison circuits 117 to 119 and the high voltage output analog comparison circuit 125 have an arbitrary number of stages in consideration of the withstand voltage margin and circuit area of the P well-N well. The booster cell can be provided, and even when the number of elements is reduced, the same effect as the above-described configuration can be obtained.

  FIG. 4 shows still another configuration example of the booster circuit according to the present invention. In FIG. 4, reference numeral 701 denotes a two parallel booster circuit that generates a boosted voltage Vpump by inputting a two-phase clock signal CLK1, CLK2 and performing a boosting operation. 702, 703, 704, 705, 706, and 707 are diode-connected between the input / output terminals of each booster cell and the output terminal 128 of the high-voltage output analog comparison circuit 125 with respect to the booster cells 102 to 107 in FIG. The added transistor 710 is added. Reference numerals 708 and 709 denote backflow prevention circuits. The same reference numerals as those in FIG. 1 indicate the same as those. Further, the number of series connection of the booster circuit 701 is an example.

  As a difference from FIG. 1, in the configuration of FIG. 4, the low voltage (or high voltage) output analog comparison circuits 117 to 119 and 125 are shared, and the number of elements is reduced. As a result, when the potential of the input / output terminals 111 to 116 of the booster cells 702 to 707 rises when the booster circuit 701 is activated, the N well potential is in the order of the parasitic diode 909 from the P well 907 of the booster cells 702 to 707. It is supplied as a directional current. By providing the transistor 710 having a diode function in order to suppress the forward current of the parasitic diode 909, a stable boosting operation can be performed even when the booster circuit 701 is started.

  FIG. 5 shows still another configuration example of the booster circuit according to the present invention. In FIG. 5, reference numeral 621 denotes a two-parallel booster circuit that generates a boosted voltage Vpump by inputting a two-phase clock signal CLK1 and CLK2 and performing a boosting operation. Reference numerals 858 and 859 denote backflow prevention circuits which input the two-phase clock signals CLK1 and CLK2 and control the transistors 861 and 862 of the backflow prevention circuits 858 and 859, thereby turning on and off the charge transfer transistor 860. . As a result, the reduction in transfer efficiency that occurs in the backflow prevention circuits 108 and 109 of FIG. 1 is suppressed. The same reference numerals as those in FIG. 1 indicate the same as those. The number of series connection of the booster circuit 621 is an example.

  As a difference from FIG. 1, in the configuration of FIG. 5, two-phase clock signals CLK1 and CLK2 are input to control the gate potential of the charge transfer transistor 860 to improve the charge transfer efficiency and the boosting efficiency. In this case, the low voltage output analog comparison circuit 501 is used.

  According to FIG. 5, by using low voltage output analog comparison circuits 117, 118, 119, and 501 having the same configuration at each stage of the booster circuit 621, the booster capacitors of the booster cells 104 and 107 in the final stage in FIG. The difference between the load of 910 and the load of the boost capacitor 910 of the other boost cells 102, 103, 105, 106 can be suppressed, the parasitic capacitance in the boost capacitor 910 of each stage can be substantially equalized, The charge transfer amount of the booster cells becomes uniform, and stable boosting operation is possible.

  6 is an example in which high-voltage output analog comparison circuits 511, 512, 513, and 125 are used for all the booster cells 102 to 107 and the backflow prevention circuits 108 and 109 in FIG. Only the gates of the transistors 126 and 127 of the high-voltage output analog comparison circuit 511 that controls the N wells of the booster cells 102 and 105 in the first stage are fixed to VSS. Thus, a stable boosting operation can be performed as in FIG.

  As described above, although the booster circuit using the two-phase clock signals CLK1 and CLK2 is taken as an example of the booster circuit configuration, the booster circuit 801 using the four-phase clock signals CLK1, CLK2, CLK3, and CLK4 shown in FIG. In the case where a triple well Nch transistor is used for the boosting cell, such as the boosting circuits 851, 881, 601 and 611 using the two-phase clock signals CLK1 and CLK2 as shown in FIGS. By using the low voltage output analog comparison circuits 117 to 119, 501 or the high voltage output analog comparison circuits 511 to 513, 125, the same effect can be obtained regardless of the configuration of the booster cell. Further, as shown in FIG. 11, it is possible to connect the P well of the Nch transistor 612 of the boosting cells 602 to 607 in common with the N well, and further to connect the N well of the Pch transistor 611 in common. Can also be reduced.

  In FIG. 7, reference numerals 802, 803, 804, 805, 806, and 807 are boosting cells, 808 and 809 are backflow prevention circuits, 810 is a charge transfer transistor (Nch transistor), 811 and 813 are Nch transistors, and 812 is a boosting capacitor. It is. In FIG. 8, 852, 853, 854, 855, 856, and 857 are boosting cells, 858 and 859 are backflow prevention circuits, 860 is a charge transfer transistor (Nch transistor), 861 and 863 are Nch transistors, and 862 is a Pch transistor. It is. 10 and 11, reference numerals 602, 603, 604, 605, 605, and 607 are boost cells, 608 and 609 are backflow prevention circuits, 610 and 612 are charge transfer transistors (Nch transistors), and 611 and 614 are charge transfers. Transistors (Pch transistors) 613 are connection nodes.

  FIGS. 12, 13, and 14 are configuration examples of a high voltage (low voltage) output analog comparison circuit, which is one of the high voltage (low voltage) output analog comparison circuits for all the booster cells and the backflow prevention circuit. One or both may be confused. Further, regardless of the number of transistors such as charge transfer transistors in the N well in each booster cell and the presence or absence of the Pch transistor, the P well of the Nch transistor such as the charge transfer transistor is connected to the N well, The same effect can be obtained if the P-well connection is not necessarily directly connected to the source as long as the boosting operation is possible, such as when the potential of the source is switched between the drain and source potentials.

  Further, the configurations of the low voltage output analog comparison circuits 117 to 119, 501 and the high voltage output analog comparison circuits 511, 512, 513, and 125 shown in the figure are merely examples, and any configuration having similar functions may be used.

  FIG. 15 is a plan view showing a layout configuration example in the booster circuit according to the present invention, and illustrates the charge transfer transistor 906 and the low voltage output analog comparison circuits 117 to 119 of the booster cells 102 to 107 shown in FIG. ing.

  From FIG. 15, the output terminal 122 (or 123, 124) of the low voltage output analog comparison circuit 117 (or 118, 119) is the charge transfer transistor 906 of the booster cells 102 and 105 (or 103 and 106, or 104 and 107). N well (NT), and the N well is laid out in common for the charge transfer transistors 906 of the two boosting cells 102 and 105.

  According to FIG. 15, the N well is commonly laid out in the switching element 906 having a triple well structure existing in two or more boosting cells 102 and 105 controlled by the output voltage of the low voltage output analog comparison circuit 117. Thus, the layout area can be reduced.

  The layout configuration of FIG. 15 is an example, and the layout of the N well of the switching element 906 controlled by the output voltage of the low voltage output analog comparison circuit 118 is related to the number of boosting cell stages as shown in FIGS. It can be arbitrarily separated and shared.

  Further, as shown in FIGS. 18 and 19, the N wells of the low voltage output analog comparison circuits 117 to 119 can be laid out in common with the N wells of the switching elements 906 of the boosting cells 102 to 107.

  Further, as shown in FIGS. 20 and 21, the N well of the transistor 120 of the low voltage output analog comparison circuits 117, 118, 119, 501, the boosting cells 102, 103, 104, and the backflow prevention circuit 108 is made common and low It is also possible to share the N well of the transistor 121 of the voltage output analog comparison circuits 117, 118, 119, and 501 and the booster cells 105, 106, and 107 and the backflow prevention circuit 109. As a result, it is possible to reduce the influence of noise in the boost capacitor while reducing the charge / discharge charge amount of the N well, and to perform a stable boost operation.

  As shown in FIG. 22, FIG. 23, and FIG. 24, the same layout is possible in the high voltage output analog comparison circuits 511, 512, 513, and 125.

  The above layout is an example, and the N-well region and the P-well region of a plurality of transistors having the same potential can be arbitrarily shared regardless of the boosting cell column.

  As described above, the booster circuit according to the present invention is characterized in that in the triple well structure element constituting the booster cell, the substrate bias effect is suppressed and the current consumption can be reduced and the circuit area and layout area can be reduced. It is useful as a nonvolatile semiconductor memory device, a power generation circuit for improving analog circuit characteristics in a CMOS process, and the like.

  The present invention can also be applied to applications such as a volatile semiconductor memory device such as a DRAM, a liquid crystal device, and a power supply circuit for portable equipment.

It is a circuit diagram which shows the structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the other structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a circuit diagram which shows the further another structural example of the booster circuit which concerns on this invention. It is a top view which shows the example of a layout structure in the booster circuit which concerns on this invention. It is a top view which shows the other layout structural example in the booster circuit which concerns on this invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. FIG. 10 is a plan view showing still another layout configuration example in the booster circuit according to the present invention. It is a circuit diagram which shows the example of the conventional booster circuit. FIG. 26 is a waveform diagram of a two-phase clock signal in the booster circuit of FIG. 25.

Explanation of symbols

101, 201, 301 Booster circuit 102-107 Booster cell 108, 109 Backflow prevention circuit 110-116 Input / output terminals 117-119 of booster cell Low voltage output analog comparator circuit 120, 121 Nch transistor 122-124 Low voltage output analog comparator circuit Output terminal 125 high voltage output analog comparison circuit 126, 127 Pch transistor 128 output terminal 501 of high voltage output analog comparison circuit low voltage output analog comparison circuit 511-513 high voltage output analog comparison circuit 601, 611 step-up circuit 602-607 step-up Cell 608, 609 Backflow prevention circuit 610, 612 Charge transfer transistor (Nch transistor)
611, 614 Charge transfer transistor (Pch transistor)
613 Connection node 621, 622 Boost circuit 701 Boost circuit 702-707 Boost cell 708, 709 Backflow prevention circuit 710 Diode connection transistor 801 Boost circuit 802-807 Boost cell 808, 809 Backflow prevention circuit 810 Charge transfer transistor (Nch transistor)
811, 813 Nch transistor 812 Boost capacitor 851, 881 Boost circuit 852 to 857 Boost cell 858, 859 Backflow prevention circuit 860 Charge transfer transistor (Nch transistor)
861, 863 Nch transistor 862 Pch transistor 901 Booster circuit 902-904 Booster cell 905 Backflow prevention circuit 906 Charge transfer transistor (Nch transistor)
907 P-well (PW)
908 N-well (NT)
909 Parasitic diode 910 between P-well and N-well Boost capacitor 911-914 Input / output terminals CLK1-CLK4 of boost cell Clock signal Ttrans Charge transfer period Vpump Output terminal voltage (boost voltage)

Claims (13)

A first well type first well region on the substrate; a second well type second well region in the first well region; the first well region and the second well region One or more switching elements in one or both of the well regions, and the one or more switching elements are used to turn on and off between the first terminal and the second terminal. A booster circuit comprising a booster cell for transferring charge from a first terminal to the second terminal,
A first booster cell array composed of N booster cells (N ≧ 1);
A second boost cell array composed of M booster cells (M ≧ 1);
The output potential of the booster cell at the i-th stage (1 ≦ i ≦ N) of the first booster cell row and the booster cell of the i-th stage (1 ≦ i ≦ M) of the second booster cell row. Among the output potentials, it has an analog comparison circuit that outputs a high-side potential or a low-side potential,
The output potential of the analog comparison circuit is set to one or more of the (i + 1) th boosting cell of the first and second boosting cell columns, the ith boosting cell, or the boosting cell preceding the ith stage. A booster circuit, wherein the booster circuit is applied to the first well region of the one or more switching elements. A first well type first well region on the substrate; a second well type second well region in the first well region; the first well region and the second well region One or more switching elements in one or both of the well regions, and the one or more switching elements are used to turn on and off between the first terminal and the second terminal. A booster circuit comprising a booster cell for transferring charge from a first terminal to the second terminal,
A first booster cell array composed of N booster cells (N ≧ 1);
A second boost cell array composed of M booster cells (M ≧ 1);
The input potential of the booster cell at the i-th stage (1 ≦ i ≦ N) of the first booster cell row and the booster cell of the i-th stage (1 ≦ i ≦ M) of the second booster cell row. An analog comparison circuit that outputs a high-side potential or a low-side potential among the input potentials;
The output potential of the analog comparison circuit is set to one or more of the (i + 1) th boosting cell of the first and second boosting cell columns, the ith boosting cell, or the boosting cell preceding the ith stage. A booster circuit, wherein the booster circuit is applied to the first well region of the one or more switching elements. A first well type first well region on the substrate; a second well type second well region in the first well region; the first well region and the second well region One or more switching elements in one or both of the well regions, and the one or more switching elements are used to turn on and off between the first terminal and the second terminal. A booster circuit comprising a booster cell for transferring charge from a first terminal to the second terminal and a backflow prevention circuit,
A first booster cell array composed of N booster cells (N ≧ 1) and the backflow prevention circuit;
A second booster cell array composed of M booster cells (M ≧ 1) and the backflow prevention circuit;
The output potential of the booster cell in the i-th stage (1 ≦ i ≦ N) of the first booster cell column and the booster cell in the i-th stage (1 ≦ i ≦ M) of the second booster cell column, respectively. And an analog comparison circuit that outputs a high-side potential or a low-side potential among the output potentials of
The output potential of the analog comparison circuit is applied to the backflow prevention circuit of the first and second booster cell rows, the booster cell at the (i + 1) th stage, the booster cell at the ith stage, or the booster cell before the ith stage. A step-up circuit for applying to the first well region of the one or more switching elements provided in one or more of them. A first well type first well region on the substrate; a second well type second well region in the first well region; the first well region and the second well region One or more switching elements in one or both of the well regions, and the one or more switching elements are used to turn on and off between the first terminal and the second terminal. A booster circuit comprising a booster cell for transferring charge from a first terminal to the second terminal and a backflow prevention circuit,
A first booster cell array composed of N booster cells (N ≧ 1) and the backflow prevention circuit;
A second booster cell array composed of M booster cells (M ≧ 1) and the backflow prevention circuit;
An analog comparison circuit for outputting a higher potential or a lower potential among the intermediate potential of the backflow prevention circuit of the first booster cell row and the intermediate potential of the backflow prevention circuit of the second booster cell row. And
The output potential of the analog comparison circuit is supplied to the backflow prevention circuit of the first and second boosting cell columns or one of the boosting cells included in the first boosting cell column and the second boosting cell column. A booster circuit, wherein the booster circuit is applied to the first well region of the one or more switching elements provided as described above. A first well type first well region on the substrate; a second well type second well region in the first well region; the first well region and the second well region One or more switching elements in one or both of the well regions, and the one or more switching elements are used to turn on and off between the first terminal and the second terminal. A booster circuit comprising a booster cell for transferring charge from a first terminal to the second terminal and a backflow prevention circuit,
A first booster cell array composed of N booster cells (N ≧ 1) and the backflow prevention circuit;
A second booster cell array composed of M booster cells (M ≧ 1) and the backflow prevention circuit;
The input potentials of the boost cells in the i-th stage (1 ≦ i ≦ N) of the first and second boost cell arrays or the backflow prevention circuits are compared, and the higher potential of the input potentials or An analog comparison circuit that outputs a lower potential,
The output potential of the analog comparison circuit is applied to the backflow prevention circuit of the first and second booster cell rows, the booster cell at the (i + 1) th stage, the booster cell at the ith stage, or the booster cell before the ith stage. A step-up circuit for applying to the first well region of the one or more switching elements provided in one or more of them. The booster circuit according to any one of claims 1 to 5,
A booster circuit, wherein the second well region and the first terminal are connected to each other so that the second well region and the first terminal have the same potential. The booster circuit according to any one of claims 1 to 5,
A booster circuit, wherein the second well region and the first well region are connected to each other so that the second well region and the first well region have the same potential. The booster circuit according to any one of claims 1 to 5,
The analog comparison circuit has a first conductivity type first well region on the substrate, and has a second conductivity type second well region in the first well region. A booster circuit comprising one or more switching elements in a well region or in the second well region, and provided in each stage of the booster cell. The booster circuit according to any one of claims 1 to 5,
The analog comparison circuit has a first conductivity type first well region on the substrate, and has a second conductivity type second well region in the first well region. One or more switching elements are provided in the well region or the second well region, and one or more switching elements are provided in the first and second boosting cell rows, and are provided for any number of boosting cell stages. And a booster circuit. The booster circuit according to any one of claims 1 to 5,
A booster circuit comprising diode means between the first terminal of the booster cell and the first well region. The booster circuit according to any one of claims 1 to 5,
Boosting, characterized in that the layout of the first well regions of the one or more switching elements in which the potentials of the first well regions of the first and second boosting cell rows are the same is shared. circuit. The booster circuit according to any one of claims 1 to 5,
The layout of the first well region of the one or more switching elements having the same potential in the first well region of the first and second booster cell rows and the first of the analog comparison circuit. A booster circuit characterized by sharing a well region layout. The booster circuit according to any one of claims 1 to 5,
The layout of the first well region of the one or more switching elements of the i-th boost cell in the first boost cell row and the layout of the first well region of the first element of the analog comparison circuit. And
The layout of the first well region of the one or more switching elements of the i-th boost cell in the second boost cell row and the layout of the first well region of the second element of the analog comparison circuit. Is a common booster circuit.

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