JP3524845B2 - Charge pump circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit used in a power supply circuit or the like, and more particularly to a charge pump circuit capable of high efficiency and large current output.

[0002]

2. Description of the Related Art Recent video devices such as video cameras, digital still cameras (DSC), and DSC phones use CCDs for capturing the video. This CCD drive circuit has positive and negative high voltage (tens of volts) and large current (several meters).
A) It requires a power supply and currently this high voltage is generated using a switching regulator.

A switching regulator can generate a high voltage with high performance, that is, high power efficiency (output power / input power). However, this circuit has a drawback that harmonic noise is generated at the time of switching current, and therefore the power supply circuit must be shielded for use. Furthermore, a coil is required as an external component.

On the other hand, the charge pump circuit can generate a high voltage with a small noise, but has a drawback that the power efficiency is lower than the conventional one. Therefore, the charge pump circuit is used as a power supply circuit of a portable device having power efficiency as a priority specification. It is not possible. Therefore, if a high-performance charge pump circuit can be realized, it can contribute to downsizing of portable devices.

A Dickson charge pump circuit is known as the most basic conventional charge pump circuit. This circuit is described, for example, in the technical document "John F. Dickson.
On-chip High-Voltage Generation in MNOS Integrate
d Circuits Using an Improved Voltage Multiplier Te
chnique IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.S
C-11, NO.3 pp.374-378 JUNE 1976. ”.

FIG. 5 is a schematic circuit diagram showing a four-stage Dickson charge pump circuit. In FIG. 5, five diodes are connected in series. C is a coupling capacitance, CL is an output capacitance, and CLK and CLKB are input clock pulses having opposite phases. Further, 51 is a clock driver, and 52 is a current load.

When the constant current Iout flows in the output in the stable state, the input current to the charge pump circuit is the current from the input voltage Vin and the current supplied from the clock driver. These currents are as follows, ignoring the charging / discharging current to the parasitic capacitance. Φ1 = High,
2Io in the direction of the solid line arrow in the figure during the period of Φ2 = Low
The average current of ut flows. Also, Φ1 = Low, Φ2 =
2Iout in the direction of the dashed arrow in the figure during the High period
The average current of flows. All these average currents in a clock cycle will be Iout. The boosted voltage Vout of the charge pump circuit in the stable state is expressed as follows.

[0008] Vout = Vin -Vd + n (V φ - V l -Vd) (1) Here, in V _phi Each connection node is a voltage amplitude generated by the coupling capacitance with the change of the clock pulse.
V _l is a voltage drop caused by the output current Iout, and Vin is an input voltage, which is normally set to the power supply voltage Vdd for positive boosting and 0 V for negative boosting. Vd is the forward bias diode voltage (n) is the number of pumping stages. Further, V _l and V _φ are expressed by the following equations.

V _l = (2Iout · T / 2) / (C + C _S ) (2) V _φ = V _φ · C / (C + _CS ) (3) where C is the clock coupling capaci
tance) and C _S are parasitic capacitances (stray ca
pacitance at each node), V _φ is the clock pulse amplitude, f is the frequency of the clock pulse, and T is the clock period.

As described above, in the charge pump circuit, boosting is performed by using the diode as a charge transfer element and sequentially transferring the charge to the next stage.

[0011]

By the way, as described above, it is important to increase the power efficiency in a large current output load type charge pump circuit. According to the study by the inventor of the present application, it has been found that reducing the output impedance of the clock driver is effective as one method therefor, which will be described below.

FIG. 6 is a diagram showing the relationship between the clock pulse and the charge transfer current. In the small current type charge pump circuit, the charge transfer current is normally zero within 1/2 cycle of the clock, as in "current type A" in the figure.

On the other hand, in the large current type charge pump circuit, the charge transfer current does not normally become zero within 1/2 cycle of the clock unlike the "current type B" in the figure. Therefore, assuming that the power supply voltage of the clock driver is Vdd and the residual current at the 1/2 cycle point of the clock is Ires, V _φ = Vdd−ΔV _{ds (P)} −ΔV _{ds (N)} (4) where ΔV _{ds ( P)} is the drain-source residual voltage of the P-channel MOS transistor of the clock driver when the current Ires flows. Also, ΔV _{ds (N)} is the current Ir
N-channel MO of clock driver when es flows
It is the drain-source residual voltage of the S transistor.

Therefore, as is apparent from the equations (1) to (4), the boosting efficiency (power efficiency) is improved by V _l ≈0, Vd ≈0, ΔV _{ds (P)} ≈0. , ΔV _{ds (N)} ≈0 is a condition.

Therefore, the present invention aims to improve the power efficiency of the charge pump circuit by realizing the conditions of ΔV _{ds (P)} ≈0 and ΔV _{ds (N)} ≈0 based on the above-mentioned examination results. And

[0016]

SUMMARY OF THE INVENTION A charge pump circuit according to the present invention comprises a plurality of charge transfer MOS transistors connected in series and having a predetermined input voltage applied to a first stage charge transfer MOS transistor, and the charge transfer MOS transistor. A coupling capacitor, one end of which is connected to each connection point of the MOS transistor, and a clock driver which alternately supplies a reverse-phase clock pulse to the other end of the coupling capacitor, are provided, and a boosted voltage is supplied from a charge transfer MOS transistor at a subsequent stage. In the output charge pump circuit, a level shift circuit for level-shifting the voltage of the input clock of the clock driver to a voltage higher than the power supply voltage of the clock driver is provided.

According to such means, the source-drain voltage V when the transistor of the clock driver is turned on
Since gs can be made higher than the power supply voltage of the clock driver, the impedance can be lowered.
As a result, the conditions of ΔV _{ds (P)} ≈0 and ΔV _{ds (N)} ≈0 can be realized, so that the power efficiency of the charge pump circuit can be improved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing a clock driver portion of a charge pump circuit according to an embodiment of the present invention. The other parts are similar to those of the conventional charge pump circuit shown in FIG.

In FIG. 1, 1 is a P-channel type MOS transistor in the output stage, and 2 is an N-channel type MOS transistor in the output stage.
Transistors 3 are voltage sources for supplying power supply voltage Vdd, 4
Is an output terminal. Reference numeral 5 is a first level shift circuit for applying a level-shifted voltage of the input clock CLK to the P-channel MOS transistor, and is supplied with the power supply voltage Vdd and the power supply voltage -Vdd from the voltage source 7. Reference numeral 6 denotes a second level shift circuit for applying a level-shifted voltage of the input clock CLK to the N-channel type MOS transistor.
Vdd and ground voltage 0V are supplied. Reference numeral 9 is an inverter that inverts the input clock CLK and outputs it to the first and second clock drivers.

Therefore, the power supply voltage supplied to the inverter 9 is Vdd, and the input clock CLK is 0V to Vd.
Assuming that the amplitude is d, the first level shift circuit 5
Has an amplitude of -Vdd to Vdd, so that when the P-channel MOS transistor 1 is turned on, its source-drain voltage Vgs = -2Vdd, which allows a reduction in impedance. Therefore, the condition of ΔV _{ds (P)} ≈0 and ΔV _{ds (N)} ≈0 which the present inventor has studied can be realized, so that the power efficiency of the charge pump circuit can be improved. .

Similarly, since the output of the second level shift circuit 6 has an amplitude of 0 to 2Vdd, when the N-channel MOS transistor 1 is turned on, its source-drain voltage Vgs = 2Vdd, which is low. Impedance becomes possible.

FIG. 2 is a circuit diagram showing the structure of the above-mentioned level shift circuit. FIG. 2 (a) shows the first level shift circuit and FIG. 2 (b) shows the second level shift circuit. In FIG. 2A, 10 and 11 are P-channel MOS transistors, 12 is an inverter, and IN is an input terminal to which the output of the inverter 9 of FIG. 1 is applied. Reference numerals 13 and 14 are N-channel type MO whose drain and gate are cross-connected.
The S transistor, 15 is an output terminal. The power supplies of this first level shift circuit are Vdd and -Vdd.

In FIG. 2B, 16 and 17 are N-channel MOS transistors, 18 is an inverter, and IN is an input terminal to which the output of the inverter 9 of FIG. 1 is applied. Reference numerals 19 and 20 denote P-channel MOS transistors having drains and gates cross-connected, and reference numeral 21 denotes an output terminal. The power supplies of this second level shift circuit are 2Vdd and 0V.

In the above-mentioned structure, the power source of the first level shift circuit is Vdd and -Vdd, but the present invention is not limited to this, and higher voltage sources such as Vdd and -2Vdd may be used. Further, the power supply of the second level shift circuit is 2Vdd and 0V, but is not limited to this, and a higher voltage source, for example, 3Vdd and 0V.
V may be used. As a result, the output of the clock driver can be further lowered in impedance.

Basically, a voltage source 7 of -Vdd, + 2Vd
The voltage source 8 of d is specially provided. However, the circuit configuration is simplified by using a part of the boosted voltage of the charge pump circuit as a voltage source.

FIG. 3 is a circuit diagram showing a charge pump circuit for generating a positive boosted voltage. In the figure, four charge transfer MOS transistors M1 to M4 are connected in series. M1 and M2 in the former stage are N-channel type, M in the latter stage
3 and M4 are P-channel type. Gate of M1 to M4
The source and the substrate are connected to have the same potential so that the substrate-to-substrate voltage Vgb has the same value as the gate-source voltage Vgs. The power source voltage Vdd is supplied as the input voltage Vin to the source of M1. In addition, the boosted voltage Vout is output from the drain of M4, and the current load L
Supplied to oad.

C1, C2 and C3 are coupling capacitors whose one ends are connected to connection points (pumping nodes) of the charge transfer MOS transistors M1 to M4. A clock pulse CLK and a clock pulse CLKB having an opposite phase to the clock pulse CLK are alternately applied to the other ends of the coupling capacitors C1 to C3. The clock pulses CLK and CLKB are output from a clock driver (not shown).

Charge transfer MOS transistors M1 and M2
The outputs of the inversion level shift circuits S1 and S2 are supplied to the respective gates. Further, the non-inverting level shift circuit S is provided at each gate of the charge transfer MOS transistors M3 and M4.
The outputs of 3 and S4 are supplied.

A detailed description of the operation will be omitted.
From the second stage of the charge pump circuit, a stable DC level 2Vdd can be obtained through the 2Vdd output circuit including the output transistor Mm and the capacitor Cm.
Therefore, it is preferable to use this as the voltage source 8.

FIG. 4 is a circuit diagram showing a two-stage charge pump circuit which performs negative boosting (boosting below 0 V). This two-stage charge pump circuit outputs a boosted voltage of -2Vdd. In the figure, the combination of the clock pulses CLK 'and CLKB' and the level shift circuit is changed. That is, the charge transfer MOS transistors M1 ', M2', M3 'are connected in series, and the coupling capacitors C1', C2 'are connected to the connection node. M1 'is a P-channel type and has a ground potential (0
V) is being applied. M2 'and M3' are N-channel type.

The output of the inverting level shift circuit S1 'is applied to the gate of M1', and the outputs of the non-inverting level shift circuits S2 'and S3' are applied to the gates of M2 'and M3'. Then, the minus boosted voltage −Vout is output from the drain of the charge transfer MOS transistor M3 ′ and is supplied to the current load Load.

In the figure, an output circuit for extracting -Vdd from the second-stage charge transfer MOS transistor M2 'is provided. This circuit is a non-inverting level shift circuit S2 '.
It is composed of a MOS transistor Mm 'and a capacitor Cm' controlled by. According to this circuit,
Since a stable DC voltage of Vdd can be obtained, it is preferable to use this as the voltage source 7.

[0033]

According to the present invention, since the source-drain voltage Vgs when the transistor of the clock driver is turned on is made higher than the power supply voltage of the clock driver by the level shift circuit, the impedance of the clock driver is lowered. be able to.

As a result, ΔV _{ds (P)} ≈0, ΔV _{ds (N)} ≈
Since the condition of 0 can be realized, the power efficiency of the charge pump circuit can be improved.

As the voltage source of the level shift circuit,
Since the boosted voltage of the charge pump circuit is used, the circuit configuration is simple.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a clock driver portion of a charge pump circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a level shift circuit.

FIG. 3 is a circuit diagram showing a charge pump circuit that generates a positive boosted voltage.

FIG. 4 is a circuit diagram showing a two-stage charge pump circuit that performs negative boosting (boosting below 0 V).

FIG. 5 is a schematic circuit diagram showing a four-stage Dickson charge pump circuit.

FIG. 6 is a diagram showing a relationship between a clock pulse and a charge transfer current.

[Explanation of symbols]

1 P-channel MOS transistor 2 N-channel MOS transistor 3 voltage source 4 output terminals 5 First level shift circuit 6 Second level shift circuit 7 Voltage source 8 voltage source 9 inverter

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H03K 19/0185 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27/04 H02M 3/07 H03K 19/0185

Claims (3)

(57) [Claims] 1. A plurality of charge transfer MOS transistors connected in series and having a predetermined input voltage applied to a first stage charge transfer MOS transistor, and the charge transfer MO transistor.
A coupling capacitor whose one end is connected to each connection point of the S transistor, and a clock driver which alternately supplies clock pulses of opposite phase to the other end of the coupling capacitor,
In a charge pump circuit for outputting a boosted voltage from a charge transfer MOS transistor at a subsequent stage, a level shift circuit for level-shifting a voltage of an input clock of the clock driver to a voltage higher than a power supply voltage of the clock driver is provided. A charge pump circuit. 2. The boosted voltage extracted from the charge pump circuit or another charge pump circuit is used as a power source of the level shift circuit.
The charge pump circuit described in. 3. The clock driver is a CMOS driver in which a P-channel transistor and an N-channel transistor are connected in series, and a first level shift circuit for level-shifting a voltage of an input clock applied to the P-channel transistor. A second level shift circuit for level-shifting the voltage of the input clock applied to the N-channel transistor, and when the P-channel transistor or the N-channel transistor is turned on according to the input clock, The charge pump circuit according to claim 1, wherein a source-gate voltage Vgs that is equal to or higher than the power supply voltage Vdd is applied.