CN115421552B

CN115421552B - Dynamic bias low-power-consumption integrator serving as floating voltage source based on capacitor

Info

Publication number: CN115421552B
Application number: CN202211033035.6A
Authority: CN
Inventors: 马添福; 郭春炳; 张春华; 符业聪; 苑梦; 郑基炜; 孙博
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2023-06-23
Anticipated expiration: 2042-08-26
Also published as: CN115421552A

Abstract

The invention discloses a dynamic bias low-power-consumption integrator based on a capacitor serving as a floating voltage source, which comprises the following components: the dynamic bias circuit comprises a PMOS transistor M5, an NMOS transistor M6 and a floating voltage source CI; when CLK 1=1, the gates and drains of M5 and M6 are shorted to form diode connection, at this time, two diodes are connected in series with CI, the current of M5 drain flows through CI to charge the upper plate, and the current of plate under CI flows through M6 to discharge; after the floating voltage source CI is charged and discharged for half a clock period, stable voltage difference is formed between the upper polar plate and the lower polar plate of the CI, so that bias voltage is provided for the capacitors C1 and C2 of the inverter circuit. The invention aims to provide a dynamic bias low-power-consumption integrator which is based on a capacitor serving as a floating voltage source, so that the average power consumption of the integrator in a bias phase is greatly reduced compared with that in an integration phase. Meanwhile, the capacitor floating voltage source is used, additional static bias voltage is not needed, and two paths of static bias circuits are reduced, so that the power consumption of the additional bias circuits is reduced.

Description

Dynamic bias low-power-consumption integrator serving as floating voltage source based on capacitor

Technical Field

The invention relates to the field of analog integrated circuits, in particular to a dynamic bias low-power-consumption integrator serving as a floating voltage source based on a capacitor.

Background

In recent years, the development of internet of things (IOT) has driven the need for low-power, high-resolution analog-to-digital converters (ADCs). Most analog-to-digital converters in IOT applications are powered by batteries or energy harvesters, so the design of ultra low power consumption (ULP) is of great importance to extend the useful life of the ADC.

For example, delta-Sigma ADC is widely used in the fields of low-power consumption high-precision audio signal data conversion, high-precision narrowband sensor signal data conversion, radio frequency signal low-pass and band-pass data converters, etc., and has become one of the most mainstream data converter frameworks at present. With the development of IOT, the power consumption requirement of Delta-Sigma ADC is higher and higher, and in some application fields, ultra-low power consumption is required. In the Delta-Sigma circuit, the integrator is a core circuit part of the Delta-Sigma circuit and consumes most of power consumption, so that the reduction of the power consumption of the integrator is of great significance for reducing the power consumption of the whole Delta-Sigma ADC. The conventional operational amplifier is a common scheme used as an integrator, but is not suitable for an application scene with ultra-low power consumption because a large amount of static power consumption is consumed in a non-integral phase. The inverter is used as an integrator proposal, so that the power consumption of the integrator is greatly reduced, and the current requirement on the low-power consumption Delta-Sigma ADC is met.

Existing inverters based on dynamic biasing have consumed nearly the same average power consumption in the integration phase and the bias phase.

Disclosure of Invention

The invention aims to provide a dynamic bias low-power-consumption integrator which is based on a capacitor serving as a floating voltage source, so that the average power consumption of the integrator in a bias phase is greatly reduced compared with that in an integration phase. Meanwhile, the capacitor floating voltage source is used, additional static bias voltage is not needed, and two paths of static bias circuits are reduced, so that the power consumption of the additional bias circuits is reduced.

To this end, the invention discloses a dynamically biased low power integrator based on a capacitor acting as a floating voltage source, comprising: the device comprises a two-phase non-overlapping clock generation circuit, an inverter circuit, a dynamic bias circuit and a static bias circuit which are connected with each other;

the dynamic bias circuit comprises a PMOS transistor M5, an NMOS transistor M6 and a floating voltage source CI; when CLK 1=1, the gates and drains of M5 and M6 are shorted to form diode connection, at this time, two diodes are connected in series with CI, the current of M5 drain flows through CI to charge the upper plate, and the current of plate under CI flows through M6 to discharge; after the floating voltage source CI charges and discharges for half a clock period, stable voltage difference is formed between the upper polar plate and the lower polar plate of the CI, so that bias voltage is provided for the capacitors C1 and C2 of the inverter circuit; when CLK 2=1, the upper and lower polar plates of the capacitor CI are short-circuited, and the charge is cleared to wait for the next charge and discharge operation; when clk2=1, the gates of M5 and M6 are respectively connected to AVDD and VSS, AVDD is the reference power supply of the integrator, VSS is the reference ground of the integrator, so that M5 and M6 are turned off, wherein the input clock signal is CLK, four-way clock signals are generated, and CLK1 and CLK2 are two-phase non-overlapping signals.

Preferably, the two-phase non-overlapping clock generating circuit is composed of digital logic gates such as a NAND gate and a NOT gate; wherein clk1=1, clk2=0, clk1=0, clk2=1; CLK1D, CLK D is a signal delayed by a certain time interval, respectively.

Preferably, the inverter circuit includes PMOS transistors M1, M2, NMOS transistors M3, M4, bias capacitors C1, C2; wherein M1 is used as an input tube of the inverter, the source electrode of the input tube is connected to AVDD, the grid electrode of the input tube is connected to the right polar plate of C1, and the drain electrode of the input tube is connected to the source electrode of M2; m2 is connected to AVDD to be turned off when clk1=1 and to the bias voltage VP when clk2=1 as a switch constituting the cascode structure, so that M2 is turned on; m4 is used as an inverter input transistor, the source electrode of the inverter input transistor is connected to VSS, the grid electrode of the inverter input transistor is connected to the right polar plate of C2, and the drain electrode of the inverter input transistor is connected to the source electrode of M3; m3 as a switch constituting a cascode structure, the gate of which is connected to VSS off when clk1=1 and to voltage VN when clk2=1, so that M3 is on; when clk1=1, the left plates of C1 and C2 are connected to the input common-mode voltage VCM, the right plates of C1 and C2 are respectively connected to the upper plate and the lower plate of CI, and the right plates of C1 and C2 are biased at a certain voltage by the floating voltage source CI of the dynamic bias circuit.

Preferably, the static bias circuit includes PMOS transistors M7, M10, M11, M13, M15, NMOS transistors M8, M9, M12, M14, M16, and a resistor R1; wherein, the resistors R1 form a current source insensitive to the change of the power supply voltage AVDD, M13, M14, M15 and M16; m14 is an NMOS current mirror transistor of a current source, and the grid electrode of the NMOS current mirror transistor is connected to the grid electrode of M16 to complete the proportional copying of current; m10 and M11 are connected into diode connection type, and static bias voltage VP is formed under the drive of certain current biased by M16; similarly, M7 is a PMOS current mirror transistor of a current source, and the grid electrode of the PMOS current mirror transistor is connected to the grid electrode of M15 to complete the proportional replication of current; m8 and M9 are connected into diode connection type, and static bias voltage VN is formed under the drive of certain current of M7 bias; when the capacitors C3 and C4 are in CLK 1=1, the upper polar plate and the lower polar plate are in short circuit and are respectively connected to AVDD and VSS; when clk2=1, the upper plates of C3 and C4 are connected to VN and VP, respectively, which are bias voltages formed by the static bias circuit.

Preferably, the operating state of the low power integrator is such that clk1=1: when CLK 1=1, the integrator connects M5 and M6 of the dynamic bias circuit into diode connection, and connects in series with the floating voltage source CI, at this time, the current flows through M5 to charge the upper plate of CI, and at the same time, the lower plate of CI discharges through M6; in the charge and discharge process, the gate voltage of M5 rises, the gate voltage of M6 falls, and after a certain time, CI forms a certain voltage difference, so that bias voltages are provided for C1 and C2 in the inverter circuit; at this time, the grid electrode of M2 in the inverter circuit is connected to AVDD, the grid electrode of M3 is connected to VSS, at this time, the upper and lower polar plates of the capacitors C3 and C4 are in short circuit and are respectively connected to AVDD and VSS, so that conditions are provided for quickly establishing bias voltage for the inverter circuit next time.

Preferably, the low power integrator operates in a state of clk2=1: when the integrator is in CLK 2=1, under the condition that the dynamic bias circuit provides bias voltage for the inverter circuit, the grid electrode of M1 in the inverter circuit is biased by the right plate voltage of C1, and the grid electrode of M4 is biased by the right plate voltage of C2; at this time, the input transistors M1 and M4 of the inverter have a certain static operating point; at this time, the gate of M2 is connected to AVDD when clk1=1, and is switched to VP, so that the source-drain of M2 is turned on, and forms a cascode amplifier structure with the M1 transistor, and the gate of M3 is connected to VSS when clk1=1, and is switched to VN, so that the source-drain of M3 is turned on, and forms a cascode amplifier structure with the M4 transistor.

Preferably, during operation of the complete integrator: when clk1=1, the right plate of the sampling capacitor CS is connected to the input common mode voltage VCM, while the input signal VIN is sampled to the left plate of CS, and a certain voltage difference is formed at two ends of CS; at the moment, when the CLK 1=1 is ended, the dynamic bias circuit provides bias voltages for C1 and C2 in the integrator circuit, and provides a static bias condition for integration of the integrator when the CLK 2=1 arrives; at this time, the left plate of the capacitor CF is disconnected from the left plates of C1 and C2. When CLK2 = 1, the left plate of the sampling capacitor CS is connected to the common mode voltage VCM, while the right plate of CS is disconnected from the common mode voltage VCM, and the left plate of the capacitor CF is connected to the left plates of C1 and C2; at the moment, as the charge at two ends of the CS capacitor is conserved, the voltages of the right polar plates of C1 and C2 are changed, and the inverter starts to work, so that the integration of the output end VOUT is started, wherein the integrated gain is CS/CF; at the end of integration, the voltage at the right end of CS returns to VCM, thus completing one integration process.

Compared with the existing dynamic bias integrator, the design of the invention has the advantages that the average current of the dynamic bias circuit of the integrator is greatly reduced when the integrator is in CLK 1=1 compared with the average current of the inverter circuit of the integrator when the integrator is in CLK 2=1; compared with the existing dynamic bias integrator, the dynamic bias integrator has the advantages that a floating current source consisting of PMOS and NMOS in the dynamic bias circuit is replaced by the capacitor CI, and the CI is used as a floating voltage source, so that two additional static bias voltages can be reduced, and the power consumption of the two static bias circuits is reduced. Meanwhile, as the differential pressure at two ends of the CI rises in the charging and discharging process of the CI, M5 and M6 enter a subthreshold region after the differential pressure reaches a certain degree, the current is extremely reduced, the charging and discharging of the CI starts to become slow, a large amount of current consumption is restrained, and the average current in the dynamic bias process is smaller compared with that when the PMOS and the NMOS act as floating current sources.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic diagram of a circuit configuration of a conventional integrator;

FIG. 2 is a schematic diagram of a circuit configuration of a low power integrator according to the present invention;

fig. 3 is a circuit diagram of the integrator of the present invention when clk1=1;

fig. 4 is a circuit diagram of the integrator of the present invention when clk2=1;

FIG. 5 is a test circuit diagram of an example of the present invention;

fig. 6 (a) is a voltage waveform diagram of the differential output of the integrator according to the present invention, and fig. 6 (b) is a voltage waveform diagram of the differential output of the integrator according to the prior art;

FIG. 7 (a) is a graph of current output waveforms of the integrator in the integrating phase and dynamic bias phase inverter legs and dynamic bias legs of the present invention, and FIG. 7 (b) is a graph of current output waveforms of the integrator in the integrating phase and dynamic bias phase inverter legs and dynamic bias legs of the present invention;

fig. 8 (a) is the average current consumed by the integrating phase inverter circuit in the integrator circuit of the present invention, and fig. 8 (b) is the average current consumed by the integrating phase inverter circuit in the existing integrator circuit;

fig. 9 (a) shows the average current of the dynamic bias phase circuit in the integrator circuit of the present invention, and fig. 9 (b) shows the average current of the dynamic bias phase circuit in the conventional integrator circuit.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

The invention discloses a dynamic bias low-power-consumption integrator based on a capacitor serving as a floating voltage source, which is mainly used for a digital-to-analog conversion part of integrated circuits in the fields of high-precision low-power-consumption Delta-Sigma A/D converters and the like; comprising the following steps: the device comprises a two-phase non-overlapping clock generation circuit, an inverter circuit, a dynamic bias circuit and a static bias circuit which are connected with each other;

the dynamic bias circuit comprises a PMOS transistor M5, an NMOS transistor M6 and a floating voltage source CI; when CLK 1=1, the gates and drains of M5 and M6 are shorted to form diode connection, at this time, two diodes are connected in series with CI, the current of M5 drain flows through CI to charge the upper plate, and the current of plate under CI flows through M6 to discharge; after the floating voltage source CI charges and discharges for half a clock period, stable voltage difference is formed between the upper polar plate and the lower polar plate of the CI, so that bias voltage is provided for the capacitors C1 and C2 of the inverter circuit; when CLK 2=1, the upper and lower polar plates of the capacitor CI are short-circuited, and the charge is cleared to wait for the next charge and discharge operation; when clk2=1, the gates of M5 and M6 are respectively connected to AVDD and VSS, AVDD is the reference power supply of the integrator, and VSS is the reference ground of the integrator, so that M5 and M6 are turned off, where the input clock signal is CLK, four-way clock signals are generated, and CLK1 and CLK2 are two-phase non-overlapping signals.

Specifically, the two-phase non-overlapping clock generating circuit is composed of a digital logic gate circuit such as a NAND gate, a NOT gate and the like; the input clock signal is CLK, and generates four-way clock signals, CLK1 and CLK2 are two-phase non-overlapping signals, clk2=0 when clk1=1, and clk2=1 when clk1=0. CLK1D, CLK D is a signal delayed by a certain time interval, respectively.

The inverter circuit includes PMOS transistors M1 and M2, NMOS transistors M3 and M4, and bias capacitors C1 and C2. Wherein M1 is connected as an inverter input tube with its source connected to AVDD, its gate connected to the right plate of C1, and its drain connected to the source of M2. M2 is connected as a switch constituting the cascode structure to AVDD to turn off when clk1=1 and to a bias voltage VP when clk2=1, so that M2 is turned on. M4 is connected as an inverter input transistor with its source connected to VSS, gate connected to the C2 right plate, and drain connected to the source of M3. M3 is connected as a constituting cascode switch to VSS off when clk1=1 and to voltage VN when clk2=1, so that M3 is on. When clk1=1, the left plates of C1 and C2 are connected to the input common-mode voltage VCM, the right plates of C1 and C2 are respectively connected to the upper plate and the lower plate of CI, and the right plates of C1 and C2 are biased at a certain voltage by the floating voltage source CI of the dynamic bias circuit.

The static bias circuit includes PMOS transistors M7, M10, M11, M13, M15, NMOS transistors M8, M9, M12, M14, M16, and a resistor R1. Wherein M13, M14, M15, M16, resistor R1 forms a current source insensitive to variations in supply voltage AVDD. M14 is an NMOS current mirror transistor of a current source, and the grid electrode of the NMOS current mirror transistor is connected to the grid electrode of M16 to complete the current copying in proportion. M10 and M11 are connected into diode connection type, and static bias voltage VP is formed under the drive of certain current biased by M16. Similarly, M7 is a PMOS current mirror transistor of a current source, whose gate is connected to the gate of M15, completing the scaled replication of the current. M8 and M9 are connected into diode connection type, and static bias voltage VN is formed under the drive of a certain current of M7 bias. When clk1=1, the capacitors C3 and C4 have upper and lower plates shorted and are connected to AVDD and VSS, respectively. When clk2=1, the C3, C4 upper plates are connected to VN and VP, respectively; VN and VP are bias voltages formed by the static bias circuit.

Specifically, when the operating state of the low-power integrator is clk1=1:

the integrator is connected in circuit as shown in fig. 3 when clk1=1. M5 and M6 of the dynamic bias circuit are connected into diode connection type and are connected in series with the floating voltage source CI, at the moment, current flows through M5 to charge the upper pole plate of the CI, and meanwhile, the lower pole plate of the CI discharges through M6. In the process of charging and discharging, the gate voltage of M5 rises, the gate voltage of M6 falls, and after a certain time, CI forms a certain voltage difference, so that bias voltages are provided for C1 and C2 in the inverter circuit. At this time, the gate of M2 in the inverter circuit is connected to AVDD, and the gate of M3 is connected to VSS, so that the branch is disconnected, and the consumption of quiescent current is reduced. At this time, the upper and lower polar plates of the capacitors C3 and C4 are shorted and connected to AVDD and VSS, respectively, to provide conditions for quickly establishing bias voltages for the inverter circuit next time.

Further, the working state of the low-power integrator is as clk2=1:

the integrator is connected in circuit as shown in fig. 4 when clk2=1. Under the condition that the dynamic bias circuit provides bias voltage to the inverter circuit when clk2=1, the gate of M1 in the inverter circuit is biased by the right plate voltage of C1, and the gate of M4 is biased by the right plate voltage of C2. At this time, the input transistors M1 and M4 of the inverter have a certain static operating point. At this time, when clk1=1, the gate of M2 is connected to AVDD and is switched to VP, so that the source-drain of M2 is turned on, and the gate and M1 transistor form a cascode amplifier structure, so that the gain of the amplifier structure is improved, and the integration accuracy is improved. Similarly, when clk1=1, the gate of M3 is connected to VSS and switched to VN, so that the source-drain of M3 is turned on, and the cascode amplifier structure is formed with the M4 transistor.

Further, during operation of the complete integrator:

when clk1=1, as shown in fig. 3, the right plate of the sampling capacitor CS is connected to the input common mode voltage VCM, while the input signal VIN is sampled to the left plate of CS, and a certain voltage difference is formed between the two ends of CS. At this time, the dynamic bias circuit provides bias voltages to C1 and C2 in the integrator circuit when clk1=1 ends, and provides static bias conditions for integration of the integrator when clk2=1 arrives. At this time, the left plate of the capacitor CF is disconnected from the left plates of C1 and C2. When clk2=1, as shown in fig. 4, the left plate of the sampling capacitor CS is connected to the common mode voltage VCM, while the right plate of CS is disconnected from the common mode voltage VCM, and the left plate of the capacitor CF is connected to the left plates of C1 and C2. At this time, due to conservation of charge at both ends of the CS capacitor, the voltages of the right plates of C1 and C2 change, and the inverter starts to work, so that integration of the output end VOUT is started, wherein the integrated gain is CS/CF. At the end of integration, the voltage at the right end of CS returns to VCM, thus completing one integration process.

Compared with the prior art, the invention has the following technical characteristics:

compared with the existing dynamic bias integrator, the dynamic bias integrator is as shown in fig. 1, so that the average current of the dynamic bias circuit is greatly reduced when the integrator is in the state of clk1=1 compared with the average current of the inverter circuit when the integrator is in the state of clk2=1.

Compared with the existing dynamic bias integrator, in the design of the invention, as shown in figure 1, the floating current source consisting of PMOS and NMOS in the dynamic bias circuit is replaced by the capacitor CI, and the CI is used as a floating voltage source, so that two additional static bias voltages can be reduced, and the power consumption of the two static bias circuits is reduced. Meanwhile, as the differential pressure at two ends of the CI rises in the charging and discharging process of the CI, M5 and M6 enter a subthreshold region after the differential pressure reaches a certain degree, the current is extremely reduced, the charging and discharging of the CI starts to become slow, a large amount of current consumption is restrained, and the average current in the dynamic bias process is smaller compared with that when the PMOS and the NMOS act as floating current sources.

The integrator provided by the invention has the advantages that under the sampling frequency of 1M, the differential input is 900mv, the integral gain is 0.4, the average current of the inverter circuit is 14.88uA when the integrator is in CLK 1=1, and the average current of the dynamic bias circuit is 4.521uA when the integrator is in CLK 2=1, so that the power consumption is lower.

The invention uses Cadence software to carry out circuit design and simulation, adopts TSMC 65nm CMOS technology, the size of a basic MOS tube adopted by an inverter circuit in an integrator circuit is consistent with that of an inverter of the existing integrator, and the grid bias voltage of an input transistor of the inverter is biased at the same voltage value by a dynamic bias circuit. Design test circuit schematic as shown in fig. 5, the circuit includes two differential input integrator circuits and a common mode feedback circuit.

The main parameters of the invention are set as follows:

the power supply voltage avdd=3.3v, the input clock frequency (signal sampling frequency) with reference to the ground VSS is 1mhz, vip is 2.1V, and vin is 1.2V, i.e., the differential input 900mv. The sampling capacitance CS is 4pF and the feedback capacitance CF is 10pF, so that the integrator integral gain is 0.4, the load capacitance CL is 1pF, the floating voltage source capacitance CI is 1pF, the common mode feedback capacitance CM is 200fF, and the resistance r1=25kΩ.

(1) Functional simulation of integrator differential output

As a result of the simulation, as shown in fig. 6, under the condition that the differential input is 900mv and the integral gain is 0.4, the theoretical differential output is 360mv. The differential output voltage of the integrator of the present invention was 359.615mv as measured in fig. 6 (a), and 359.055mv as measured in fig. 6 (b), all of which were working properly.

Inverter circuit and dynamic bias circuit current contrast

Simulation results as shown in fig. 7 (a), the integrator of the present invention has a large quiescent current (fig. M1878/D) after the current of the inverter circuit has stabilized during clk2=1. While the current of the dynamic bias circuit (fig. M1879/D) tends to stabilize after gradually decreasing to a small current over time during clk1=1, so that the average current of the dynamic bias circuit is smaller during clk1=1. As shown in fig. 7 (b), the current of the inverter circuit has a large quiescent current (fig. M683/D) after the integration stabilizes during clk2=1. The current of the dynamic bias circuit after the bias is stabilized (fig. M684/D), and has a very large quiescent current that is close to the same as the inverter circuit branch, so that the average current of the dynamic bias circuit is large during clk1=1.

Phase-integrated average current of inverter circuit

As shown in FIG. 8 (a), the simulation result shows that the integrator of the invention has a clock frequency of 1M and a clock period of 1us, and as shown in the figure, a clip function in a cadence simulation software calculator intercepts a certain high level section of a clock signal CLK2, the test intercepts a current of 1.5 us-2 us, and an average current is calculated to be 14.88uA through an average function. As shown in fig. 8 (b), the conventional integrator similarly intercepts a certain high level section of the clock signal CLK2, intercepts a current of 1.5us to 2us, and calculates an average current of 14.96uA by an average function. It can be seen that under the same bias conditions, the average current consumed by the integration phase of the inventive integrator is nearly the same as that of the existing integrator.

Average current of bias phase of dynamic bias circuit

As shown in fig. 9 (a), the clock frequency of the integrator of the present invention is 1M, the clock period is 1us, as shown in the figure, a clip function in the cadence simulation software calculator intercepts a certain high level section of the clock signal CLK1, the test intercepts 2us to 2.5us of current, the average current is 4.521uA calculated by the average function, and the average current of the integration phase of the integrator of the present invention is reduced by about 70% compared with the average current of 14.88uA of the integration phase of the integrator of the present invention. As shown in fig. 9 (b), the conventional integrator also intercepts a certain high level section of the clock signal CLK1, intercepts a current of 2us to 2.5us, calculates an average current of 12.99uA by an average function, and has almost the same average current as 14.96uA of the integration phase. Under the same bias condition, the average current consumed by the integrator in the dynamic bias phase is greatly reduced, and the power consumption of the two static bias circuits is reduced by using the capacitor floating voltage source.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dynamically biased low power integrator based on a capacitor acting as a floating voltage source, comprising: the device comprises a two-phase non-overlapping clock generation circuit, an inverter circuit, a dynamic bias circuit and a static bias circuit which are connected with each other;

the dynamic bias circuit comprises a PMOS transistor M5, an NMOS transistor M6 and a floating voltage source CI; when CLK 1=1, the gates and drains of M5 and M6 are shorted to form diode connection, at this time, two diodes are connected in series with CI, the current of M5 drain flows through CI to charge the upper plate, and the current of plate under CI flows through M6 to discharge; after the floating voltage source CI charges and discharges for half a clock period, stable voltage difference is formed between the upper polar plate and the lower polar plate of the CI, so that bias voltage is provided for the capacitors C1 and C2 of the inverter circuit; when CLK 2=1, the upper and lower polar plates of the capacitor CI are short-circuited, and the charge is cleared to wait for the next charge and discharge operation; when CLK2 = 1, the gates of M5, M6 are connected to AVDD, VSS, AVDD being the reference power supply of the integrator, VSS being the reference ground of the integrator, such that M5, M6 are turned off, wherein the input clock signal is CLK, four-way clock signals are generated, CLK1 and CLK2 are two-phase non-overlapping signals;

the inverter circuit comprises PMOS transistors M1 and M2, NMOS transistors M3 and M4 and bias capacitors C1 and C2; wherein M1 is used as an input tube of the inverter, the source electrode of the input tube is connected to AVDD, the grid electrode of the input tube is connected to the right polar plate of C1, and the drain electrode of the input tube is connected to the source electrode of M2; m2 is connected to AVDD to be turned off when clk1=1 and to the bias voltage VP when clk2=1 as a switch constituting the cascode structure, so that M2 is turned on; m4 is used as an inverter input transistor, the source electrode of the transistor is connected to VSS, the grid electrode of the transistor is connected to the right polar plate of C2, and the drain electrode of the transistor is connected to the source electrode of M3; m3 as a switch constituting a cascode structure, the gate of which is connected to VSS off when clk1=1 and to voltage VN when clk2=1, so that M3 is on; when CLK 1=1, the left plates of C1 and C2 are connected to the input common-mode voltage VCM, the right plates of C1 and C2 are respectively connected to the upper plate and the lower plate of CI, and the right plates of C1 and C2 are biased at a certain voltage by the floating voltage source CI of the dynamic bias circuit;

the static bias circuit comprises PMOS transistors M7, M10, M11, M13 and M15, NMOS transistors M8, M9, M12, M14 and M16 and a resistor R1; wherein, the resistors R1 form a current source insensitive to the change of the power supply voltage AVDD, M13, M14, M15 and M16; m14 is an NMOS current mirror transistor of a current source, and the grid electrode of the NMOS current mirror transistor is connected to the grid electrode of M16 to complete the proportional copying of current; m10 and M11 are connected into diode connection type, and static bias voltage VP is formed under the drive of certain current biased by M16; similarly, M7 is a PMOS current mirror transistor of a current source, and the grid electrode of the PMOS current mirror transistor is connected to the grid electrode of M15 to complete the proportional replication of current; m8 and M9 are connected into diode connection type, and static bias voltage VN is formed under the drive of certain current of M7 bias; when the capacitors C3 and C4 are in CLK 1=1, the upper polar plate and the lower polar plate are in short circuit and are respectively connected to AVDD and VSS; when clk2=1, the upper plates of C3 and C4 are connected to VN and VP, respectively, which are bias voltages formed by the static bias circuit.

2. The dynamically biased low power integrator functioning as a floating voltage source based on a capacitor of claim 1, wherein the two-phase non-overlapping clock generating circuit is comprised of a nand gate and a nor gate digital logic gate circuit; wherein clk1=1, clk2=0, clk1=0, clk2=1; CLK1D, CLK D is a signal delayed by a certain time interval, respectively.

3. The dynamically biased low power integrator functioning as a floating voltage source based on a capacitor of claim 1, wherein the low power integrator operates in a state of clk1=1:

when CLK 1=1, the integrator connects M5 and M6 of the dynamic bias circuit into diode connection, and connects in series with the floating voltage source CI, at this time, the current flows through M5 to charge the upper plate of CI, and at the same time, the lower plate of CI discharges through M6; in the charge and discharge process, the gate voltage of M5 rises, the gate voltage of M6 falls, and after a certain time, CI forms a certain voltage difference, so that bias voltages are provided for C1 and C2 in the inverter circuit; at this time, the grid electrode of M2 in the inverter circuit is connected to AVDD, the grid electrode of M3 is connected to VSS, at this time, the upper and lower polar plates of the capacitors C3 and C4 are in short circuit and are respectively connected to AVDD and VSS, so that conditions are provided for quickly establishing bias voltage for the inverter circuit next time.

4. A dynamically biased low power integrator based on a capacitor acting as a floating voltage source according to claim 3, characterized in that the low power integrator operates in a state where clk2=1:

when the integrator is in CLK 2=1, under the condition that the dynamic bias circuit provides bias voltage for the inverter circuit, the grid electrode of M1 in the inverter circuit is biased by the right plate voltage of C1, and the grid electrode of M4 is biased by the right plate voltage of C2; at this time, the input transistors M1 and M4 of the inverter have a certain static operating point; at this time, the gate of M2 is connected to AVDD when clk1=1, and is switched to VP, so that the source-drain of M2 is turned on, and forms a cascode amplifier structure with the M1 transistor, and the gate of M3 is connected to VSS when clk1=1, and is switched to VN, so that the source-drain of M3 is turned on, and forms a cascode amplifier structure with the M4 transistor.

5. The dynamically biased low power integrator functioning as a floating voltage source based on a capacitor of claim 4 wherein, during operation of the complete integrator:

when clk1=1, the right plate of the sampling capacitor CS is connected to the input common mode voltage VCM, while the input signal VIN is sampled to the left plate of CS, and a certain voltage difference is formed at two ends of CS; at the moment, when the CLK 1=1 is ended, the dynamic bias circuit provides bias voltages for C1 and C2 in the integrator circuit, and provides a static bias condition for integration of the integrator when the CLK 2=1 arrives; at this time, the left plate of the capacitor CF is disconnected from the left plates of C1 and C2, and when clk2=1, the left plate of the sampling capacitor CS is connected to the common mode voltage VCM, and the right plate of the sampling capacitor CS is disconnected from the common mode voltage VCM, and the left plate of the capacitor CF is connected to the left plates of C1 and C2; at the moment, as the charge at two ends of the CS capacitor is conserved, the voltages of the right polar plates of C1 and C2 are changed, and the inverter starts to work, so that the integration of the output end VOUT is started, wherein the integrated gain is CS/CF; at the end of integration, the voltage at the right end of CS returns to VCM, thus completing one integration process.