CN114866088A - Low-power-consumption integrator circuit based on dynamic access inverter and working method thereof - Google Patents
Low-power-consumption integrator circuit based on dynamic access inverter and working method thereof Download PDFInfo
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Abstract
A low-power-consumption integrator circuit based on a dynamic access inverter and a working method thereof relate to the technical field of analog integrated circuits and comprise a dynamic bias inverter, a dynamic access branch circuit, a sampling capacitor and an integrating capacitor. The invention has the beneficial effects that: the dynamic access branch is added on the basis of the traditional integrator circuit based on the dynamic phase inverter, when the integrator works in a sampling phase, only a small static current is needed, and when the integrator works in an integration phase, the dynamic access branch works to provide a large dynamic current for the integrator, so that the output of the integrator can be quickly established.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a low-power-consumption integrator circuit based on a dynamic access phase inverter and a working method thereof.
Background
With the continuous development of the internet of things technology, the market demand of various portable devices such as mobile phones and wearable devices is increasing, various integrated circuit chips are core components of the devices, the rapid development and the market demand of the portable devices are increasing, and higher requirements are put on the performances of various chips. Because the chip in the portable device needs to be powered by a battery, but the energy stored by the battery is limited, in order to prolong the service life of the battery, the power consumption of the whole chip also needs to be reduced while the storage capacity of the battery is increased. The digital-to-analog converter chip is widely applied to various portable devices, and the application scene of the internet of things puts forward new requirements on the performance of the digital-to-analog converter chip, for example, when the precision and the speed are improved, the power consumption is expected to be reduced as much as possible, and how to compromise the performances such as the power consumption, the precision and the speed becomes a hot content in the current ADC circuit research. The integrator circuit is a key circuit in the digital-to-analog converter chip, and the performance of the integrator circuit plays a crucial role in various performances of the ADC chip.
The conventional static amplifier circuit is used in the conventional integrator, when the conventional static amplifier is in a high-speed application scene, a very large static power consumption is needed to provide a large current for the integrator to accelerate the response speed of the integrator, but since the mobile device is powered by a battery, in order to prolong the service time of the battery, higher and higher requirements are put on the power consumption performance of the integrator, if the power consumption of the integrator needs to be reduced, the static current of the amplifier needs to be reduced, but the reduction of the static current can cause the bandwidth performance of the amplifier to be sharply reduced, so that the response speed of the amplifier is reduced, and the conventional static amplifier circuit is not suitable for the high-speed application scene, so how to consider the performances of the integrator circuit, such as low power consumption, quick response and the like, becomes a difficult point of circuit design.
The limitations and solutions of the conventional techniques are: literature referenceAn integrator circuit based on a Dynamic Bias Inverter is proposed in an a 300- μ W Audio Δ Σ Modulator with100.5-dB DR Using Dynamic Bias Inverter, and is used in a sigma delta Modulator, the integrator circuit of the Dynamic Bias Inverter is shown in fig. 2, and the integrator is controlled by two non-overlapping clocks, and can be divided into two working phases: a sampling phase and an integration phase; when the integrator is operating in the sampling phase, as shown in fig. 3, the input signal V IN Sampling capacitor C S Charging while floating current source I Q For the input pipe M n1 And M p1 Thereby charging the input tube M n1 And M p1 Provides a DC bias voltage and stores the bias voltage in a capacitor C c1 And C c2 The above step (1); when the integrator works in the integrating phase, as shown in FIG. 4, the amplifier main circuit is composed of an input tube M n1 And M p1 Cascode tube M n2 And M p2 Forming an amplifier based on Cascode inverter, sampling the capacitor C S The amount of charge on is integrated into an integrating capacitor C I To obtain an integrated voltage V at the output of the integrator OUT 。
However, in order to increase the speed of output setup when the integrator is operating in the integration phase, a floating current source I for charging the gate of the input tube when the integrator is operating in the sampling phase is required Q The current value of (2) is designed to be larger, so that the integrator circuit still needs a larger static circuit and consumes larger static power consumption.
Disclosure of Invention
The invention aims to provide a low-power-consumption integrator circuit based on a dynamic access inverter and a working method thereof, aiming at the problem of large static power consumption of the traditional integrator based on the dynamic bias inverter, and the integrator circuit can provide higher output establishment speed while keeping low power consumption of the integrator circuit.
In order to achieve the above object, a first aspect of the present invention provides a low power consumption integrator circuit based on a dynamic access inverter, comprising a dynamic bias inverter, a dynamic access branch, a sampling capacitor and an integration capacitor, wherein the dynamic bias inverter comprises a switch S 1 And openerOff S 2 And a switch S 3 Switch S 4 Switch S 5 Switch S 6 Switch S 7 And a switch S 8 Switch S 9 Switch S 10 Switch S 11 Switch S 12 MOS transistor M n1 MOS transistor M n3 MOS transistor M n4 MOS transistor M n5 MOS transistor M p1 MOS transistor M p3 MOS transistor M p4 MOS transistor M p5 Capacitor C c1 Capacitor C c2 Sampling capacitor C S Integral capacitance C I Wherein the MOS transistor M n1 Gate and capacitor C c1 Right pole plate and switch S 2 Is connected with the left end of the MOS tube M n1 Source electrode of the MOS transistor M is connected with VSS and MOS transistor M n1 Drain electrode of (1) and MOS transistor M n3 Is connected with the source electrode of the MOS transistor M n3 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n3 Drain electrode and integrating capacitor C I Is connected with the right polar plate of the MOS tube M n4 Source electrode and MOS transistor M n1 Is connected with the drain electrode of the MOS transistor M n4 Gate of (2) and switch S 8 Is connected with the right end of the MOS tube M n4 And a switch S 2 Is connected with the right end of the MOS tube M n5 Source electrode and MOS transistor M n4 Is connected with the drain electrode of the MOS tube M n5 Grid of (C) is connected with V bn MOS transistor M n5 Drain electrode of (1) and MOS transistor M p5 Is connected with the source electrode of the MOS transistor M p5 Grid of is connected with V bp MOS transistor M p5 Source electrode and MOS transistor M n4 Is connected with the drain electrode of the MOS transistor M p4 Gate of (2) and switch S 6 Is connected with the left end of the MOS tube M p4 Source electrode and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p3 Gate of (2) and switch S 7 Is connected with the left end of the MOS tube M p3 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p1 Gate and capacitor C c2 Is connected with the right polar plate of the MOS tube M p1 Drain electrode of (1) and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p1 The source of the transistor is connected to VDD; capacitor C c2 Left polar plate and sampling capacitor C s Is connected with the right polar plate of the sampling capacitor C s The left pole plate of the plate is connected with the V IN Integral capacitance C I Left pole plate ofSwitch S 1 Right end of (1), integrating capacitor C I The right pole plate is connected with V OUT Capacitor C c1 Left polar plate and capacitor C S Is connected with the right polar plate of the capacitor C c1 Right polar plate and MOS tube M n1 The grid electrodes are connected; switch S 1 Left end of and sampling capacitor C S Is connected with the right polar plate of the switch S 1 Right end of (1) and an integrating capacitor C I Is connected with the left polar plate of the switch S 2 Left end of and capacitor C c1 Is connected with the right polar plate of the switch S 2 Right end of and MOS tube M n4 Is connected to the drain of the switch S 3 Left end of and capacitor C c2 Is connected with the right polar plate of the switch S 3 Right end of and MOS tube M p4 Is connected to the drain of the switch S 4 Is connected to VDD, switch S 4 And a switch S 6 Is connected to the left end of the switch S 5 Is connected to VDD, switch S 5 And a switch S 7 Is connected to the left end of the switch S 6 Right end connected with V b0 Switch S 7 Right end connected with V b0 Switch S 8 Is connected to VSS, switch S 8 And a switch S 11 Is connected to the left end of the switch S 9 Is connected to VSS, switch S 9 And a switch S 10 Is connected to the left end of the switch S 10 Right end connected with V b1 Switch S 11 Right end connected with V b1 Switch S 12 Is connected with the left end V CM Switch S 12 Right end of and a capacitor C c1 The left polar plate is connected;
the dynamic access branch comprises an MOS (metal oxide semiconductor) transistor M n2 MOS tube M p2 MOS transistor M n14 MOS transistor M p14 Wherein the MOS transistor M n2 Grid and MOS tube M n1 Grid connected MOS transistor M n2 Drain electrode of (1) and MOS transistor M n14 Is connected with the source electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p2 Drain electrode of (1) and MOS transistor M p14 Is connected with the source electrode of the MOS transistor M p2 Is connected with VDD, and a MOS tube M p2 Grid and MOS tube M p1 Is connected with the grid of the MOS transistor M p14 Gate of (2) and switch S 7 Is connected with the left end of the MOS tubeM p14 Source electrode and MOS transistor M p2 Is connected with the drain electrode of the MOS transistor M p14 Drain electrode of (1) and MOS transistor M p3 Is connected with the drain electrode of the MOS transistor M n14 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n14 Source electrode and MOS transistor M n2 Is connected with the drain electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Are connected.
In a second aspect of the present invention, a working method of a low power consumption integrator circuit based on a dynamic access inverter is provided, where the working process of the dynamic bias inverter is: the working process of the dynamic bias inverter is controlled by two-phase non-overlapping clocks and can be divided into a sampling phase and an integral phase, and when the dynamic bias inverter works in the sampling phase, the switch S 1 Open, switch S 12 Conduction, V IN Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s Is connected to V CM Input signal V IN Is sampled to a sampling capacitor C s The above step (1); switch S 4 Switch S 7 Open, switch S 5 Switch S 6 On, M p4 Is connected to V b0 Thereby conducting MOS transistor M p4 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p3 MOS transistor M p14 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 Open, switch S 9 Switch S 11 Conducting MOS transistor M n4 Is connected to V b1 Thereby conducting MOS transistor M n4 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n3 MOS transistor M n14 The gate of which is connected to VSS and thus turned off; switch S 2 Switch S 3 Conducting MOS transistor M p1 Grid and MOS tube M p4 Is connected with the drain electrode of the MOS transistor M n1 Grid and MOS tube M n4 Is connected with the drain electrode of the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tubes M p1 MOS transistor M n1 Charging the grid electrode of the input tube to a pre-designed direct current level and enabling the input tube MOS tube M to be connected with the grid electrode p1 MOS transistor M n1 Biased to subthreshold operationState, and store bias voltage to the capacitor C c1 And a capacitor C c2 The above step (1);
when the dynamically biased inverter is operating in the integrating phase, switch S 1 On, switch S 12 Opening, V CM Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s Is connected to C I The left pole plate of (1); switch S 4 Switch S 7 On, switch S 5 Switch S 6 Disconnected, MOS transistor M p3 MOS transistor M p14 Is connected to V b0 Thereby conducting MOS transistor M p3 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p4 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 On, switch S 9 Switch S 11 Disconnected, MOS transistor M n3 MOS transistor M n14 Is connected to V b1 Thereby conducting MOS transistor M n3 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n4 The gate of which is connected to VSS and thus turned off; switch S 2 Switch S 3 Is disconnected, thereby making the MOS tube M n5 MOS transistor M p5 Composed floating current source and input tube MOS tube M p1 MOS transistor M n1 Disconnection based on MOS transistor M p1 MOS transistor M p2 MOS transistor M p3 MOS transistor M n1 MOS transistor M n2 MOS transistor M p3 The formed inverter is used as an amplifier in an integrator, and a sampling capacitor C is used s Is driven to V CM Thereby enabling the capacitance C to be sampled s Is transferred to the integrating capacitor C I According to the principle of conservation of charge, V can be obtained OUT Is equal to
The working process of the dynamic access branch circuit is as follows: the dynamic access branch is controlled by two non-overlapping clocks and can be divided into a sampling phase and an integral phase; when the dynamic access branch works at the sampling phase, the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tube M p2 MOS transistor M n2 The grid electrode of the transistor is charged to a pre-designed DC level due to the MOS transistor M p2 And MOS transistor M n2 The drain of the transistor is disconnected, so that the floating current source only needs to supply the MOS transistor M p1 MOS transistor M n1 Providing drain-source current to bias it to subthreshold region without providing MOS transistor M p2 And MOS transistor M n2 Providing drain-source bias current and also providing the MOS transistor M with the same p2 And MOS transistor M n2 Provides a bias voltage to the grid and stores the bias voltage in a capacitor C c1 And a capacitor C c2 The above step (1); when the dynamic access branch works in an integral phase, based on the MOS transistor M p2 MOS transistor M p14 MOS transistor M n2 MOS transistor M n14 Dynamic access branch and MOS transistor M based on same p1 MOS transistor M p2 MOS transistor M p3 MOS transistor M n1 MOS transistor M n2 MOS transistor M p3 The formed inverters are connected in parallel to be used as an amplifier in the integrator, and the dynamic access branch circuit provides additional dynamic current to the integrating capacitor C I Charging to accelerate the rapid build-up of integrator output voltage, thereby enabling V OUT Is reached more quickly
The invention has the beneficial effects that: (1) the low-power-consumption integrator circuit based on the dynamic bias phase inverter has the advantages of low power consumption and is only 1 muA in quiescent current, and the low-power-consumption integrator circuit is suitable for the requirements of low power consumption and quick response of various application scenes of the Internet of things; (2) the invention improves the structure of the traditional integrator circuit based on the dynamic bias phase inverter, adds a dynamic access branch, enables the integrator to quickly respond in the integral phase by only needing extremely low static current bias input tube when the integrator works in the sampling phase, reduces the power consumption of the integrator circuit, and simultaneously enables the output of the integrator to be quickly established, thereby ensuring the dynamic performance of the integrator.
Drawings
FIG. 1 is a schematic diagram of the overall circuit of a low power consumption integrator based on a dynamic access inverter according to the present invention;
FIG. 2 is a schematic diagram of a conventional dynamic bias inverter based integrator circuit;
FIG. 3 is a schematic diagram of a conventional dynamic bias inverter based integrator circuit when the integrator is operating in the sampling phase;
FIG. 4 is a schematic diagram of a conventional dynamically biased inverter based integrator circuit when the integrator is operating in the integration phase;
FIG. 5 is a schematic diagram of two phase non-overlapping clocks used in the present invention;
FIG. 6 is a simplified diagram of a low power integrator circuit based on a dynamic access inverter according to the present invention;
FIG. 7 is a simplified circuit diagram of a low power consumption integrator based on a dynamic access inverter according to the present invention when the integrator is operating in the sampling phase;
FIG. 8 is a simplified diagram of a low power integrator circuit based on a dynamically switched-in inverter according to the present invention when the integrator is operating in the integration phase; FIG. 9 is a schematic diagram of a circuit of the low power consumption integrator operating in a sampling phase based on dynamic access according to the present invention;
FIG. 10 is a schematic circuit diagram of the low power consumption integrator operating in the integration phase based on dynamic access according to the present invention;
FIG. 11 shows power consumption simulation results in an embodiment of the present invention;
FIG. 12 is a simulation result of step response in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following drawings and examples, but the invention is not limited thereto.
The dynamic access circuit is added on the basis of the traditional integrator circuit based on the dynamic bias inverter, the circuit diagram is shown as figure 6, when the integrator works at the sampling phase, the circuit diagram is shown as figure 7, and the input signal V is IN Sampling capacitor C S Charging while floating current source I Q For the input pipe M n1 And M p1 Charging the input tube M while the grid electrode of the transistor is charged n2 And M p2 Charging the gate, but not necessarily M n2 And M p2 Providing a drain-source current; when the integrator works in the integrating phase, as shown in FIG. 8, the amplifier main body circuit is composed of an input tube M n1 、M n2 、M p1 And M p2 Cascode pipe M n2 、M n14 、M p2 、M p14 Forming an amplifier based on Cascode inverter, sampling the capacitor C S The amount of charge on is transferred to the integrating capacitor C I To obtain an integrated voltage V at the output of the integrator OUT . Compared with the traditional integrator circuit based on the dynamic bias phase inverter, the low-power-consumption integrator circuit based on the dynamic access phase inverter can greatly reduce the static power consumption and simultaneously can quickly establish the output of the integrator.
The invention provides a low-power-consumption integrator circuit dynamically accessed to a phase inverter and a working method thereof.A dynamic access branch is added, an amplifier circuit based on the phase inverter can be biased by extremely low static current when the integrator works in a sampling phase, and larger dynamic current can be provided when the integrator works in an integrating phase so as to quickly establish the output of the integrator, so that the integrator circuit can quickly respond and consume extremely low power consumption.
As shown in fig. 1, the low power consumption integrator circuit based on the dynamic access inverter of the present invention includes a dynamic bias inverter, a dynamic access branch, a sampling capacitor, and an integrating capacitor, wherein:
1. dynamically biased inverter
The dynamically biased inverter includes a switch S 1 Switch S 2 Switch S 3 Switch S 4 Switch S 5 Switch S 6 Switch S 7 And a switch S 8 Switch S 9 Switch S 10 Switch S 11 Switch S 12 MOS transistor M n1 MOS transistor M n3 MOS transistor M n4 MOS transistor M n5 MOS transistor M p1 MOS transistor M p3 MOS transistor M p4 MOS transistor M p5 Capacitor C c1 Capacitor C c2 Sampling capacitor C S Integral ofCapacitor C I . Wherein the MOS transistor M n1 Gate and capacitor C c1 Right pole plate and the sum switch S 2 Is connected with the left end of the MOS tube M n1 Source electrode of the MOS transistor M is connected with VSS and MOS transistor M n1 Drain electrode of (1) and MOS transistor M n3 Is connected with the source electrode of the MOS transistor M n3 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n3 Drain electrode and integrating capacitor C I Is connected with the right polar plate of the MOS tube M n4 Source electrode and MOS transistor M n1 Is connected with the drain electrode of the MOS transistor M n4 Gate of (2) and switch S 8 Is connected with the right end of the MOS tube M n4 And switch S 2 Is connected with the right end of the MOS tube M n5 Source electrode and MOS transistor M n4 Is connected with the drain electrode of the MOS tube M n5 Grid of is connected with V bn MOS transistor M n5 Drain electrode of (1) and MOS transistor M p5 Is connected with the source electrode of the MOS transistor M p5 Grid of is connected with V bp MOS transistor M p5 Source electrode and MOS transistor M n4 Is connected with the drain electrode of the MOS transistor M p4 Gate of (2) and switch S 6 Is connected with the left end of the MOS tube M p4 Source electrode and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p3 Gate of (2) and switch S 7 Is connected with the left end of the MOS tube M p3 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p1 Gate and capacitor C c2 Is connected with the right polar plate of the MOS tube M p1 Drain electrode of (1) and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p1 The source of the transistor is connected to VDD; capacitor C c2 Left polar plate and sampling capacitor C s Is connected with the right polar plate of the sampling capacitor C s The left pole plate is connected with V IN Integral capacitance C I Left pole plate of (1) is connected with switch S 1 Right end of (1), integrating capacitor C I The right pole plate is connected with V OUT Capacitor C c1 Left polar plate and sampling capacitor C S Is connected with the right polar plate of the capacitor C c1 Right polar plate and MOS tube M n1 The grid electrodes are connected; switch S 1 Left end of and sampling capacitor C S Is connected with a switch S 1 Right end of (1) and an integrating capacitor C I Is connected with the left polar plate of the switch S 2 Left end of and capacitor C c1 Is connected with the right polar plate of the switch S 2 Right end of (D) and MOS tube M n4 Is connected to the drain of the switch S 3 Left end of and capacitor C c2 Is connected with the right polar plate of the switch S 3 Right end of and MOS tube M p4 Is connected to the drain of the switch S 4 Is connected to VDD, switch S 4 And a switch S 6 Is connected to the left end of the switch S 5 Is connected to VDD, switch S 5 And a switch S 7 Is connected to the left end of the switch S 6 Right end connected with V b0 Switch S 7 Right end connected with V b0 Switch S 8 Is connected to VSS, switch S 8 And a switch S 11 Is connected to the left end of the switch S 9 Is connected to VSS, switch S 9 And a switch S 10 Is connected to the left end of the switch S 10 Right end connected with V b1 Switch S 11 Right end connected with V b1 Switch S 12 Is connected with the left end V CM Switch S 12 Right end of and a capacitor C c1 The left pole plate is connected.
The working process of the dynamic bias inverter is as follows:
the working process of the dynamic bias inverter is controlled by two non-overlapping clocks and can be divided into a sampling phase and an integration phase.
When the dynamically biased inverter is operating in the sampling phase, the circuit is as shown in FIG. 9, with switch S 1 Open, switch S 12 Conduction, V IN Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s Is connected to V CM Input signal V IN Is sampled to a sampling capacitor C s The above step (1); switch S 4 And a switch S 7 Open, switch S 5 Switch S 6 Conducting MOS transistor M p4 Is connected to V b0 Thereby conducting MOS transistor M p4 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p3 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 Open, switch S 9 Switch S 11 Conducting MOS transistor M n4 Is connected to V b1 Thereby conducting MOS transistor M n4 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n3 Is connected to the gridTo VSS and thus off; switch S 2 Switch S 3 Conducting MOS transistor M p1 Grid of (3) and MOS tube M p4 Is connected with the drain electrode of the MOS transistor M n1 Grid and MOS tube M n4 Is connected with the drain electrode of the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tubes M p1 MOS tube M n1 Charging the grid electrode of the input tube to a pre-designed direct current level and enabling the input tube MOS tube M to be connected with the grid electrode p1 MOS transistor M n1 Bias to sub-threshold working state and store bias voltage to capacitor C c1 And a capacitor C c2 The above.
When the dynamically biased inverter is operating in the integration phase, the circuit is as shown in FIG. 10, with switch S 1 On, switch S 12 Opening, V CM Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s The right pole plate of the capacitor is connected to an integrating capacitor C I The left pole plate of (1); switch S 4 Switch S 7 On, switch S 5 Switch S 6 Disconnected, MOS transistor M p3 MOS transistor M p14 Is connected to V b0 Thereby conducting MOS transistor M p3 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p4 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 On, switch S 9 Switch S 11 Disconnected, MOS transistor M n3 MOS transistor M of switch n14 Is connected to V b1 Thereby conducting MOS transistor M n3 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n4 The gate of which is connected to VSS and thus turned off; switch S 2 Switch S 3 Is disconnected, thereby making the MOS tube M n5 MOS transistor M p5 Constructed floating current source and input tube M p1 、M n1 Disconnection based on MOS transistor M p1 MOS transistor M p2 MOS tube M p3 MOS tube M n1 MOS transistor M n2 MOS transistor M p3 The formed inverter is used as an amplifier in an integrator, and a sampling capacitor C is used s Is driven to V CM Thereby enabling the capacitance C to be sampled s Is transferred to the integrating capacitor C I According to the principle of conservation of charge, V can be obtained OUT Is equal to
2. Dynamic access leg
The dynamic access branch comprises an MOS (metal oxide semiconductor) transistor M n2 MOS transistor M p2 MOS transistor M n14 MOS transistor M p14 Wherein the MOS transistor M n2 Grid and MOS tube M n1 Grid connected MOS transistor M n2 Drain electrode of (1) and MOS transistor M n14 Is connected with the source electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p2 Drain electrode of (1) and MOS transistor M p14 Is connected with the source electrode of the MOS transistor M p2 Is connected with VDD, and a MOS tube M p2 Grid and MOS tube M p1 Is connected with the grid of the MOS transistor M p14 Gate of (2) and switch S 7 Is connected with the left end of the MOS tube M p14 Source electrode and MOS transistor M p2 Is connected with the drain electrode of the MOS tube M p14 Drain electrode of (1) and MOS transistor M p3 Is connected with the drain electrode of the MOS transistor M n14 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n14 Source electrode of (3) and MOS transistor M n2 Is connected with the drain electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Are connected.
The working process of the dynamic access branch comprises the following steps:
the dynamic access branch is controlled by two non-overlapping clocks and can be divided into a sampling phase and an integral phase.
When the dynamic access branch works in the sampling phase, as shown in fig. 9, the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tubes M p2 MOS transistor M n2 The grid electrode of the transistor is charged to a pre-designed DC level due to the MOS transistor M p2 And MOS transistor M n2 The drain of the transistor is disconnected, so that the floating current source only needs to supply the MOS transistor M p1 MOS tube M n1 Providing current to bias it to subthreshold region without providing MOS transistor M p2 And MOS transistor M n2 Providing bias current and also providing bias current to MOS transistor M p2 And MOS tubeM n2 Provides a bias voltage to the grid and stores the bias voltage in a capacitor C c1 And a capacitor C c2 The above.
When the dynamic access branch works in an integral phase, based on the MOS transistor M p2 MOS transistor M p14 MOS transistor M n2 MOS transistor M n14 Dynamic access branch and MOS transistor M based on same p1 MOS transistor M p2 MOS transistor M p3 MOS transistor M n1 MOS transistor M n2 MOS transistor M p3 The formed inverters are connected in parallel to be used as an amplifier in the integrator, and the dynamic access branch circuit provides additional dynamic current to the integrating capacitor C I Charging to accelerate the rapid build-up of integrator output voltage, thereby enabling V OUT Is reached more quickly
FIG. 5 is a schematic diagram of two-phase non-overlapping clocks, CLK1 and CLK2 being two-phase non-overlapping clocks with switch S 1 Switch S 4 Switch S 7 Switch S 8 Switch S 10 Under control of CLK 1; switch S 2 Switch S 3 And a switch S 5 Switch S 6 Switch S 9 Switch S 11 Switch S 12 Controlled by CLK 2.
Fig. 11 shows the simulation result of the power consumption of the integrator circuit of the present invention, when the power supply voltage VDD is 1.8V, the integrator only consumes 1uA of quiescent current when operating in the sampling phase.
FIG. 12 shows the simulation result of step response of the integrator circuit of the present invention, when the power voltage VDD is 1.8V and the sampling capacitance C is s At 2pF, integrating capacitor C I At 8pF, 5pF load capacitance, 600mV input step signal, 149.76mV output signal amplitude, 0.24mV difference from the ideal output of 150mV, 99.85% precision, 0.12 μ s settling time.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and it should be understood by those of ordinary skill in the art that the specific embodiments of the present invention can be modified or substituted with equivalents with reference to the above embodiments, and any modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims to be appended.
Claims (3)
1. The low-power-consumption integrator circuit based on the dynamic access inverter is characterized by comprising a dynamic bias inverter, a dynamic access branch circuit, a sampling capacitor and an integrating capacitor, wherein the dynamic bias inverter comprises a switch S 1 Switch S 2 Switch S 3 Switch S 4 Switch S 5 Switch S 6 Switch S 7 Switch S 8 And a switch S 9 Switch S 10 Switch S 11 Switch S 12 MOS transistor M n1 MOS transistor M n3 MOS transistor M n4 MOS transistor M n5 MOS transistor M p1 MOS tube M p3 MOS transistor M p4 MOS transistor M p5 Capacitor C c1 Capacitor C c2 Sampling capacitor C S Integral capacitance C I Wherein the MOS transistor M n1 Gate and capacitor C c1 Right pole plate and switch S 2 Is connected with the left end of the MOS tube M n1 Source electrode of the MOS transistor M is connected with VSS and MOS transistor M n1 Drain electrode of (1) and MOS transistor M n3 Is connected with the source electrode of the MOS transistor M n3 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n3 Drain electrode and integrating capacitor C I Is connected with the right polar plate of the MOS tube M n4 Source electrode of (3) and MOS transistor M n1 Is connected with the drain electrode of the MOS transistor M n4 Gate of (2) and switch S 8 Is connected with the right end of the MOS tube M n4 And switch S 2 Is connected with the right end of the MOS tube M n5 Source electrode and MOS transistor M n4 Is connected with the drain electrode of the MOS transistor M n5 Grid of is connected with V bn MOS transistor M n5 Drain electrode of (1) and MOS transistor M p5 Is connected with the source electrode of the MOS transistor M p5 Grid of is connected with V bp MOS transistor M p5 Source electrode of (3) and MOS transistor M n4 Is connected with the drain electrode of the MOS transistor M p4 Gate of (2) and switch S 6 Is connected with the left end of the MOS tube M p4 Source electrode and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p3 Gate of (2) and switch S 7 Is connected with the left end of the MOS tube M p3 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p1 Gate and capacitor C c2 Is connected with the right polar plate of the MOS tube M p1 Drain electrode of (1) and MOS transistor M p3 Is connected with the source electrode of the MOS transistor M p1 The source of the transistor is connected to VDD; capacitor C c2 Left polar plate and sampling capacitor C s Is connected with the right polar plate of the sampling capacitor C s The left pole plate is connected with V IN Integral capacitance C I Left pole plate of (1) is connected with switch S 1 Right end of (1), integrating capacitor C I The right pole plate is connected with V OUT Capacitor G c1 Left polar plate and capacitor C S Is connected with the right polar plate of the capacitor C c1 Right polar plate and MOS tube M n1 The grid electrodes are connected; switch S 1 Left end of and sampling capacitor C S Is connected with the right polar plate of the switch S 1 Right end of (1) and an integrating capacitor C I Is connected with the left polar plate of the switch S 2 Left end of and capacitor C c1 Is connected with the right polar plate of the switch S 2 Right end of and MOS tube M n4 Is connected to the drain of the switch S 3 Left end of and capacitor C c2 Is connected with a switch S 3 Right end of and MOS tube M p4 Is connected to the drain of the switch S 4 Is connected to VDD, switch S 4 And a switch S 6 Is connected to the left end of the switch S 5 Is connected to VDD, switch S 5 And a switch S 7 Is connected to the left end of the switch S 6 Right end connected with V b0 Switch S 7 Right end connected with V b0 Switch S 8 Is connected to VSS, switch S 8 And a switch S 11 Is connected to the left end of the switch S 9 Is connected to VSS, switch S 9 And a switch S 10 Is connected to the left end of the switch S 10 Right end connected with V b1 Switch S 11 Right end connected with V b1 Switch S 12 Is connected with the left end V CM Switch S 12 Right end of (1) and a capacitor C c1 The left polar plate is connected;
the dynamic access branch comprises an MOS (metal oxide semiconductor) transistor M n2 MOS transistor M p2 MOS transistor M n14 MOS transistor M p14 Wherein the MOS transistor M n2 Grid and MOS tube M n1 Grid connected MOS transistor M n2 Drain electrode of (1) and MOS transistor M n14 Is connected with the source electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Is connected with the drain electrode of the MOS transistor M p2 Drain electrode of (1) and MOS transistor M p14 Is connected with the source electrode of the MOS transistor M p2 Is connected with VDD, and a MOS tube M p2 Grid and MOS tube M p1 Is connected with the grid of the MOS transistor M p14 Gate of (2) and switch S 7 Is connected with the left end of the MOS tube M p14 Source electrode and MOS transistor M p2 Is connected with the drain electrode of the MOS transistor M p14 Drain electrode of (1) and MOS transistor M p3 Is connected with the drain electrode of the MOS transistor M n14 Gate of (2) and switch S 10 Is connected with the left end of the MOS tube M n14 Source electrode and MOS transistor M n2 Is connected with the drain electrode of the MOS transistor M n14 Drain electrode of (1) and MOS transistor M n3 Are connected.
2. The method for operating the low power consumption integrator circuit based on the dynamic access inverter as claimed in claim 1, wherein the operation process of the dynamic bias inverter is as follows: the working process of the dynamic bias inverter is controlled by two-phase non-overlapping clocks and can be divided into a sampling phase and an integral phase, and when the dynamic bias inverter works in the sampling phase, the switch S 1 Open, switch S 12 Conduction, V IN Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s Is connected to V CM Input signal V IN Is sampled to a sampling capacitor C s The above step (1); switch S 4 Switch S 7 Open, switch S 5 Switch S 6 On, M p4 Is connected to V b0 Thereby conducting MOS transistor M p4 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p3 MOS transistor M p14 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 Open, switch S 9 Switch S 11 Conducting MOS transistor M n4 Is connected to V b1 Thereby conducting MOS transistor M n4 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n3 MOS transistor M n14 Is connected to the gridTo VSS and thus off; switch S 2 Switch S 3 Conducting MOS transistor M p1 Grid and MOS tube M p4 Is connected with the drain electrode of the MOS transistor M n1 Grid and MOS tube M n4 Is connected with the drain electrode of the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tubes M p1 MOS transistor M n1 Charging the grid electrode of the input tube to a pre-designed direct current level and enabling the input tube MOS tube M to be connected with the grid electrode p1 MOS transistor M n1 Bias to sub-threshold working state and store bias voltage to capacitor C c1 And a capacitor C c2 C, removing;
when the dynamically biased inverter is operating in the integrating phase, switch S 1 On, switch S 12 Opening, V CM Is connected to a sampling capacitor C s Left polar plate of (1), sampling capacitor C s Is connected to C I The left pole plate of (1); switch S 4 Switch S 7 On, switch S 5 Switch S 6 Disconnected, MOS transistor M p3 MOS transistor M p14 Is connected to V b0 Thereby conducting MOS transistor M p3 Is connected to the MOS transistor M p1 Drain electrode of (1), MOS tube M p4 The gate of which is connected to VDD and thus turned off; switch S 8 Switch S 10 On, switch S 9 Switch S 11 Disconnected, MOS transistor M n3 MOS transistor M n14 Is connected to V b1 Thereby conducting MOS transistor M n3 Is connected to the MOS transistor M n1 Drain electrode of (1), MOS tube M n4 The gate of which is connected to VSS and thus turned off; switch S 2 Switch S 3 Is disconnected, thereby making the MOS tube M n5 MOS transistor M p5 Composed floating current source and input tube MOS tube M p1 MOS transistor M n1 Disconnection based on MOS transistor M p1 MOS transistor M p2 MOS transistor M p3 MOS transistor M n1 MOS transistor M n2 MOS transistor M p3 The formed inverter is used as an amplifier in an integrator, and a sampling capacitor C is used s Is driven to V CM Thereby enabling the capacitance C to be sampled s Is transferred to the integrating capacitor C I According to the principle of conservation of charge,can obtain V OUT Is equal to
3. The method for operating the dynamic access inverter-based low power consumption integrator circuit according to claim 1, wherein the operation process of the dynamic access branch is as follows: the dynamic access branch is controlled by two non-overlapping clocks and can be divided into a sampling phase and an integral phase; when the dynamic access branch works at the sampling phase, the MOS transistor M n5 MOS transistor M p5 The formed floating current source passes through the MOS transistor M p4 MOS transistor M n4 Respectively supply MOS tubes M p2 MOS transistor M n2 The grid electrode of the transistor is charged to a pre-designed DC level due to the MOS transistor M p2 And MOS transistor M n2 The drain of the transistor is disconnected, so that the floating current source only needs to supply the MOS transistor M p1 MOS transistor M n1 Providing drain-source current to bias it to subthreshold region without providing MOS transistor M p2 And MOS transistor M n2 Providing drain-source bias current and also providing the MOS transistor M with the same p2 And MOS transistor M n2 Provides a bias voltage to the grid and stores the bias voltage in a capacitor C c1 And a capacitor C c2 The above step (1); when the dynamic access branch works in an integral phase, based on the MOS transistor M p2 MOS transistor M p14 MOS transistor M n2 MOS transistor M n14 Dynamic access branch and MOS transistor M based on same p1 MOS transistor M p2 MOS transistor M p3 MOS transistor M n1 MOS tube M n2 MOS transistor M p3 The formed inverters are connected in parallel to be used as an amplifier in the integrator, and the dynamic access branch circuit provides additional dynamic current to the integrating capacitor C I Charging to accelerate the rapid build-up of integrator output voltage, thereby enabling V OUT Is reached more quickly
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| CN115421552A (en) * | 2022-08-26 | 2022-12-02 | 广东工业大学 | Dynamic bias low-power-consumption integrator based on capacitor serving as floating voltage source |
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