CN112269421B - Reference voltage generation circuit for reconfigurable SAR ADC - Google Patents
Reference voltage generation circuit for reconfigurable SAR ADC Download PDFInfo
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- CN112269421B CN112269421B CN202011085436.7A CN202011085436A CN112269421B CN 112269421 B CN112269421 B CN 112269421B CN 202011085436 A CN202011085436 A CN 202011085436A CN 112269421 B CN112269421 B CN 112269421B
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
The invention relates to the field of analog integrated circuits, and provides a reference voltage generating circuit structure for a reconfigurable SAR ADC (synthetic aperture radar), which realizes closed-loop feedback regulation, realizes that a bias current changes along with a sampling rate, saves energy consumption and is suitable for various application scenes. The invention relates to a reference voltage generating circuit for a reconfigurable SAR ADC, which comprises an idle time detection circuit, a current source consisting of fixed current and variable current, and a source follower consisting of an operational amplifier and an MOS (metal oxide semiconductor) tube, wherein the idle time detection circuit generates different output voltages VCON under the control of time sequence, and controls the current source to generate currents with different driving capacities and provide the currents to the source follower, so that reference voltages VREF with different driving capacities are generated and provided to a core circuit of a successive approximation type analog-to-digital converter to realize reconfiguration. The invention is mainly applied to the design and manufacture occasions of the analog integrated circuit.
Description
Technical Field
The present invention relates to the field of analog integrated circuits, and more particularly, to a reference voltage generating circuit structure for an analog-to-digital converter.
Background
With the development of microelectronic process technology, the feature size and the power supply voltage of a process transistor are lower and lower, a successive approximation type analog-to-digital converter (SAR ADC) has more and more advantages under a deep nanometer process due to the unique architecture characteristics of the SAR ADC, and the SAR ADC gradually expands to the application field of broadband communication and shows wider prospects by combining with high-speed technologies such as asynchronous logic technology, self-timing technology, time interleaving technology, digital redundancy and compensation technology, pipeline auxiliary technology, single-step multi-bit technology and the like. Aiming at the characteristics of wide application scene and different index requirements, the reconfigurable SAR ADC is designed to realize the maximum utilization of resources, and is the development trend of the ADC.
The main difficulty of reconfigurable ADC design is how to ensure the stability of energy efficiency under different resolution and sampling rate configurations, and how to ensure that the static power consumption reasonably changes along with the sampling rate is a research focus. The method based on the switched capacitor is a common method for connecting the bias current of the circuit with the sampling rate, but the method is only adopted, so that certain blindness is achieved, and whether the bias current of the circuit is set reasonably cannot be judged.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a reference voltage generating circuit structure for a reconfigurable SAR ADC (synthetic aperture radar), which realizes closed-loop feedback regulation, realizes the change of bias current along with the sampling rate, saves energy consumption and is suitable for various application scenes. Therefore, the invention adopts the technical scheme that the reference voltage generating circuit for the reconfigurable SAR ADC comprises an idle time detection circuit, a current source consisting of fixed current and variable current, and a source follower consisting of an operational amplifier and an MOS (metal oxide semiconductor) tube, wherein the idle time detection circuit generates different output voltages VCON under the control of time sequence, controls the current source to generate currents with different driving capacities and supplies the currents to the source follower, so that reference voltages VREF with different driving capacities are generated and supplied to a core circuit of a successive approximation type analog-to-digital converter to realize the reconfiguration.
The idle time detection circuit is composed of a current source, a switch and a capacitor, and the connection relation is as follows: one end of the current source is connected with the power supply, and the other end of the current source is connected with one end of the switch S1 and one end of the switch S2; one end of the switch S1 is connected to the output end of the current source and one end of the switch S2, the other end of the switch S1 is connected to one end of the switch S3, one end of the capacitor C1 and the other end of the switch S4, the other end of the switch S2 is connected to VSS, the other end of the switch S3 is connected to VSS, the other end of the capacitor C1 is connected to VSS, the other end of the switch S4 is connected to the output end VCON and one end of the capacitor C2, and the other end of the capacitor C2 is connected to VSS.
The current source is composed of a fixed current source and a variable current source, and comprises a PMOS tube M4, an NMOS tube M5 and a PMOS tube M1, wherein the connection relationship is as follows: the gate end of the PMOS tube M4 is connected with the output end VCON of the idle time detection circuit, the drain end is connected with VSS, the source end is connected with the drain end and the gate end of the PMOS tube M1, the gate end and the drain end of the NMOS tube M5 and the gate end of the PMOS tube M2 in the source follower circuit, the source end of the NMOS tube is connected with VSS, and the source end of the PMOS tube M1 is connected with VDD.
The source follower is composed of MOS tubes M2, M3, M6, M7 and a remote computing amplifier, and the connection relation is as follows: the source end of the PMOS tube M2 is connected with VDD, the gate end is connected with the gate end of a PMOS tube M1 and the gate end of a PMOS tube M3 in the current source circuit, the drain end is connected with the negative input end of the operational amplifier and the source end of the PMOS tube M6, the positive input end of the operational amplifier is connected with an input signal VIN +, the output end is connected with the gate end of a PMOS tube M6 and the gate end of a PMOS tube M7, the drain end is connected with VSS, the source end of the PMOS tube M3 is connected with VDD, the drain end is connected with the output end VREF and the source end of a PMOS tube M7, and the drain end of the PMOS tube M7 is connected with VDD.
The current of the current source is copied through the mirror image of the M2 tube and the M3 tube, the negative input end of the operational amplifier is connected with the source end of the M6 tube to form negative feedback, when the negative input end signal is increased in a small signal range, the voltage of the output end of the operational amplifier is reduced, and as the current of the branch where the M6 tube is located is constant, the voltage of the source end of the M6 tube is reduced, the voltage signal of the negative input end of the operational amplifier is reduced, tends to be stable, and the driving capability is enhanced; because the gate terminals of the M7 tube and the M3 tube are respectively connected to the gate terminals of the M6 tube and the M2 tube, the output voltage VREF is as stable as the voltage of the source terminal of the M6 tube, i.e., the negative input terminal of the operational amplifier.
The invention has the characteristics and beneficial effects that:
the invention relates to a reference voltage generating circuit for a reconfigurable SAR ADC (synthetic aperture radar), which comprises an idle time detection circuit, a current source consisting of a fixed current and a variable current and a source follower consisting of an operational amplifier and an MOS (metal oxide semiconductor) tube. The invention can realize the self-adaptive adjustment of power consumption along with resolution/sampling rate by matching with a self-timing technology, thereby realizing the reconfigurable SAR ADC.
Description of the drawings:
FIG. 1 is a schematic diagram of a reference voltage generation circuit for a reconfigurable SAR ADC of the present invention;
fig. 2 is a schematic diagram of an idle time detection circuit in the present invention.
Fig. 3 is a schematic diagram of an operational amplifier in the present invention.
Detailed Description
Aiming at the prior art, the invention provides a reference voltage generating circuit structure used for a reconfigurable SAR ADC, which realizes closed-loop feedback regulation, realizes that the bias current changes along with the sampling rate, saves the energy consumption and is suitable for various application scenes.
In order to solve the technical problem, the invention provides a reference voltage generating circuit for a reconfigurable SAR ADC, which comprises an idle time detection circuit, a current source composed of a fixed current and a variable current, and a source follower composed of an operational amplifier and an MOS (metal oxide semiconductor) tube. The idle time detection circuit generates different output voltages VCON under the control of a time sequence, and controls the current source to generate currents with different driving capacities and provide the currents to the source follower, so that reference voltages VREF with different driving capacities are generated and provided to the SAR ADC core circuit to realize reconfigurability. The idle time detection circuit is composed of a current source, a switch and a capacitor, and the connection relation is as follows: one end of the current source is connected with a power supply, the other end of the current source is connected with one end of a switch S1 and one end of a switch S2, one end of a switch S1 is connected with an output end of the current source and one end of a switch S2, the other end of a switch S1 is connected with one end of a switch S3, one end of a capacitor C1 and the other end of a switch S4, the other end of the switch S2 is connected with VSS, the other end of the switch S3 is connected with VSS, the other end of the capacitor C1 is connected with VSS, the other end of a switch S4 is connected with an output end VCON and one end of a capacitor C2, and the other end of the capacitor C2 is connected with VSS. The current source is composed of a fixed current source and a variable current source and comprises a PMOS tube M4, an NMOS tube M5 and a PMOS tube M1. The connection relation is as follows: the gate end of the PMOS tube M4 is connected with the output end VCON of the idle time detection circuit, the drain end is connected with VSS, the source end is connected with the drain end and the gate end of the PMOS tube M1, the gate end and the drain end of the NMOS tube M5 and the gate end of the PMOS tube M2 in the source follower circuit, the source end of the NMOS tube is connected with VSS, and the source end of the PMOS tube M1 is connected with VDD. The source follower is composed of MOS tubes M2, M3, M6, M7 and a remote computing amplifier, and the connection relation is as follows: the source end of the PMOS tube M2 is connected with VDD, the gate end is connected with the gate end of a PMOS tube M1 and the gate end of a PMOS tube M3 in the current source circuit, the drain end is connected with the negative input end of the operational amplifier and the source end of the PMOS tube M6, the positive input end of the operational amplifier is connected with an input signal VIN +, the output end is connected with the gate end of a PMOS tube M6 and the gate end of a PMOS tube M7, the drain end is connected with VSS, the source end of the PMOS tube M3 is connected with VDD, the drain end is connected with the output end VREF and the source end of the PMOS tube M7, and the drain end of the PMOS tube M7 is connected with VDD.
The invention provides a reference voltage generating circuit for a reconfigurable SAR ADC (synthetic aperture radar), which comprises an idle time detection circuit, a current source consisting of a fixed current and a variable current and a source follower consisting of an operational amplifier and an MOS (metal oxide semiconductor) tube, wherein the circuit is shown in figure 1. The idle time detection circuit generates different output voltages VCON under the control of a time sequence, and controls the current source to generate currents with different driving capacities and provide the currents to the source follower, so that reference voltages VREF with different driving capacities are generated and provided for the SAR ADC core circuit to be reconfigurable. The idle time detection circuit is composed of a current source, a switch and a capacitor, and the connection relation is as follows: one end of the current source is connected with a power supply, the other end of the current source is connected with one end of a switch S1 and one end of a switch S2, one end of a switch S1 is connected with an output end of the current source and one end of a switch S2, the other end of a switch S1 is connected with one end of a switch S3, one end of a capacitor C1 and the other end of a switch S4, the other end of the switch S2 is connected with VSS, the other end of the switch S3 is connected with VSS, the other end of the capacitor C1 is connected with VSS, the other end of a switch S4 is connected with an output end VCON and one end of a capacitor C2, and the other end of the capacitor C2 is connected with VSS. The current source is composed of a fixed current source and a variable current source and comprises a PMOS tube M4, an NMOS tube M5 and a PMOS tube M1. The connection relation is as follows: the gate end of the PMOS tube M4 is connected with the output end VCON of the idle time detection circuit, the drain end is connected with VSS, the source end is connected with the drain end and the gate end of the PMOS tube M1, the gate end and the drain end of the NMOS tube M5 and the gate end of the PMOS tube M2 in the source follower circuit, the source end of the NMOS tube is connected with VSS, and the source end of the PMOS tube M1 is connected with VDD. The source follower is composed of MOS tubes M2, M3, M6, M7 and a remote computing amplifier, and the connection relation is as follows:
the source end of the PMOS tube M2 is connected with VDD, the gate end is connected with the gate end of a PMOS tube M1 and the gate end of a PMOS tube M3 in the current source circuit, the drain end is connected with the negative input end of the operational amplifier and the source end of the PMOS tube M6, the positive input end of the operational amplifier is connected with an input signal VIN +, the output end is connected with the gate end of a PMOS tube M6 and the gate end of a PMOS tube M7, the drain end is connected with VSS, the source end of the PMOS tube M3 is connected with VDD, the drain end is connected with the output end VREF and the source end of a PMOS tube M7, and the drain end of the PMOS tube M7 is connected with VDD.
The present invention will be described in further detail with reference to specific embodiments.
Firstly, the working principle of the idle time detection circuit is introduced:
before the quantization is completed, Data _ ready is kept at a low level, a switch correspondingly controlled by the Data _ ready is turned on, and the capacitor C1 is kept in a reset state. When the quantization is completed, the Data _ ready changes from low level to high level, the switch controlled by the Data _ ready is turned on, and the capacitor C1 performs current integration. When the sampling clock CLK _ samp of the ADC arrives, CLK _ samp becomes high, the corresponding switch is turned on, and the voltage obtained by integrating C1 is sampled onto C2 and is held during the low level of CLK _ samp.
The working principle of the source follower is described next:
the current of the current source is duplicated through the mirror image of the M2 tube and the M3 tube. The negative input end of the operational amplifier is connected with the source end of the M6 tube to form negative feedback, when the negative input end signal is increased in a small signal range, the output end voltage of the operational amplifier is reduced, and because the current of the branch where the M6 tube is located is constant, the source end voltage of the M6 tube is reduced, the negative input end voltage signal of the operational amplifier is reduced, tends to be stable, and the driving capability is enhanced. Because the gate ends of the M7 tube and the M3 tube are respectively connected with the gate ends of the M6 tube and the M2 tube, the output voltage VREF is as stable as the voltage of the source end of the M6 tube, namely the negative input end of the operational amplifier, and has strong driving capability.
Finally, the operation principle that the whole system is reconfigurable is introduced:
when the quantization is completed, a Data _ ready flag signal is generated. The idle time from the moment when quantization is completed to the sampling moment is different due to different sampling rates, and ideally, the idle time is expected to be 0. The idle time detection circuit detects the idle time, and controls the variable current part of the current source part according to the detection result, wherein the current source is smaller when the idle time is longer, and the current source is larger when the idle time is shorter. The current of the current source is different, the current of the branch where the mirror image is copied to the M2 tube is different from the current of the branch where the M3 tube is located, and the driving capability of the final output voltage VREF is different. The reference voltage VREF is output to an SAR ADC core module, the self-timing technology is combined, the establishing time of modules such as a capacitor array and a comparator is adjusted, the power consumption of each module is reduced, and finally the power consumption is adjusted along with the resolution/sampling rate in a self-adaptive mode.
While the present invention has been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are intended to be illustrative rather than restrictive, and many modifications may be made by those skilled in the art without departing from the spirit of the present invention within the scope of the appended claims.
Claims (4)
1. A reference voltage generating circuit for a reconfigurable SAR ADC is characterized by comprising an idle time detection circuit, a current source composed of fixed current and variable current, and a source follower composed of an operational amplifier and an MOS (metal oxide semiconductor) tube, wherein the idle time detection circuit generates different output voltages VCON under the control of time sequence, controls the current source to generate currents with different driving capacities and supplies the currents to the source follower, so that reference voltages VREF with different driving capacities are generated and supplied to a successive approximation type analog-to-digital converter core circuit to realize reconfiguration; the idle time detection circuit is composed of a current source, a switch and a capacitor, and the connection relation is as follows: one end of the current source is connected with the power supply, and the other end of the current source is connected with one end of the switch S1 and one end of the switch S2; one end of the switch S1 is connected to the output end of the current source and one end of the switch S2, the other end of the switch S1 is connected to one end of the switch S3, one end of the capacitor C1 and one end of the switch S4, the other end of the switch S2 is connected to VSS, the other end of the switch S3 is connected to VSS, the other end of the capacitor C1 is connected to VSS, the other end of the switch S4 is connected to the output end VCON and one end of the capacitor C2, and the other end of the capacitor C2 is connected to VSS.
2. The reference voltage generating circuit for the reconfigurable SAR ADC of claim 1, wherein the current source is composed of a fixed current source and a variable current source, and comprises a PMOS transistor M4, an NMOS transistor M5 and a PMOS transistor M1, and the connection relationship is as follows: the gate end of the PMOS tube M4 is connected with the output end VCON of the idle time detection circuit, the drain end is connected with VSS, the source end is connected with the drain end and the gate end of the PMOS tube M1, the gate end and the drain end of the NMOS tube M5 and the gate end of the PMOS tube M2 in the source follower circuit, the source end of the NMOS tube M5 is connected with VSS, and the source end of the PMOS tube M1 is connected with VDD.
3. A reference voltage generating circuit for a reconfigurable SAR ADC as claimed in claim 1, wherein said source follower is formed by MOS transistors M2, M3, M6, M7 and an operational amplifier, and the connection relationship is as follows: the source end of the PMOS tube M2 is connected with VDD, the gate end is connected with the gate end of a PMOS tube M1 and the gate end of a PMOS tube M3 in the current source circuit, the drain end is connected with the negative input end of the operational amplifier and the source end of the PMOS tube M6, the positive input end of the operational amplifier is connected with an input signal VIN +, the output end is connected with the gate end of a PMOS tube M6 and the gate end of a PMOS tube M7, the drain end of the PMOS tube M6 is connected with VSS, the source end of the PMOS tube M3 is connected with VDD, the drain end is connected with the output end VREF and the source end of the PMOS tube M7, and the drain end of the PMOS tube M7 is connected with VSS.
4. The reference voltage generating circuit for the reconfigurable SAR ADC of claim 1, wherein a current of a current source is copied through a mirror image of an M2 tube and an M3 tube, a negative input end of the operational amplifier is connected with a source end of an M6 tube to form negative feedback, and when a signal of the negative input end is increased in a small signal range, the voltage of an output end of the operational amplifier is reduced, because a branch where the M6 tube is located is constant in current, and the voltage of a source end of the M6 tube is reduced, so that a voltage signal of the negative input end of the operational amplifier is reduced, tends to be stable, and the driving capability is enhanced; because the gate terminals of the M7 tube and the M3 tube are respectively connected to the gate terminals of the M6 tube and the M2 tube, the output voltage VREF is as stable as the voltage of the source terminal of the M6 tube, i.e., the negative input terminal of the operational amplifier.
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| CN103197122A (en) * | 2013-04-12 | 2013-07-10 | 矽力杰半导体技术(杭州)有限公司 | Current detection circuit and switch-type regulator provided with same |
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| JP4791505B2 (en) * | 2008-04-24 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | ΔΣ A / D converter |
| KR101044056B1 (en) * | 2009-04-10 | 2011-06-27 | 주식회사 에이디텍 | An infrared-ray receiver having a gain control unit of mode transformation type |
| CN103825614B (en) * | 2014-02-12 | 2017-04-05 | 北京时代民芯科技有限公司 | A kind of high-speed low-power-consumption analog-digital converter of wideband input |
| US20160105194A1 (en) * | 2014-10-10 | 2016-04-14 | Analog Devices Technology | Passive analog sample and hold in analog-to-digital converters |
| KR102429421B1 (en) * | 2018-02-14 | 2022-08-04 | 에스케이하이닉스 주식회사 | Buffer circuit, clock dividing circuit and semiconductor device using the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7791406B1 (en) * | 2006-04-04 | 2010-09-07 | Marvell International Ltd. | Low leakage power management |
| CN103197122A (en) * | 2013-04-12 | 2013-07-10 | 矽力杰半导体技术(杭州)有限公司 | Current detection circuit and switch-type regulator provided with same |
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