CN103235630A - Low-power-consumption reference voltage buffer applied to production line analog-to-digital converter (ADC) - Google Patents
Low-power-consumption reference voltage buffer applied to production line analog-to-digital converter (ADC) Download PDFInfo
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- CN103235630A CN103235630A CN 201310164696 CN201310164696A CN103235630A CN 103235630 A CN103235630 A CN 103235630A CN 201310164696 CN201310164696 CN 201310164696 CN 201310164696 A CN201310164696 A CN 201310164696A CN 103235630 A CN103235630 A CN 103235630A
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Abstract
The invention provides a low-power-consumption reference voltage buffer applied to a production line analog-to-digital converter (ADC). On the basis that the buffer uses a traditional source electrode voltage follower as an output buffer, a novel dynamic current control method is adopted, and a discharging current control circuit and a charging current control circuit are added, so that the buffer can drive a very large load capacitor, and required voltage accuracy can be achieved within a short period of time. A two-phase non-overlapping clock control switch array in the production line ADC controls metal oxide semiconductor (MOS) tubes accessed to the circuits, and the MOS tubes control discharging current and charging current of a buffer circuit. The low-power-consumption reference voltage buffer greatly reduces current consumed by the buffer and accordingly reduces power consumption of the circuits when drives the load capacitor.
Description
Technical field
The invention belongs to the electronic circuit technology field, especially relate to a kind of low-power consumption reference voltage impact damper that is applied to pipeline ADC.
Background technology
The reference voltage impact damper is very important in a reference voltage circuit ingredient.Because it is all very big usually to produce the circuit output resistance of reference voltage source, if directly be used for driving resistive load, can make the value of output voltage substantial deviation reference voltage, the entire gain of circuit descends, and influences the overall performance of circuit.In addition, in production line analog-digital converter ADC, for the Consideration of precision and noise, sampling capacitance has very big value usually, makes the entire circuit equivalent capacity very big.Like this; if reference voltage is directly used in the pipeline ADC; the total capacitance of equivalence and the output impedance of the reference voltage source integrating circuit time constant that obtains that multiplies each other will be very big; it will be very slow causing the foundation of electric capacity both end voltage; this has seriously limited operating rate and the precision of pipeline ADC, thereby influences the overall performance of pipeline ADC.In addition, can form by line each other between each module in the pipeline ADC and crosstalk, this will make that the output of reference voltage is no longer stable, even depart from the output valve of setting far away.The characteristics of reference voltage impact damper are exactly that output resistance is smaller, driving force is very high, reference voltage in needs, can provide very big output current, make circuit finish the foundation of large-signal and small-signal fast, so must improve driving force through impact damper.
At present, the output of reference voltage impact damper Low ESR mainly contains dual mode and realizes, a kind of is to adopt negative-feedback technology, and a kind of is exactly to adopt source follower.Adopt negative-feedback technology needing to realize the backfeed loop of careful design circuit, guarantee the stable of integrated circuit.In addition, backfeed loop also will consume certain electric current, increase the overall power of circuit.Because source follower itself just has less output impedance, and there is not a Miller effect of electric capacity, can realize bigger bandwidth under the identical power consumption, simultaneously can ensure the stability of circuit well, be exactly to adopt the source follower technology to realize impact damper so use more.
In pipeline ADC, the matching precision of choosing needs consideration noiseproof feature and electric capacity of sampling capacitance.Under this constraint aspect two, the value of sampling capacitance is often very big, so the capacitive load of impact damper is very big.This just requires the driving force of impact damper very strong, provide very big electric current under load capacitance charging, discharge scenario, but this often needs very big quiescent current to realize.The operating rate of ifs circuit is very high, electric current will be very big so, often reaches tens milliamperes, has occupied a part of power consumption very big among the ADC, so that the reference voltage impact damper of design low-power consumption just seems is particularly necessary.
Summary of the invention
Technical matters to be solved by this invention is to overcome the deficiencies in the prior art, the present invention proposes a kind of low-power consumption reference voltage impact damper that is applied to pipeline ADC.
For solving the problems of the technologies described above, the technical solution used in the present invention is as follows:
A kind of low-power consumption reference voltage impact damper that is applied to pipeline ADC, described reference voltage impact damper comprises differential voltage amplifier, source follower, capacitor discharge loop, electric capacity charge circuit;
Described differential voltage amplifier section comprises first resistance, second resistance, the 3rd resistance, the 4th resistance, differential amplifier;
Described source follower circuit partly comprises NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe;
Described capacitor discharge loop comprises first load capacitance, second switch, the 3rd NMOS pipe, discharge current control circuit; Described discharge current control circuit comprises first cmos switch, the 5th NMOS pipe;
Described electric capacity charge circuit comprises second load capacitance, the 3rd switch, the 2nd NMOS pipe, charging current control circuit; Described charging current control circuit comprises second cmos switch, PMOS pipe;
Described reference voltage impact damper also comprises first voltage source, first switch, the 4th switch, second voltage source;
Described reference voltage buffer circuits connects as follows:
First resistance, one end ground connection, the negative input end of another termination differential amplifier of first resistance, the positive output end of the 3rd resistance one termination differential amplifier, the negative input end of another termination differential amplifier of the 3rd resistance; Second resistance, one termination input voltage, the positive input terminal of another termination differential amplifier of second resistance; The positive input terminal of the 4th resistance one termination differential amplifier, another termination differential amplifier negative output terminal of the 4th resistance;
The one NMOS tube grid connects the differential amplifier negative output terminal, and the drain electrode of NMOS pipe connects power supply, and NMOS pipe source electrode connects the drain electrode of the 3rd metal-oxide-semiconductor; The 2nd NMOS tube grid connects the differential amplifier positive output end, and the drain electrode of the 2nd NMOS pipe connects power supply, and the 2nd NMOS pipe source electrode connects the drain electrode of the 4th NMOS pipe; The 3rd NMOS manages source ground; The 4th NMOS manages source ground, and the 4th NMOS tube grid links to each other with the 3rd NMOS tube grid, and the 4th NMOS tube grid links to each other with fixed bias voltage source together with the 3rd NMOS tube grid;
First switch one terminates to first voltage source, and the first switch other end links to each other with the first electric capacity top crown, second switch one end respectively; The plate earthing of the first electric capacity subordinate; Another termination of second switch the 3rd NMOS manages drain electrode; The 5th NMOS tube grid connects first cmos switch, one end, and the 5th NMOS manages source ground; Another termination of first cmos switch the 5th NMOS manages drain electrode, and the drain electrode of the 5th NMOS pipe connects the top crown of first electric capacity;
The 4th switch one termination second voltage source, the 4th switch other end links to each other with the second electric capacity top crown, the 3rd switch one end respectively; The plate earthing of the second electric capacity subordinate; Another termination of the 3rd switch the 4th NMOS manages drain electrode; The first gate pmos utmost point connects second cmos switch, one end, and PMOS pipe source electrode connects power supply; Another termination of second cmos switch the one PMOS manages drain electrode, and the drain electrode of PMOS pipe connects the top crown of second electric capacity.
The invention has the beneficial effects as follows: the present invention proposes a kind of low-power consumption reference voltage impact damper that is applied to pipeline ADC, described reference voltage impact damper adopts source follower as the body of work circuit of impact damper, utilizes the not overlapping clock of two-phase in the pipeline ADC to design extra charging and discharge loop for the load capacitance of impact damper.Do not carry out at electric capacity that the switch in this circuit all disconnects under the charge status, can not increase extra power consumption to circuit.Under identical load capacitance situation, when the voltage at the electric capacity two ends is established to identical precision, can dwindle time and the consumed current of foundation greatly, reduce the power consumption of circuit.
Description of drawings
Fig. 1 is the low-power consumption reference voltage impact damper based on pipeline ADC of the present invention.
Fig. 2 is the discharge current control circuit synoptic diagram of reference voltage impact damper of the present invention.
Fig. 3 is the charging current control circuit synoptic diagram of reference voltage impact damper of the present invention.
Fig. 4 follows impact damper under identical load electric capacity situation for impact damper of the present invention and original basic source electrode, differential voltage and time relation curve that the electric capacity two ends are set up.Wherein, solid line is the voltage among the present invention, and dotted line is the voltage of original source follower circuit.
Embodiment
Below in conjunction with accompanying drawing, a kind of low-power consumption reference voltage impact damper that is applied to pipeline ADC that the present invention is proposed is elaborated:
Low-power consumption reference voltage impact damper based on pipeline ADC of the present invention is realized by utilizing the non-overlapping clock design on-off circuit of two-phase in the pipeline ADC.Can be seen that by Fig. 1 the non-overlapping clock of the two-phase in the circuit is respectively CLK1, CLK2.Do not consider the circuit that the present invention designs, the circuit on an analysis chart 1 top.As can be seen, when CLK1 is high, CLK2 when low (this time period note is T1), switch SW 1, SW4 closure, SW2, SW3 disconnect, capacitor C 1 charging of voltage source V H, capacitor C 2 chargings of voltage source V L.Simultaneously, NMOS pipe NM1, NM2 constitute basic source follower, and NMOS pipe NM3, NM4 are as the active load of source follower.In period, voltage source V H is charged to VH with capacitor C 1 both end voltage at this section, and voltage source V L is charged to VL with capacitor C 2 both end voltage.Simultaneously, the voltage of differential voltage amplifier OP end is set up voltage VH through NMOS pipe NM2 at the NM2 source electrode, and the ON terminal voltage is set up voltage VL through NMOS pipe NM1 at the NM1 source electrode.When CLK1 is low, when CLK2 is high (this time period note is T2), switch SW 1, SW4 disconnect, SW2, SW3 closure, voltage VH on the capacitor C 1 need discharge into low-voltage VL through NMOS pipe NM3, voltage on the capacitor C 2 is VL, needs power supply through NMOS pipe NM2 it to be charged, and makes that voltage rises to VH from VL on the capacitor C 2.Capacitor C 1, C2 are more big, and the time of charging and discharge is more long, and the electric current that voltage is established to certain precision needs is also more big.This makes that the size of NMOS pipe NM3, NM2 is very big, and the size of corresponding NM1, NM4 also must increase, so that the steady current under the static state to be provided.
The circuit that proposes among the present invention such as Fig. 2, shown in Figure 3 are respectively discharge current synoptic diagram, charging current synoptic diagram.Now be analyzed as follows according to the sign among the figure: at T1 in the time, switch TG1 and TG2 disconnect, at this moment circuit and original circuit do not have any difference, the voltage of differential voltage amplifier OP end is through NMOS pipe NM2, set up voltage VH at the NM2 source electrode, the ON terminal voltage is set up voltage VL through NMOS pipe NM1 at the NM1 source electrode, and the voltage at capacitor C 1, C2 two ends also is established to VH, VL respectively by switch SW 1, SW4.When at T2 in the time period, switch TG1, TG2 closure, at this moment NMOS pipe NM5 constitutes the diode connecting circuit, and PMOS pipe PM1 also constitutes the diode connecting circuit.At this moment, capacitor C 1 not only can be managed NM3 by NMOS and be discharged over the ground, can manage the NM5 discharge by NMOS; Meanwhile, power supply not only can be managed capacitor C 2 chargings of NM2 by NMOS, can also manage capacitor C 2 chargings of PM1 by PMOS.Find out that thus duration of charging and discharge time can shorten greatly.
Fig. 4 follows impact damper under identical load electric capacity (C1=C2=20pF) situation for impact damper of the present invention and original basic source electrode, differential voltage and time relation curve (VH-VL=1V) that the electric capacity two ends are set up.Solid line is the voltage among the present invention, and dotted line is the voltage of original source follower circuit.As seen from Figure 4, under identical power consumption, the circuit structure that the present invention proposes makes voltage set up speed and follows impact damper much larger than basic source electrode, also can drive bigger capacitive load.
The circuit that the present invention proposes mainly comprises differential voltage amplifier, the source follower as output buffer, capacitor discharge loop, electric capacity charge circuit;
Differential voltage amplifier section comprises first resistance R 1, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, differential amplifier A1;
Source follower circuit comprises that partly a NMOS pipe NM1, the 2nd NMOS manage NM2, and the 3rd NMOS pipe NM3, the 4th NMOS manage NM4;
The capacitor discharge loop comprises the first load capacitance C1, second switch SW2, the 3rd NMOS pipe NM3, discharge current control circuit.Discharge current control circuit is a series of arrays that connect according to " discharge current control circuit synoptic diagram ".Comprise the first cmos switch TG1 in the synoptic diagram, the 5th NMOS manages NM5;
The electric capacity charge circuit comprises the second load capacitance C2, the 3rd switch SW 3, the 2nd NMOS pipe NM2, charging current control circuit.Charging current control circuit is a series of arrays that connect according to " discharge current control circuit synoptic diagram ".Comprise the second cmos switch TG2 in the synoptic diagram, a PMOS manages PM1;
Remainder comprises voltage source V H, first switch SW 1, the 4th switch SW 4, voltage source V L for the setting that fictitious load electric capacity charges and discharge needs in the circuit;
Circuit connecting relation is as follows:
First resistance R, 1 one end ground connection, the negative input end of a termination amplifier A1, the positive output end of the 3rd resistance R 3 one termination amplifier A1, the negative input end of a termination amplifier A1; Second resistance R, 2 one termination input voltage vin, the positive input terminal of a termination amplifier A1, the positive input terminal of the 4th resistance R 4 one termination amplifier A1, a termination amplifier A1 negative output terminal;
The one NMOS pipe NM1 grid connects amplifier A1 negative output terminal, and drain electrode connects power supply, and source electrode connects the 3rd metal-oxide-semiconductor NM3 drain electrode; The 2nd NMOS pipe NM2 grid connects amplifier A1 positive output end, and drain electrode connects power supply, and source electrode connects the 4th NMOS pipe NM4 drain electrode; The 3rd NMOS pipe NM3 source ground; The 4th NMOS pipe NM4 source ground, grid links to each other with the 3rd NMOS pipe NM3, receives fixed bias voltage Vbn;
The 4th switch SW 4 one terminates to voltage source V L, and the other end is received second capacitor C, 2 top crowns, the plate earthing of the 3rd switch SW 3, the second capacitor C 2 subordinates, the 3rd switch SW 3 another terminations the 4th NMOS pipe NM4 drain electrode; The one PMOS pipe PM1 grid connects the second cmos switch TG2, one end, and source electrode connects power supply; Another termination of the second cmos switch TG2 the one PMOS pipe PM1 drain electrode, PMOS pipe PM1 drain electrode connects the top crown of second capacitor C 2.
In the design process of circuit, to reasonably select the dimension scale of NMOS pipe NM2 and PMOS pipe PM1, in like manner, also need carefully to choose the dimension scale of NMOS pipe NM3 and NM5, guarantee the charging voltage speed approximately equal that A is ordered in the circuit voltage discharge rate and B are ordered, like this could the whole Time Created that shortens voltage.So can manage NM2 and NMOS pipe NM3 design trimming circuit to NMOS, guarantee that the Time Created of voltage is adjustable.
Claims (1)
1. a low-power consumption reference voltage impact damper that is applied to pipeline ADC is characterized in that described reference voltage impact damper comprises differential voltage amplifier, source follower, capacitor discharge loop, electric capacity charge circuit;
Described differential voltage amplifier section comprises first resistance, second resistance, the 3rd resistance, the 4th resistance, differential amplifier;
Described source follower circuit partly comprises NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe;
Described capacitor discharge loop comprises first load capacitance, second switch, the 3rd NMOS pipe, discharge current control circuit; Described discharge current control circuit comprises first cmos switch, the 5th NMOS pipe;
Described electric capacity charge circuit comprises second load capacitance, the 3rd switch, the 2nd NMOS pipe, charging current control circuit; Described charging current control circuit comprises second cmos switch, PMOS pipe;
Described reference voltage impact damper also comprises first voltage source (VH), first switch, the 4th switch, second voltage source (VL);
Described reference voltage buffer circuits connects as follows:
First resistance, one end ground connection, the negative input end of another termination differential amplifier of first resistance, the positive output end of the 3rd resistance one termination differential amplifier, the negative input end of another termination differential amplifier of the 3rd resistance; Second resistance, one termination input voltage (Vin), the positive input terminal of another termination differential amplifier of second resistance; The positive input terminal of the 4th resistance one termination differential amplifier, another termination differential amplifier negative output terminal of the 4th resistance;
The one NMOS tube grid connects the differential amplifier negative output terminal, and the drain electrode of NMOS pipe connects power supply, and NMOS pipe source electrode connects the drain electrode of the 3rd metal-oxide-semiconductor; The 2nd NMOS tube grid connects the differential amplifier positive output end, and the drain electrode of the 2nd NMOS pipe connects power supply, and the 2nd NMOS pipe source electrode connects the drain electrode of the 4th NMOS pipe; The 3rd NMOS manages source ground; The 4th NMOS manages source ground, and the 4th NMOS tube grid links to each other with the 3rd NMOS tube grid, and the 4th NMOS tube grid links to each other with fixed bias voltage source (Vbn) together with the 3rd NMOS tube grid;
First switch one terminates to first voltage source (VH), and the first switch other end links to each other with the first electric capacity top crown, second switch one end respectively; The plate earthing of the first electric capacity subordinate; Another termination of second switch the 3rd NMOS manages drain electrode; The 5th NMOS tube grid connects first cmos switch, one end, and the 5th NMOS manages source ground; The first cmos switch other end is connected with the top crown of the drain electrode of the 5th NMOS pipe, first electric capacity respectively;
The 4th switch one termination, second voltage source (VL), the 4th switch other end link to each other with the second electric capacity top crown, the 3rd switch one end respectively; The plate earthing of the second electric capacity subordinate; Another termination of the 3rd switch the 4th NMOS manages drain electrode; The first gate pmos utmost point connects second cmos switch, one end, and PMOS pipe source electrode connects power supply; The second cmos switch other end is connected with the top crown of the drain electrode of PMOS pipe, second electric capacity respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201310164696 CN103235630A (en) | 2013-05-08 | 2013-05-08 | Low-power-consumption reference voltage buffer applied to production line analog-to-digital converter (ADC) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201310164696 CN103235630A (en) | 2013-05-08 | 2013-05-08 | Low-power-consumption reference voltage buffer applied to production line analog-to-digital converter (ADC) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105162468A (en) * | 2015-09-21 | 2015-12-16 | 东南大学 | High-speed reference buffer circuit with voltage bootstrap |
| CN117351867A (en) * | 2023-12-05 | 2024-01-05 | 上海视涯技术有限公司 | Buffer, voltage stabilizer, silicon-based display panel and display device |
-
2013
- 2013-05-08 CN CN 201310164696 patent/CN103235630A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105162468A (en) * | 2015-09-21 | 2015-12-16 | 东南大学 | High-speed reference buffer circuit with voltage bootstrap |
| CN105162468B (en) * | 2015-09-21 | 2018-04-24 | 东南大学 | A kind of high speed benchmark buffer circuit with voltage bootstrapping |
| CN117351867A (en) * | 2023-12-05 | 2024-01-05 | 上海视涯技术有限公司 | Buffer, voltage stabilizer, silicon-based display panel and display device |
| CN117351867B (en) * | 2023-12-05 | 2024-02-06 | 上海视涯技术有限公司 | Buffer, voltage stabilizer, silicon-based display panel and display device |
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Application publication date: 20130807 |