CN103279162B - Low-power-consumption reference voltage buffer based on assembly line ADC - Google Patents
Low-power-consumption reference voltage buffer based on assembly line ADC Download PDFInfo
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Abstract
The invention relates to a reference voltage buffer in order to overcome the defects that a buffer in the prior art is low in charging and discharging speed and high in power consumption. Due to the fact that a discharging current control circuit and a charging current control circuit are added, if a load capacitor is in the discharging clock phase, a CMOS switch array in the discharging current control circuit is closed, capacitance discharging on the load capacitor is accelerated, and the voltage of the capacitor drops fast; if the load capacitor is in the charging clock phase, a CMOS switch array in the charging current control circuit is closed, and an extra charging circuit is provided for the capacitor. The buffer can drive a load capacitor with ultra-high capacity and can establish required voltage accuracy in a very short time.
Description
Technical field
The present invention relates to reference voltage buffer, especially based on the Low-power-consumptioreference reference voltage buffer of pipeline ADC.
Background technology
Reference voltage buffer is an ingredient very important in reference voltage circuit.Because the circuit output resistance producing reference voltage source is usually all very large, if be directly used for driving resistive load, can make the value of output voltage substantial deviation reference voltage, the entire gain of circuit declines, and affects the overall performance of circuit.In addition, in pipeline ADC, for the Consideration of precision and noise, sampling capacitance has very large value usually, makes whole circuit equivalent electric capacity very large.Like this; if reference voltage is directly used in pipeline ADC; the total capacitance time constant obtained that is multiplied with the output impedance of reference voltage source of equivalence will be very large; cause the foundation of electric capacity both end voltage will slowly; this severely limits operating rate and the precision of pipeline ADC, thus affect the overall performance of pipeline ADC.In addition, can form " crosstalk " by line each other between the modules in pipeline ADC, this, by making the output of reference voltage no longer stable, departs from the output valve of setting even far away.The feature of reference voltage buffer is exactly that output resistance is smaller, driving force is very high, very large output current can be provided when needs, make circuit complete the foundation of large-signal and small-signal fast, so reference voltage has to pass through impact damper improve driving force.
At present, the output of reference voltage buffer Low ESR mainly contains two kinds of modes and realizes, and one adopts negative-feedback technology, and one is exactly adopt source follower.Adopt negative-feedback technology to realize needing the backfeed loop of careful design circuit, guarantee the stable of integrated circuit.In addition, backfeed loop also will consume certain electric current, increases the overall power of circuit.Because source follower inherently has less output impedance, and there is not the Miller effect of electric capacity, larger bandwidth can be realized under identical power consumption, the stability of circuit can be ensured simultaneously well, so apply the more source follower of employing exactly technology to realize impact damper.
In pipeline ADC, the choosing of sampling capacitance needs the matching precision considering noiseproof feature and electric capacity.Under the constraint of these two aspects, the value of sampling capacitance is often very large, so the capacitive load of impact damper is very large.This just requires that the driving force of impact damper is very strong, provide very large electric current, but this often needs very large quiescent current to realize under load capacitance charging, discharge scenario.If the operating rate of circuit is very high, so electric current is larger, often reaches tens milliamperes, occupies a part of power consumption very large in ADC, so the reference voltage buffer of design low-power consumption just seems particularly necessary.
The output of impact damper adopts traditional source follower, but can drive very large load capacitance.Circuit devises extra charge-discharge circuit in load capacitance charging and discharging circuit, makes electric capacity both end voltage can be established to the voltage accuracy of requirement in the short period of time, and the quiescent current of circuit is very little simultaneously, makes the overall power of circuit very little.
Summary of the invention
Goal of the invention: the invention discloses a kind of reference voltage buffer being applied to pipeline ADC, this impact damper can set up the signal at load capacitance two ends more rapidly.
Technical scheme: a kind of Low-power-consumptioreference reference voltage buffer based on pipeline ADC of the present invention, comprise differential voltage amplifier, source follower as output buffer, capacitor discharge loop and capacitor charging loop, and voltage source V H, VL, the first interrupteur SW 1, the 4th interrupteur SW 4;
Described differential voltage amplifier comprises the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4 and differential amplifier A1; Described first resistance R1 one end ground connection, the negative input end of a termination differential amplifier A1; Second resistance R2 mono-termination input voltage vin, the positive input terminal of another termination differential amplifier A1; The positive output end of the 3rd resistance R3 mono-termination differential amplifier A1, the negative input end of a termination differential amplifier A1; The positive input terminal of the 4th resistance R4 mono-termination differential amplifier A1, a termination differential amplifier A1 negative output terminal;
Source follower circuit part comprises the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4; Described first NMOS tube NM1 grid connects differential amplifier A1 negative output terminal, and drain electrode connects power supply, and source electrode connects the 3rd NMOS tube NM3 drain electrode; Second NMOS tube NM2 grid connects differential amplifier A1 positive output end, and drain electrode connects power supply, and source electrode connects the 4th NMOS tube (NM4) drain electrode; 3rd NMOS tube (NM3) source ground; 4th NMOS tube NM4 source ground, grid is connected with the grid of the 3rd NMOS tube NM3, receives fixed bias voltage;
Capacitor discharge loop comprises the first load capacitance C1, second switch SW2, the 3rd NMOS tube NM3 and discharge current control circuit, and described discharge current control circuit comprises the first cmos switch TG1 and the 5th NMOS tube NM5; Described first interrupteur SW 1 one end receives voltage source V H, and the other end receives the first load capacitance C1 top crown, second switch SW2, the first load capacitance C1 bottom crown ground connection, and another termination of second switch SW2 the 3rd NMOS tube NM3 drains; 5th NMOS tube NM5 grid connects first cmos switch TG1 one end, source ground; First another termination of cmos switch TG1 the 5th NMOS tube NM5 drains, and the 5th NMOS tube NM5 drain electrode connects the top crown of the first load capacitance C1;
Capacitor charging loop comprises the second load capacitance C2, the 3rd interrupteur SW 3, second NMOS tube NM2 and charging current control circuit, and described charging current control circuit comprises the second cmos switch TG2, the first PMOS PM1; Described 4th interrupteur SW 4 one end receives voltage source V L, and the other end receives the second load capacitance C2 top crown, the 3rd interrupteur SW 3, second load capacitance C2 bottom crown ground connection, and the 3rd another termination of interrupteur SW 3 the 4th NMOS tube NM4 drains; First PMOS PM1 grid connects second cmos switch TG2 one end, and source electrode connects power supply; Another termination first of second cmos switch TG2 PMOS PM1 drains, and the first PMOS PM1 drain electrode connects the top crown of the second load capacitance C2.
Principle of work: realize above-mentioned purpose by designing extra switch charging and discharging circuit, namely when capacitor charging, electric discharge, its original charging and discharging circuit basis provides extra charging, discharge channel; When between electric capacity and impact damper, switch disconnects, the charging additionally provided, discharge loop are closed.
Beneficial effect: reference buffer of the present invention adopts basic source follower as the body of work circuit of impact damper, utilizes the two-phase load capacitance that overlapping clocks is not impact damper in pipeline ADC to devise extra charging and discharging loop.Switch under electric capacity does not carry out charge status in this circuit all disconnects, and can not increase extra power consumption to circuit.In identical load capacitance situation, when the Voltage Establishment at electric capacity two ends is to identical precision, greatly can reduce the time of foundation.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention;
Fig. 2 is discharge current control circuit schematic diagram of the present invention;
Fig. 3 is charging current control circuit schematic diagram of the present invention;
Fig. 4 be the present invention and prior art under equal conditions, the relation curve of differential voltage and time, wherein solid line is the time dependent curve of voltage in the present invention, and dotted line is the time dependent curve of voltage of original source follower circuit.
Embodiment
Below in conjunction with accompanying drawing 1 to Fig. 4, the invention will be further described.
The main circuit that the present invention proposes will comprise differential voltage amplifier, the source follower as output buffer, capacitor discharge loop, capacitor charging loop, wherein:
Differential voltage amplifier part comprises the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, differential amplifier A1;
Source follower circuit part comprises the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the 4th NMOS tube NM4;
Capacitor discharge loop comprises the first load capacitance C1, second switch SW2, the 3rd NMOS tube NM3, discharge current control circuit.Discharge current control circuit comprises the first cmos switch TG1, the 5th NMOS tube NM5;
Capacitor charging loop comprises the second load capacitance C2, the 3rd interrupteur SW 3, second NMOS tube NM2, charging current control circuit.Charging current control circuit comprises the second cmos switch TG2, the first PMOS PM1;
In circuit, remainder is the setting that fictitious load capacitor charging and electric discharge need, and comprises voltage source V H, the first interrupteur SW 1, the 4th interrupteur SW 4, voltage source V L;
Circuit connecting relation is as follows:
First resistance R1 one end ground connection, the negative input end of a termination amplifier A1, the positive output end of the 3rd resistance R3 mono-termination differential amplifier A1, the negative input end of a termination differential amplifier A1; Second resistance R2 mono-termination input voltage vin, the positive input terminal of a termination differential amplifier A1, the positive input terminal of the 4th resistance R4 mono-termination differential amplifier A1, a termination differential amplifier A1 negative output terminal;
First NMOS tube NM1 grid connects differential amplifier A1 negative output terminal, and drain electrode connects power supply, and source electrode meets the 3rd metal-oxide-semiconductor NM3 and drains; Second NMOS tube NM2 grid connects differential amplifier A1 positive output end, and drain electrode connects power supply, and source electrode connects the 4th NMOS tube NM4 drain electrode; 3rd NMOS tube NM3 source ground; 4th NMOS tube NM4 source ground, grid is connected with the 3rd NMOS tube NM3, receives fixed bias voltage Vbn;
First interrupteur SW 1 one end receives voltage source V H, and the other end receives the first load capacitance C1 top crown, second switch SW2, the first load capacitance C1 bottom crown ground connection, and another termination of second switch SW2 the 3rd NMOS tube NM3 drains; 5th NMOS tube NM5 grid connects first cmos switch TG1 one end, source ground; First another termination of cmos switch TG1 the 5th NMOS tube NM5 drains, and the 5th NMOS tube NM5 drain electrode connects the top crown of the first load capacitance C1;
4th interrupteur SW 4 one end receives voltage source V L, and the other end receives the second load capacitance C2 top crown, the 3rd interrupteur SW 3, second load capacitance C2 bottom crown ground connection, and the 3rd another termination of interrupteur SW 3 the 4th NMOS tube NM4 drains; First PMOS PM1 grid connects second cmos switch TG2 one end, and source electrode connects power supply; Another termination first of second cmos switch TG2 PMOS PM1 drains, and the first PMOS PM1 drain electrode connects the top crown of the second load capacitance C2.
Low-power-consumptioreference reference voltage buffer based on pipeline ADC of the present invention realizes by utilizing the two-phase non-overlapping Clock Design on-off circuit in pipeline ADC.Can be seen by Fig. 1, the two-phase non-overlapping clock in circuit is respectively CLK1, CLK2.Can find out:
When CLK1 is for when high, CLK2 are low (this time period is denoted as T1), interrupteur SW 1, SW4 are closed, and SW2, SW3 disconnect, and voltage source V H charges to the first load capacitance C1, and voltage source V L charges to the second load capacitance C2.Meanwhile, the first NMOS tube NM1, the second NMOS tube NM2 form basic source follower, and the 3rd NMOS tube NM3, the 4th NMOS tube NM4 are as the active load of source follower.Within this period of time, the both end voltage of the first load capacitance C1 is charged to VH by voltage source V H, and the both end voltage of the second load capacitance C2 is charged to VL by voltage source V L.Meanwhile, the voltage that differential voltage amplifier OP holds is through the second NMOS tube NM2, and set up voltage VH at the source electrode of the second NMOS tube NM2, ON terminal voltage, through the first NMOS tube NM1, sets up voltage VL at the first NMOS tube NM1 source electrode.
When CLK1 is low, when CLK2 is high (this time period is denoted as T2), interrupteur SW 1, SW4 disconnect, SW2, SW3 are closed, voltage VH on first load capacitance C1 needs to discharge into low-voltage VL through the 3rd NMOS tube NM3, voltage on second load capacitance C2 is VL, needs power supply to charge to it through the second NMOS tube NM2, makes voltage on the second load capacitance C2 rise to VH from VL.First load capacitance C1, the second load capacitance C2 are larger, and the time of charging and discharging is longer, and the electric current that Voltage Establishment needs to certain precision is also larger.This makes the size of the 3rd NMOS tube NM3, the second NMOS tube NM2 very large, and the size of corresponding first NMOS tube NM1, the 4th NMOS tube NM4 also must increase, to provide the steady current under static state.In the pipeline ADC of higher sample rate, need to guarantee that the signal on sampling capacitance is established to VH from Vin, is established to VL from Vin respectively within half sampling period.Because the sampling capacitance in pipeline ADC is comparatively large, cause the load capacitance of reference voltage buffer very large.If need shorter Time Created and higher set up precision, just need the electric current that impact damper provides very large, this makes the quiescent bias current of impact damper very large, and the power consumption of impact damper will be very large.
As shown in Figures 2 and 3, discharge current schematic diagram, charging current schematic diagram is respectively.Be analyzed as follows:
Within the T1 time, switch TG1 and TG2 disconnects, the voltage that differential voltage amplifier OP holds is through the second NMOS tube NM2, voltage VH is set up at the second NMOS tube NM2 source electrode, ON terminal voltage is through the first NMOS tube NM1, set up voltage VL at NM1 source electrode, the voltage at the first load capacitance C1, the second load capacitance C2 two ends is also established to voltage VH, VL respectively by the first interrupteur SW 1, the 4th interrupteur SW 4.
Within the T2 time period, switch TG1, TG2 are closed, and at this moment the 5th NMOS tube NM5 forms diode connecting circuit, and the first PMOS PM1 also forms diode connecting circuit.Now, the first load capacitance C1 not only can be discharged by the 3rd NMOS tube NM3 over the ground, by the 5th NMOS tube NM5 electric discharge; Meanwhile, power supply not only can be charged to the second load capacitance C2 by the second NMOS tube NM2, can also be charged by the first PMOS PM1 to the second electric capacity C2.
Find out thus, duration of charging and discharge time can shorten greatly.Under DC operation condition, the switch element in charging circuit and discharge circuit all disconnects, and the quiescent current of impact damper is managed by the first NMOS tube NM1, the breadth length ratio of the second NMOS tube NM2 and the voltage difference between its grid and source electrode determine.When circuit working is in transient state, when clock signal is low level, similar with DC operation condition, the switch element in charging circuit and discharge circuit is also disconnect.Switch when clock signal is high level in charging circuit and discharge circuit closes, the speed of accelerated charging and electric discharge.This shows, positive Slew Rate and the negative Slew Rate of impact damper output terminal when transient state all improve, thus greatly shorten the Time Created of signal.Because circuit only works when transient state, so electric current when can not increase static state, namely the power consumption of the static state of circuit can not increase.
Fig. 4 is that impact damper of the present invention and original basic source electrode follow impact damper in identical load electric capacity (C1=C2=20pF) situation, the differential voltage that electric capacity two ends are set up and the relation curve of time (VH-VL=1V).Solid line is the voltage in the present invention, and dotted line is the voltage of available circuit.Can find out, under identical power consumption, the circuit structure that the present invention proposes makes Voltage Establishment speed much larger than prior art, also can drive larger capacitive load.Compared with the basic source-follower buffer circuit under identical load electric capacity, under electric capacity two end signal is established to same precision, greatly can reduce electric current and the power consumption of the consumption of circuit.
In addition, in the design process of circuit, those skilled in the art reasonably can select the dimension scale of the second NMOS tube NM2 and the first PMOS PM1; In like manner, also can choose the dimension scale of the 3rd NMOS tube NM3 and the 5th NMOS tube NM5, guarantee the tension discharge speed of A point in circuit and the charging voltage speed approximately equal of B point, like this could the overall Time Created shortening voltage.Trimming circuit can be designed to the second NMOS tube NM2 and the 3rd NMOS tube NM3, guarantee that the Time Created of voltage is adjustable.
Claims (1)
1. the Low-power-consumptioreference reference voltage buffer based on pipeline ADC, it is characterized in that, comprise differential voltage amplifier, source follower as output buffer, capacitor discharge loop and capacitor charging loop, and voltage source V H, VL, the first switch (SW1), the 4th switch (SW4);
Described differential voltage amplifier comprises the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) and differential amplifier (A1); Described first resistance (R1) one end ground connection, the negative input end of a termination differential amplifier (A1); Second resistance (R2) one termination input voltage (Vin), the positive input terminal of another termination differential amplifier (A1); The positive output end of the 3rd resistance (R3) one termination differential amplifier (A1), the negative input end of a termination differential amplifier (A1); The positive input terminal of the 4th resistance (R4) one termination differential amplifier (A1), termination differential amplifier (A1) negative output terminal;
Source follower circuit part comprises the first NMOS tube (NM1), the second NMOS tube (NM2), the 3rd NMOS tube (NM3) and the 4th NMOS tube (NM4); Described first NMOS tube (NM1) grid connects differential amplifier (A1) negative output terminal, and drain electrode connects power supply, and source electrode connects the 3rd NMOS tube (NM3) drain electrode; Second NMOS tube (NM2) grid connects differential amplifier (A1) positive output end, and drain electrode connects power supply, and source electrode connects the 4th NMOS tube (NM4) drain electrode; 3rd NMOS tube (NM3) source ground; 4th NMOS tube (NM4) source ground, grid is connected with the grid of the 3rd NMOS tube (NM3), receives fixed bias voltage;
Capacitor discharge loop comprises the first load capacitance (C1), second switch (SW2), the 3rd NMOS tube (NM3) and discharge current control circuit, and described discharge current control circuit comprises the first cmos switch (TG1) and the 5th NMOS tube (NM5); Described first switch (SW1) end receives voltage source V H, the other end receives the first load capacitance (C1) top crown, second switch (SW2), first load capacitance (C1) bottom crown ground connection, second switch (SW2) another termination the 3rd NMOS tube (NM3) drains; 5th NMOS tube (NM5) grid connects the first cmos switch (TG1) one end, source ground; First cmos switch (TG1) another termination the 5th NMOS tube (NM5) drains, and the 5th NMOS tube (NM5) drain electrode connects the top crown of the first load capacitance (C1);
Capacitor charging loop comprises the second load capacitance (C2), the 3rd switch (SW3), the second NMOS tube (NM2) and charging current control circuit, and described charging current control circuit comprises the second cmos switch (TG2), the first PMOS (PM1); Described 4th switch (SW4) end receives voltage source V L, the other end receives the second load capacitance (C2) top crown, the 3rd switch (SW3), second load capacitance (C2) bottom crown ground connection, the 3rd switch (SW3) another termination the 4th NMOS tube (NM4) drain electrode; First PMOS (PM1) grid connects the second cmos switch (TG2) one end, and source electrode connects power supply; Another termination first PMOS (PM1) of second cmos switch (TG2) drains, and the first PMOS (PM1) drain electrode connects the top crown of the second load capacitance (C2).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103901934B (en) * | 2014-02-27 | 2016-01-06 | 开曼群岛威睿电通股份有限公司 | Reference voltage generating device |
| CN105049041B (en) * | 2015-08-28 | 2018-12-25 | 西安启微迭仪半导体科技有限公司 | Low-power consumption piece internal reference Voltag driving circuit applied to high-speed AD converter |
| CN105162468B (en) * | 2015-09-21 | 2018-04-24 | 东南大学 | A kind of high speed benchmark buffer circuit with voltage bootstrapping |
| CN111817719B (en) * | 2020-09-08 | 2020-12-11 | 杭州城芯科技有限公司 | Reference level buffer suitable for pipelined ADC and pipelined ADC |
| CN113485500B (en) * | 2021-05-24 | 2022-11-11 | 中国电子科技集团公司第四十一研究所 | Active grounding circuit and method based on negative feedback loop control |
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