JPH0537307A - Voltage controlled oscillating circuit and phase lock loop circuit - Google Patents

Abstract

PURPOSE:To offer the voltage controlled oscillator which can obtain a sufficiently high oscillation frequency, even in a circuit in which a power supply voltage is reduced for the purpose of reducing power consumption, etc. CONSTITUTION:At the time of connecting an inversion amplifier 1 of an odd number stage constituted of two pieces of transistors to the next stage, a variable resistor 2 which can control a resistance value from the outside is inserted. An oscillation frequency depends on a time constant given by the product of the resistance value of the variable resistor 2 and the input capacity of the inversion amplifier of the next stage. In such a way, even if a power supply voltage is reduced, a sufficiently high frequency oscillation is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and is particularly suitable for an integrated circuit having a low power supply voltage.

[0002]

2. Description of the Related Art Conventionally, a voltage controlled oscillator circuit is disclosed in Japanese Examined Patent Publication No. 60-25.
It was realized by the circuit disclosed in Japanese Patent Application No. 922 (Japanese Patent Application No. 52-40282, Japanese Patent Application Laid-Open No. 52-123851). FIG. 2 shows a typical use example of the conventional circuit. Transistors MP1 to M
P5 and MN1 to MN5 are five-stage inverting amplifier 1 of the oscillator
Constituting the transistor, transistors MP6 to MP10
And MN6 to MN10 are transistors forming a constant current source that limits the current supplied to the inverting amplifier 1.
The oscillation frequency is the transistor MP6 that constitutes the constant current source.
To MP10 and MN6 to MN10 are controlled by increasing / decreasing the current value supplied from the power source with the voltage applied to each gate.

[0003]

It has been found that the above-mentioned conventional circuit has the following problems when it is applied to a circuit in which the power supply voltage is lowered to reduce power consumption and the like.

Transistors MP1 to MP5 and MN1 to M forming the inverting amplifier 1 of five stages of the oscillator shown in FIG.
The substrate bias voltages of Vbsp and Vbsn are applied to N5, respectively. Therefore, the absolute values | Vthp | and | Vthn | of the threshold voltage are increased.
The increase in the threshold voltage increases the propagation delay time of the five-stage inverting amplifier 1 and reduces the oscillation frequency. When the power supply voltage is lowered to reduce power consumption, etc., the oscillation frequency is significantly lowered, and the substrate bias voltage fluctuates in response to fluctuations in the power supply voltage, which causes a problem of large frequency fluctuations. I understood it.

[0005]

As shown in FIG. 1, when an inverting amplifier 1 composed of two transistors is connected to the next stage in order to control the oscillation frequency, instead of controlling the supplied current. This is solved by inserting a variable resistor 2 whose resistance value can be controlled from the outside.

[0006]

The operation of the circuit of FIG. 1 is as follows. When the inverting amplifier 1 including the two transistors drives the next stage, the response of the output is mainly determined by the input capacitance of the next stage and the resistance in series with it. This resistance is composed of the output resistance of the inverting amplifier itself and the variable resistor 2 provided between the stages. Therefore, by controlling the resistance value of the variable resistor 2 by the voltage applied to the control terminal 3, the signal propagation time to the next stage can be controlled. Therefore, the present oscillating circuit in which the odd-numbered inverting amplifiers 1 are connected in a ring shape operates as a voltage-controlled oscillating circuit.

In the inverting amplifier 1 composed of the two transistors, the source electrodes of both PchMOS and NchMOS are connected to the power supply terminals VDD and VSS, so that the substrate bias voltage is not applied. Therefore, the fluctuation of the threshold voltage is suppressed, and the remarkable decrease of the oscillation frequency is suppressed. Also,
The substrate bias does not change even when the power supply voltage changes, and the operating margin does not decrease.

[0008]

FIG. 3 shows an embodiment of the present invention. In this example, a CMOS transistor is used as a resistor whose value can be controlled by voltage. By inputting the control voltages VCu and VCd complementarily, the resistance value is changed and the oscillation frequency is controlled.

Another embodiment of the present invention is shown in FIG. This is an example in which the resistance whose value can be controlled by the voltage is composed of only NMOS. The resistance value is changed by the control voltage VC to control the oscillation frequency. The circuit size of the control circuit can be reduced because it can be configured with 3/4 the number of elements of the conventional circuit shown in FIG. 2 and it is not necessary to apply complementary control voltages.

Another embodiment of the present invention is shown in FIG. This is an example in which the resistance whose value can be controlled by the voltage is configured only by the PMOS. The resistance value is changed by the control voltage VC to control the oscillation frequency. Similar to the embodiment shown in FIG. 4, this embodiment can be configured with 3/4 the number of elements of the conventional circuit shown in FIG. 2, and it is not necessary to apply a complementary control voltage. The circuit scale of is also reduced.

The variable resistor 2 composed of the CMOS, NMOS, and PMOS described above does not have to be connected to all the stages of the inverting amplifier 1 and may have at least one stage. However, when this number is small, the controllable frequency range is narrowed.

Another embodiment of the present invention is shown in FIG. 4 is an example in which a phase-locked oscillator (PLL) is configured using the voltage controlled oscillator (VCO) of the embodiment shown in FIG. It oscillates in synchronization with four times the frequency of the input reference clock.

The output OUT of the VCO is 4 by the frequency divider 8.
The divided clock is input to the phase comparison circuit 5, and the reference clock R
It is compared with the phase of EF. The phase comparison circuit 5 generates a signal for controlling the oscillation frequency according to the phase difference between the reference clock and the clock obtained by dividing the output of the VCO by 4. The charge pump 6 controls the potential of the node CP2 by charging / discharging the capacitor C according to this control signal. The current mirror circuit 7 generates complementary oscillation control potentials VCu and VCd from the potential of the node CP2.

Since the oscillation frequency of this circuit is strongly influenced by the potential fluctuation of the node CP2, it is necessary to suppress the influence of power supply noise. Since the impedance between the node CP2 and the power supply Vdd is low, it is necessary to reduce the noise of the power supply Vdd. For this purpose, it is preferable to use the power supply Vdd as the power supply for the well and separate it from the noisy substrate.
In addition, since the impedance between the GND and the gate electrode of the variable resistance pMOS transistor is low, it is necessary to reduce the fluctuation of GND. Therefore, in the circuit of this embodiment, PLL-Vdd and PLL-GND supplied to the VCO are used.
Are connected to the digital circuit power supplies D-Vdd and D-GND.
VCO board ground terminal Sub-G
The ND is also separated from each of the above power supply terminals.

The present embodiment is designed to obtain an output having a frequency four times as high as that of the reference clock REF. However, by setting the frequency division number of the frequency divider to 1 / n, an arbitrary n-fold frequency can be obtained. The oscillation output can be obtained.

The power supply isolation for noise suppression is based on the premise that CMOS transistors are formed on a p-type substrate. When a CMOS transistor is formed on an n-type substrate, the substrate ground terminal may be a well ground terminal. Further, in this embodiment, the capacitance C of the charge pump is connected to PLL-Vdd, but it may be grounded to PLL-GND as shown in FIG. In this case, contrary to the present embodiment, since the potential fluctuation of Vdd significantly affects the oscillation frequency, the power supply Vdd supplied to the back terminal of the pMOS transistor is separated from other power supplies. FIG. 8 shows another embodiment of the circuit for supplying the complementary control voltages VCu and VCd. In the embodiment shown in FIG. 6, the current mirror circuit is adopted, but the differential amplifier shown in FIG. 8 can be used. By using the differential amplifier, the resistance to fluctuations in the power supply voltage increases. The above noise countermeasure is shown in Fig. 1.
The same can be applied to each of the embodiments shown in FIGS. 3, 4 and 5.

[0017]

According to the present invention, the fluctuation of the threshold voltage is suppressed and the remarkable decrease of the oscillation frequency is suppressed. Further, the substrate bias does not fluctuate even when the power supply voltage fluctuates, and the operation margin does not decrease.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a conventional example.

FIG. 3 is a second embodiment of the present invention.

FIG. 4 is a third embodiment of the present invention.

FIG. 5 is a fourth embodiment of the present invention.

FIG. 6 is an application example of the second embodiment of the present invention.

7 is another embodiment of some circuits of the embodiment of FIG. 6 of the present invention.

8 is another embodiment of some circuits of the embodiment of FIG. 6 of the present invention.

[Explanation of symbols]

1 ... Inversion amplifier, 2 ... Variable resistor, 21, 22, 23 ...
Variable resistor composed of CMOS, NMOS, PMOS,
3 ... Control terminal, 4 ... Current limiting transistor, 5 ... Phase comparator, 6 ... Charge pump, 7 ... Current mirror circuit, 8 ... Divider.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Tanaka             1-280, Higashikoigokubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kakusei             Hitachi Device, 3681 Hayano, Mobara-shi, Chiba             Engineering Co., Ltd. (72) Inventor Shoji Hanamura             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Design and Development Center

Claims (6)

[Claims] 1. A voltage controlled oscillator circuit capable of controlling an oscillation frequency by a voltage applied to a control terminal or a group of control terminals, wherein an inverting amplifier group of an odd number stage, an output terminal of the inverting amplifier and an inversion of the next stage. The variable resistor group, which is inserted between the input terminals of the amplifier and has the same number as or less than that of the inverting amplifier which changes the resistance value in accordance with the voltage applied to the control terminal or the control terminal group, is included in the final stage. A voltage controlled oscillator circuit, wherein another terminal of the variable resistor connected to the inverting amplifier is connected to the input terminal of the above-mentioned inverting amplifier in the first stage. 2. The variable resistor according to claim 1 is formed of a complementary MOS transistor,
A voltage controlled oscillator circuit, wherein complementary control voltages are applied to respective gate terminals of a P-channel MOS transistor and an N-channel MOS transistor of the transistor. 3. A variable resistor according to claim 1 comprising a P-channel or N-channel MOS transistor, and the P-channel or N-channel MOS transistor.
A voltage controlled oscillator circuit characterized in that a control voltage is applied to a gate terminal of a transistor. 4. A phase locked loop circuit comprising the voltage controlled oscillator circuit according to claim 1, a charge pump circuit, and a phase comparator. 5. A phase-locked loop circuit characterized in that the power supply to the voltage controlled oscillator circuit according to claim 4 is separated from the power supplies of other circuits. 6. A phase-locked loop circuit characterized in that the power supply supplied to the source electrode of the MOS transistor constituting the voltage controlled oscillator circuit according to claim 4 is separated from the power supply supplied to the back electrode. .