CN114204918A - Oscillator - Google Patents
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- CN114204918A CN114204918A CN202010982496.2A CN202010982496A CN114204918A CN 114204918 A CN114204918 A CN 114204918A CN 202010982496 A CN202010982496 A CN 202010982496A CN 114204918 A CN114204918 A CN 114204918A
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- 239000003990 capacitor Substances 0.000 claims abstract description 81
- 238000007599 discharging Methods 0.000 claims abstract description 16
- 230000010355 oscillation Effects 0.000 claims description 26
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 16
- 230000001276 controlling effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
Abstract
The invention discloses an oscillator. The circuit comprises an oscillating circuit, wherein the oscillating circuit comprises a charging and discharging module and a voltage stabilizing circuit, the charging and discharging module comprises a first current branch circuit, a first capacitor and a first switch, the first current branch circuit and the first capacitor are connected between a power supply voltage and the ground, the first switch is connected between two ends of the first capacitor in parallel and used for providing a discharging path from a first end of the first capacitor to the ground, and a middle node of the first current branch circuit and the first capacitor is used for outputting a ramp voltage; a first comparator for comparing the ramp voltage with a reference voltage to generate a clock signal; and the current control module is connected with the first current branch and is used for controlling the current of the first current branch so as to control the frequency range of the clock signal, thereby obtaining the adjustable frequency oscillator with wide frequency range.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to an oscillator.
Background
With the popularization of portable electronic products, switching power supplies become more and more important, and power supplies used by modern electronic devices are roughly classified into linear voltage-stabilized power supplies and switching voltage-stabilized power supplies. The adjusting tube of the linear voltage-stabilized power supply works in an amplifying region, has the advantages of no introduction of additional interference, good reliability and low cost, but has the defects of larger volume and low conversion efficiency. Compared with a linear voltage-stabilized power supply, the switching power supply has the characteristics of being capable of boosting and reducing voltage and high in power supply efficiency. However, switching power supplies produce electromagnetic interference noise (EMI) when regulating voltage and current, and this electrical noise can be transmitted to the ac power line and can affect not only the permission of other electronic devices in the vicinity of the power supply by conduction, but also radiation or leakage from the power line, affecting devices not connected to the power line. These disturbances can increase significantly as the switching frequency increases and the increase in output power can pose a potential threat to the proper operation of the electronic device.
In order to suppress the interference of the switching power supply and make the switching power supply meet the requirements of relevant electromagnetic compatibility standards, the switching power supply in the prior art adopts a frequency jitter technology to increase the harmonic frequency, so that the frequency can be dispersed, namely, the switching frequency is periodically changed, so that the noise harmonic frequency is dispersed, the noise energy is dispersed and reduced, the amplitude margin is ensured on the whole frequency band, and the electromagnetic compatibility requirements are met.
The prior art switching power supply usually uses an analog method for frequency dithering, which is feasible at a specific frequency, but the analog method is very limited in frequency dithering if the frequency variation range is wide and an external clock frequency is required. For example, if the clock frequency is low, the jitter frequency of the analog method needs to set a large capacitor inside the chip; if the frequency of the external clock is high, the method needs to arrange a large capacitor charging current in the chip, and the chip volume and the cost are increased.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a tunable frequency oscillator with a wide frequency range, which can achieve good frequency jitter at different frequencies.
According to an aspect of the embodiments of the present invention, there is provided an oscillator including an oscillation circuit that generates a clock signal by charging and discharging a first capacitor, wherein the oscillation circuit includes: the charging and discharging module comprises a first current branch circuit, a first capacitor and a first switch, wherein the first current branch circuit and the first capacitor are connected between a power supply voltage and the ground, the first switch is connected between two ends of the first capacitor in parallel and used for providing a discharging path from a first end of the first capacitor to the ground, and a middle node of the first current branch circuit and the first capacitor is used for outputting a ramp voltage; a first comparator for comparing the ramp voltage with a reference voltage to generate the clock signal; and the current control module is connected with the first current branch and is used for controlling the current of the first current branch so as to control the frequency range of the clock signal.
Optionally, the first current branch includes a first transistor and a second switch sequentially connected in series between the power supply voltage and the second end of the first capacitor.
Optionally, the current control module includes: the second transistor, the third transistor, the first resistor and the second resistor are sequentially connected between the power supply voltage and the ground in series, and the second transistor and the first transistor form a current mirror; a first current source having a first terminal connected to the power supply voltage and a second terminal connected to a first node between the first resistor and the second resistor; and the inverting input end of the operational amplifier is connected with the first node, the non-inverting input end of the operational amplifier is used for receiving a first reference voltage, and the output end of the operational amplifier is connected with the control end of the third transistor, wherein the resistance value of the second resistor is adjustable, and the current of the first current branch is controlled by adjusting the resistance value of the second resistor.
Optionally, the charging and discharging module further includes: a second current branch comprising a second current source and a third switch connected in series between the supply voltage and the first end of the first capacitor; and a third current branch comprising a third current source and a fourth switch connected in series between the supply voltage and the first end of the first capacitor, wherein the third switch and the fourth switch are turned on under a condition that the first node is in a short circuit or an open circuit, respectively, to control the frequency range of the clock signal.
Optionally, the oscillation circuit further includes: and the switching control module is suitable for comparing the first node voltage with a second reference voltage and a third reference voltage and controlling one of the second switch and the fourth switch to be conducted according to a comparison result.
Optionally, the switching control module includes: a second comparator, wherein a positive phase input end is used for receiving the second reference voltage, an inverse phase input end is used for receiving the first node voltage, and an output end is used for outputting a second switching control signal; a positive phase input end of the third comparator is used for receiving the first node voltage, a negative phase input end of the third comparator is used for receiving the third reference voltage, and an output end of the third comparator is used for outputting a third switching control signal; and the first input end of the NOR gate receives the second switching control signal, the second input end of the NOR gate receives the third switching control signal, and the output end of the NOR gate is used for outputting the first switching control signal, wherein the first switching control signal to the third switching control signal are respectively used for controlling the on and off of the second switch to the fourth switch.
Optionally, the oscillator further includes: and the frequency jitter control circuit is connected in parallel with two ends of the first capacitor and used for providing an external capacitor with a periodically changed capacitance value under the feedback control of the clock signal so as to realize the frequency jitter of the clock signal.
Optionally, the frequency jitter control circuit includes a plurality of branches arranged in parallel, and each branch includes a controllable switch and a second capacitor connected in series.
Optionally, the oscillator further includes: and the counting circuit is used for converting the clock signal into a plurality of control signals which are in one-to-one correspondence with the plurality of branches, and each control signal is used for controlling the on and off of the controllable switch of the corresponding branch.
Optionally, the capacitance values of the plurality of second capacitors in the frequency jitter control circuit are increased from low to high in a binary weighted manner.
Optionally, the plurality of control signals have different frequencies respectively.
Optionally, the counting circuit is implemented by a synchronous binary counter.
The oscillation circuit comprises a current control module, wherein the current control module is connected with a first current branch in a charge-discharge module, and the current of the first current branch is controlled by adjusting the resistance value of an adjustable resistor in the current control module so as to control the frequency of a clock signal generated by the oscillation circuit, so that the adjustable frequency oscillator with a wide frequency range is obtained.
Furthermore, the oscillator also comprises a frequency jitter control circuit, the frequency jitter control circuit forms frequency jitter according to the feedback control of the clock signal output by the oscillation circuit, frequency jitter can be well carried out under different frequencies without adding a frequency source and arranging a large capacitor and a charging current in the chip, and the method is simple, easy to integrate and beneficial to saving cost.
Furthermore, the oscillator also comprises a binary synchronous counter, the counter counts clock signals output by the oscillating circuit, and forms a plurality of control signals through parallel data output ends so as to control the periodic change of capacitance values in the frequency jitter circuit, and the control method is simple and effective.
Furthermore, the oscillation circuit further comprises a second current branch and a third current branch, and the second current branch and the third current branch can be opened when the adjustable resistor in the current control module is short-circuited or opened, so that the frequency of the oscillator can be still set when the external resistor in the oscillator is short-circuited or opened, and the performance of the oscillator is favorably improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a circuit schematic of an oscillator for generating a clock signal in a switching power supply of the prior art;
FIG. 2 shows a waveform schematic of a clock signal output by a prior art oscillator;
fig. 3 is a circuit diagram of an oscillator for generating a clock signal in a switching power supply according to an embodiment of the present invention;
fig. 4 shows a waveform diagram of the clock signal output by the oscillator and the control signals Q1-Q3 when n is 3;
FIG. 5 shows a circuit schematic of the oscillating circuit of FIG. 3;
fig. 6 shows a schematic diagram of the counting circuit in fig. 3.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected" or "coupled" to another element, or being "connected" or "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may also be present, and the connection or coupling between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Fig. 1 shows a circuit schematic of an oscillator for generating a clock signal in a switching power supply of the prior art. As shown in fig. 1, the oscillator 100 includes a charge and discharge circuit 110, a comparator comp, and a buffer buff. The charge and discharge circuit 110 includes a first current source I1, a capacitor C0, and a transistor M1 connected between the power supply voltage VCC and the ground, the transistor M1 is connected between two ends of the capacitor C0, and an intermediate node between the first current source I1 and the capacitor C0 is used for outputting the ramp voltage Vslope. The positive input terminal of the comparator comp receives the ramp voltage Vslope, and the negative input terminal receives a reference voltage Vref. In the initial state, the charge on the capacitor C0 is zero, the ramp voltage Vslope is smaller than the reference voltage Vref, the output of the comparator comp is low, the transistor M1 is turned off, the first current source I1 charges the capacitor C0, when the ramp voltage Vslope is greater than the reference voltage Vref, the comparator output is inverted, the transistor M1 is turned on, the capacitor C0 starts to discharge to ground, because the gate of the transistor M1 is high, the discharge current of the capacitor C0 is much greater than the charge current of the first current source I1 to the capacitor C0, and therefore the ramp voltage Vslope starts to fall. When the ramp voltage Vslope drops to a value slightly less than the reference voltage Vref, the output of the comparator comp is inverted again, the transistor M1 is turned off, and the first current source I1 starts to charge the capacitor C0 again to start the next oscillation cycle.
The frequency of the oscillator in fig. 1 is determined by the size of the capacitor C0, and without an external parallel capacitor, the oscillator would output a square wave with a fixed frequency, as shown in fig. 2.
Fig. 3 is a circuit diagram of an oscillator for generating a clock signal in a switching power supply according to an embodiment of the present invention. As shown in fig. 3, the oscillator 200 includes an oscillation circuit 210, a frequency jitter control circuit 220, and a counting circuit 230.
The oscillating circuit 210 generates a clock signal CLK by charging and discharging the capacitor C0. The frequency jitter control circuit 220 is connected in parallel to two ends of the charging and discharging capacitor C0 inside the oscillation circuit 210, and the frequency jitter control circuit 220 provides an external capacitor with a periodically changing capacitance value under the feedback control of the clock signal CLK output by the oscillation circuit 210, so as to periodically change the frequency of the clock signal CLK output by the oscillation circuit 210. The frequency jitter control circuit 220 includes a plurality of parallel branches, and each parallel branch is connected with a controllable switch and a capacitor in series. The clock signal input terminal of the counting circuit 230 is connected to the signal output terminal OUT of the oscillating circuit 210, and is configured to convert the clock signal CLK output by the oscillating circuit 210 into control signals with different fixed frequencies respectively corresponding to the controllable switches on each branch.
The number of the control signals is equal to the number of the branches in the frequency jitter control circuit 220, and when the controllable switch corresponding to the control signal is turned off, the capacitance on the corresponding branch in the frequency jitter control circuit 220 is connected in parallel with the charge and discharge capacitance inside the oscillation circuit 210.
Specifically, the counting circuit 230 is a synchronous binary counter, the number of bits of the synchronous binary counter is equal to the number of parallel branches in the frequency jitter control circuit 220, the synchronous binary counter counts the clock signal CLK output by the oscillating circuit 210, and outputs control signals corresponding to the controllable switches respectively through parallel data. Illustratively, the counting circuit 230 synchronously counts the clock signal CLK output from the oscillation circuit 210, and outputs n control signals Q1-Qn through n parallel data outputs thereof, where n is an integer greater than 2, Q1 is the least significant bit, and Qn is the most significant bit. The counting circuit 230 may be triggered by either a rising or falling edge. The present embodiment employs a falling edge triggered synchronous binary counter.
The frequency jitter control circuit 220 comprises n parallel branches, each branch is connected in parallel with a capacitor C0, each branch is connected in series with a controllable switch and a capacitor, and the controllable switch can be one of a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor or a bipolar transistor. The counting circuit 230 counts the output signals of the oscillating circuit 210 and outputs n control signals Q1-Qn through n parallel data output terminals thereof, which are respectively used for controlling the controllable switches S1-Sn on the n branches.
Illustratively, n switches in the frequency jitter control circuit 220 are respectively implemented by NMOS transistors, and when the control signal is "1" (high level), the switches are turned on; when the control signal is "0" (low level), the switch is turned off. When the switch is closed, the capacitance on the corresponding branch is in parallel with the capacitance C0 inside the oscillating circuit 210. The capacitance values of the n branches in the frequency jitter control circuit 220 are sequentially increased in a binary weighted manner, that is, the capacitance value of the branch capacitor C1 corresponding to the control signal Q1 is C, and the control signal Q isThe capacitance value of the branch capacitor C2 corresponding to the signal Q2 is 2C, and so on, the capacitance value of the capacitor Cn on the branch corresponding to the control signal Qn is 2nC (C is the unit capacitance).
In the initial state, the control signals Q1-Qn are all "0", the switches S1-Sn on n branches in the frequency jitter control circuit 220 are all in the off state, when the 1 st falling edge arrives, the control signal Q1 becomes "1", the rest of the control signals are still "0", the switch S1 of the branch corresponding to the control signal Q1 is closed, and the capacitor C1 on the branch is connected in parallel with the capacitor C0 in the oscillation circuit 210. When the 2 nd falling edge arrives, the control signal Q2 becomes "1", the rest of the control signals are still "0", the switch S2 of the branch corresponding to the control signal Q2 is closed, and the capacitor C2 on the branch is connected in parallel with the capacitor C0 in the oscillating circuit 210. By analogy, the control signals Q1-Qn change in binary, and since the states thereof determine the parallel connection of the n capacitors in the frequency jitter control circuit 220 and the capacitor C0 in the oscillation circuit 210, the size of the capacitor connected in parallel with the capacitor C0 also changes in binary. Since the frequency of the oscillating circuit 210 is determined by the sum of the capacitance C0 and the external capacitance connected in parallel with the capacitor C0, the frequency of the oscillating circuit 210 will change periodically according to a certain rule.
Taking n as an example, that is, the counting circuit 230 adopts a 3-bit synchronous binary counter, and its parallel data output terminal outputs 3 control signals Q1-Q3, where Q1 is the lowest bit and Q3 is the highest bit, the frequency jitter control circuit 220 includes 3 parallel branches, and the capacitance values of the capacitances corresponding to the control signals Q1-Q3 on each parallel branch are C, 2C, and 4C, respectively. Fig. 4 shows waveforms of the clock signal output by the oscillator and the control signals Q1-Q3 when n is 3, and as shown in fig. 4, the frequency of the output signal of the oscillating circuit 210 changes periodically, so as to achieve the purpose of frequency jitter.
Fig. 5 shows a circuit schematic of the oscillating circuit in fig. 3. As shown in fig. 5, the oscillating circuit 210 further includes a charging and discharging module 211, a first comparator comp1, a current control module 212, and a switching control module 213.
The charging and discharging module 211 includes a first current branch, the capacitor C0, and a first switch K1. The first current branch and the capacitor C0 are connected between the power supply voltage VCC and the ground, and the first switch K1 is connected in parallel between two ends of the capacitor C0 for providing a discharge path from the first end of the capacitor C0 to the ground. The first current branch comprises a transistor M1 and a second switch K2 connected in series, the transistor M1 is used for providing a charging current to the capacitor C0 in a mirror image manner, and an intermediate node CT between the first current branch and the capacitor C0 is used for outputting a ramp voltage Vslope.
The first comparator comp1 compares the ramp voltage Vslope with a reference voltage Vref to generate the clock signal CLK.
The current control module 212 is connected to a first current branch of the charging and discharging module 211, and the current control module 212 is configured to control a current of the first current branch to control a frequency range of the clock signal.
Further, the current control module 212 includes a first current source I1, an operational amplifier OPA, a transistor M2, a transistor M3, a resistor R1, and a resistor Rosc. The transistor M2, the transistor M3, the resistor R1, and the resistor Rosc are sequentially connected in series between the power supply voltage VCC and the ground, and the transistor M2 and the transistor M1 constitute a current mirror. A first terminal of the first current source I1 is connected to the supply voltage VCC, and a second terminal is connected to a node a between the resistor R1 and the resistor Rosc. The inverting input terminal of the operational amplifier OPA is connected to the node a, the non-inverting input terminal is used for receiving the first reference voltage Vb1, and the output terminal is connected to the control terminal of the transistor M3. The resistor Rosc is an external adjustable resistor, and the current flowing through the transistor M1 is controlled by adjusting the resistance of the resistor Rosc.
In the initial state, the second switch K2 is turned on, the charge on the capacitor C0 is zero, the ramp voltage Vslope is smaller than the reference voltage Vref, the output of the first comparator comp1 is low, the first switch K1 is turned off, the transistor M1 charges the capacitor C0, when the ramp voltage Vslope is larger than the reference voltage Vref, the output of the first comparator comp1 is inverted, the first switch K1 is turned on, the capacitor C0 starts to discharge to the ground, because the discharge current of the capacitor C0 is much larger than the charge current of the transistor M1 to the capacitor C0, and therefore the ramp voltage Vslope starts to fall. When the ramp voltage Vslope drops to a value slightly less than the reference voltage Vref, the output of the first comparator comp1 is inverted again, the first switch K1 is turned off, the transistor M1 starts to charge the capacitor C0 again, and the next oscillation cycle starts.
Further, the charging and discharging module 211 further includes a second current branch and a third current branch connected in parallel with the first current branch. The second current branch comprises a second current source I2 and a third switch K3 connected in series between said supply voltage VCC and a first terminal of a capacitor C0. The third current branch comprises a third current source I3 and a fourth switch K4 connected in series between the supply voltage VCC and the first terminal of the capacitor C0. Wherein the third switch K3 and the fourth switch K4 are turned on when the node a is short-circuited or open-circuited, respectively, to control the frequency range of the clock signal when the external resistor Rosc is short-circuited or open-circuited.
Further, the switching control module 213 is configured to compare the voltage VA at the node a with the second reference voltage Vb2 and the third reference voltage Vb3, and control one of the second switch K2 to the fourth switch K4 to be turned on according to the comparison result.
Further, the switching control module includes a second comparator comp2, a third comparator comp3, and a NOR gate NOR. The second comparator comp2 has a non-inverting input for receiving the second reference voltage Vb2, an inverting input for receiving the node voltage VA, and an output for outputting a second switching control signal SC 2. The third comparator comp3 has a non-inverting input for receiving the node voltage VA, an inverting input for receiving the third reference voltage Vb3, and an output for outputting a third switching control signal SC 3. The NOR gate NOR has a first input terminal receiving the second switching control signal SC2, a second input terminal receiving the third switching control signal SC3, and an output terminal outputting the first switching control signal SC 1. The first to third switching control signals SC1 to SC3 are respectively used for controlling the second to fourth switches K2 to K4 to be turned on and off.
The voltage values of the second reference voltage Vb2 and the third reference voltage Vb3 can be set by those skilled in the art according to specific situations. In the present embodiment, both the second reference voltage Vb2 and the third reference voltage Vb3 are smaller than the power supply voltage VCC, and the second reference voltage Vb2 is smaller than the third reference voltage Vb 3. When the node a is short-circuited, the node voltage VA is smaller than the second reference voltage Vb2 and the third reference voltage Vb3, the second comparator comp2 outputs a high level, the third comparator comp3 outputs a low level, that is, the first switching control signal SC1 and the third switching control signal SC3 are low level, the second switching control signal SC2 is high level, the second switch K2 and the fourth switch K4 are turned off, the third switch K3 is turned on, and the capacitor C0 is charged by the second current source I2; when the node a is opened, the node voltage VA is pulled up to the power supply voltage VCC by the first current source I1, the node voltage VA is greater than the second reference voltage Vb2 and the third reference voltage Vb3, the second comparator comp2 outputs a low level, the third comparator comp3 outputs a high level, at this time, the first switching control signal SC1 and the second switching control signal SC2 are low levels, the third switching control signal SC3 is a high level, the second switch K2 and the third switch K3 are turned off, the fourth switch K4 is turned on, and the capacitor C0 is charged by the third current source I3; when the node a is at the normal potential, the node voltage VA is greater than the second reference voltage Vb2 and less than the third reference voltage Vb3, the second comparator comp2 and the third comparator comp3 both output a low level, the second switching control signal SC2 and the third switching control signal SC3 are at a low level, the first switching control signal SC1 is at a high level, the third switch K3 and the fourth switch K4 are turned off, the second switch K2 is turned on, and the capacitor C0 is charged by the transistor M1.
Fig. 6 shows a schematic diagram of the counting circuit in fig. 3. As shown in FIG. 6, the counting circuit 230 includes n D flip-flops and n multiplexers MUX 1-MUXn. The n D flip-flops are cascaded with each other, and each D flip-flop includes a data input terminal D, a clock terminal Clk, a first output terminal Q +, and a second output terminal Q-. The clock terminal Clk of each of the first stage D flip-flops is configured to receive the clock signal Clk output by the oscillation circuit 210, the clock terminal Clk of each of the stage D flip-flops other than the first stage D flip-flop is connected to the first output terminal Q + of the previous stage D flip-flop, and the data input terminal D of each of the stage D flip-flops is connected to the second output terminal Q-. The n multiplexers MUX1-MUXn are alternative multiplexers, each multiplexer is connected to the first output terminal Q + and the second output terminal Q-of the corresponding D flip-flop, respectively, and is configured to obtain the corresponding control signal according to the output of the corresponding D flip-flop.
In summary, an embodiment of the present invention provides an oscillation circuit, where the oscillation circuit includes a current control module, the current control module is connected to a first current branch in a charge-discharge module, and controls a current of the first current branch by adjusting a resistance of an adjustable resistor in the current control module to control a frequency of a clock signal generated by the oscillation circuit, so as to obtain an adjustable frequency oscillator with a wide frequency range.
In a further embodiment, the oscillator further comprises a frequency jitter control circuit, the frequency jitter control circuit forms frequency jitter according to the feedback control of the clock signal output by the oscillation circuit, frequency jitter can be well carried out under different frequencies without an external frequency source and a large capacitor and charging current arranged in a chip, and the method is simple, easy to integrate and beneficial to saving cost.
In a further embodiment, the clock signal output by the oscillation circuit is counted by the binary synchronous counter, and a plurality of control signals are formed by the parallel data output end to control the periodic variation of the capacitance value in the frequency jitter circuit, so that the control method is simple and effective.
In a further embodiment, the oscillation circuit of the present invention further includes a second current branch and a third current branch, where the second current branch and the third current branch may be turned on when the adjustable resistor in the current control module is short-circuited or open-circuited, so that the frequency of the oscillator may still be set when the external resistor in the oscillator is short-circuited or open-circuited, which is beneficial to improving the performance of the oscillator.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. An oscillator comprising an oscillation circuit that generates a clock signal by charging and discharging a first capacitor, wherein the oscillation circuit comprises:
the charging and discharging module comprises a first current branch circuit, a first capacitor and a first switch, wherein the first current branch circuit and the first capacitor are connected between a power supply voltage and the ground, the first switch is connected between two ends of the first capacitor in parallel and used for providing a discharging path from a first end of the first capacitor to the ground, and a middle node of the first current branch circuit and the first capacitor is used for outputting a ramp voltage;
a first comparator for comparing the ramp voltage with a reference voltage to generate the clock signal; and
and the current control module is connected with the first current branch and is used for controlling the current of the first current branch so as to control the frequency range of the clock signal.
2. The oscillator of claim 1, wherein the first current branch comprises a first transistor and a second switch connected in series between the supply voltage and the second terminal of the first capacitor.
3. The oscillator of claim 2, wherein the current control module comprises:
the second transistor, the third transistor, the first resistor and the second resistor are sequentially connected between the power supply voltage and the ground in series, and the second transistor and the first transistor form a current mirror;
a first current source having a first terminal connected to the power supply voltage and a second terminal connected to a first node between the first resistor and the second resistor; and
an operational amplifier having an inverting input connected to the first node, a non-inverting input for receiving a first reference voltage, and an output connected to the control terminal of the third transistor,
the resistance value of the second resistor is adjustable, and the current of the first current branch is controlled by adjusting the resistance value of the second resistor.
4. The oscillator of claim 3, wherein the charge-discharge module further comprises:
a second current branch comprising a second current source and a third switch connected in series between the supply voltage and the first end of the first capacitor; and
a third current branch comprising a third current source and a fourth switch connected in series between the supply voltage and the first terminal of the first capacitor,
wherein the third switch and the fourth switch are turned on to control a frequency range of the clock signal when the first node is in a short circuit or an open circuit, respectively.
5. The oscillator of claim 4, wherein the oscillating circuit further comprises:
and the switching control module is suitable for comparing the first node voltage with a second reference voltage and a third reference voltage and controlling one of the second switch and the fourth switch to be conducted according to a comparison result.
6. The oscillator of claim 5, wherein the switching control module comprises:
a second comparator, wherein a positive phase input end is used for receiving the second reference voltage, an inverse phase input end is used for receiving the first node voltage, and an output end is used for outputting a second switching control signal;
a positive phase input end of the third comparator is used for receiving the first node voltage, a negative phase input end of the third comparator is used for receiving the third reference voltage, and an output end of the third comparator is used for outputting a third switching control signal; and
a NOR gate, a first input end receiving the second switching control signal, a second input end receiving the third switching control signal, and an output end for outputting a first switching control signal,
the first switching control signal to the third switching control signal are respectively used for controlling the on and off of the second switch to the fourth switch.
7. The oscillator of claim 1, further comprising:
and the frequency jitter control circuit is connected in parallel with two ends of the first capacitor and used for providing an external capacitor with a periodically changed capacitance value under the feedback control of the clock signal so as to realize the frequency jitter of the clock signal.
8. The oscillator of claim 7, wherein the frequency jitter control circuit comprises a plurality of branches arranged in parallel, each branch comprising a controllable switch and a second capacitor connected in series.
9. The oscillator of claim 8, further comprising:
and the counting circuit is used for converting the clock signal into a plurality of control signals which are in one-to-one correspondence with the plurality of branches, and each control signal is used for controlling the on and off of the controllable switch of the corresponding branch.
10. The oscillator as claimed in claim 8, wherein the capacitance values of the plurality of second capacitors in the frequency jitter control circuit are increased from low to high in a binary weighted manner.
11. The oscillator of claim 9, wherein the counting circuit is implemented by a synchronous binary counter.
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