CN1296665A - Precision relaxation oscillator with temperature compensation and various operating modes - Google Patents
Precision relaxation oscillator with temperature compensation and various operating modes Download PDFInfo
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- CN1296665A CN1296665A CN99804764A CN99804764A CN1296665A CN 1296665 A CN1296665 A CN 1296665A CN 99804764 A CN99804764 A CN 99804764A CN 99804764 A CN99804764 A CN 99804764A CN 1296665 A CN1296665 A CN 1296665A
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Abstract
A precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator 100, two independent current generators 200, 300, a transition detector 400 and a clock pulse inhibitor 500. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The precision relaxation oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode. The precision relaxation oscillator with temperature compensation and various operating modes is implemented on a single, monolithic integrated circuit.
Description
Invention field
The present invention relates generally to produce the integrated circuit of clock pulse frequency, relate in particular to the precision relaxation oscillator that in ambient temperature, manufacturing process and the voltage scope that great changes will take place, produces the stabilizing clock pulse frequency.The present invention realizes on single monolithic integrated circuit.In addition, this precision relaxation oscillator can be operated under several modes.
The application is the U.S. Patent application 09/044th of the denomination of invention of application on March 19th, 1998 for " precision relaxation oscillator that has temperature-compensating " (" Precision Relaxation Oscillator With TemperatureCompensation "), No. 361 part continuation application, the U.S. Patent application the 09/044th of application on March 19th, 1998,361 transfer the assignee identical with the application, and have at least one co-inventor with the application.Quote hereby, for your guidance.
Description of the Prior Art
The present situation of prior art has been described the RC relaxation osillator that mainly depends on one of two kinds of schemes.In first example shown in Figure 1, single comparator and pulse generator coupling, alternately the charge and discharge capacitance device is used for the clock pulse of " D type " trigger with generation.In this design, exist several error sources.Resistance and capacitor have uncertain voltage and temperature coefficient usually.Charging current and comparator input swing (slew) is the function that also stands the supply voltage that drifts about.At this moment, pulse generator output also may change along with temperature and supply voltage.These factors have caused clock pulse frequency to change in whole temperature range.
In second embodiment shown in Figure 2, the RC circuit provides each public input of two comparators.Independently reference voltage is coupled to each of comparator remaining input terminal.Each output of two comparators all is coupled to " set-reset type " trigger.The output of trigger is used for alternately charge and discharge capacitance device.Although sort circuit has been eliminated the inexactness of the pulse generator existence of discussing as top Fig. 1, they itself still demonstrate other problem.Owing to can not especially under the situation that temperature changes, therefore, duty cycle error may take place with identical speed to capacitor charge and discharge.In addition, owing to be difficult to two reference voltages that the temperature step is as one man followed the tracks of mutually are provided, also can cause error.
Therefore, exist the needs that relaxation osillator that can temperature independent maintenance stabilizing clock pulse frequency is provided.
Summary of the invention
One of purpose of the present invention provides and a kind ofly can keep the temperature independent relaxation osillator of stabilizing clock pulse frequency.The stabilizing clock pulse is defined as the clock pulse that keeps stabilized frequency under the environment of experience temperature oscillation.
Another object of the present invention provides a kind of relaxation osillator that makes the temperature coefficient minimum of oscillator, and wherein the temperature coefficient of oscillator is that value (ppm/ ℃) after a few millionths with clock pulse frequency is removed by temperature is measured.For example, 1,000,000/every degree centigrade of the 4MHz clock pulse frequency equals 4 clock cycles.
A further object of the invention provides a kind of not being subjected to because the relaxation osillator that the frequency drift that processing procedure and supply voltage cause influences.
A further object of the invention provides three kinds of operator schemes that comprise fast mode, slow/low-power mode and park mode.
A further object of the invention is to reduce power consumption when operation under slow mode and park mode.
According to one embodiment of present invention, the invention discloses the precision relaxation oscillator that in the ambient temperature scope that great changes will take place, produces the stabilizing clock pulse frequency.Precision relaxation oscillator comprises clapp oscillator; Produce first current generator of first output current and second current feedback circuit of generation second output current.The present invention is achieved on single monolithic integrated circuit.
According to another embodiment of the invention, non-essential resistance can be coupled with first current feedback circuit or second current feedback circuit, generates and determines the needed corresponding output current of clock pulse frequency.
According to another embodiment of the invention, in first and second current feedback circuits, dispose several internal resistances, be used to select the clock pulse speed of oscillator.
According to another embodiment of the invention, disposed transition detector circuit.
According to another embodiment of the invention, disposed clock pulse inhibitor with the coupling of the output of clapp oscillator.
In conjunction with the drawings the preferred embodiments of the present invention are carried out following description more specifically, above and other objects of the present invention, feature and advantage will be clearer.
The accompanying drawing summary
Fig. 1 is the schematic diagram that shows the prior art that has pulse generator and simple R C relaxation osillator;
Fig. 2 is the schematic diagram that shows the prior art of dual comparator RC relaxation osillator;
Fig. 3 is a block diagram of the present invention;
Fig. 4 is the block diagram that is present in the CTAT current feedback circuit among the present invention;
Fig. 5 is the block diagram that is present in the PTAT current feedback circuit among the present invention;
Fig. 6 is the sequential chart of special parameter of the present invention; With
Fig. 7 is the sequential chart of clock pulse conversion between slow mode and fast mode.
Preferred embodiment describes in detail
With reference to Fig. 3, Fig. 3 has shown the precision relaxation oscillator 1 that produces the stabilizing clock pulse frequency in the ambient temperature scope that great changes will take place.Best, precision relaxation oscillator 1 produces the stabilizing clock pulse frequency in the scope of about 1kHz to 8MHz.Yet those of ordinary skill in the art should be realized that the present invention is not limited in specific frequency range.
Second kind of pattern is slow mode, can be selected to save electric power (power), also allows some functions of the circuit that precision relaxation oscillator 1 uses remain valid.The third pattern is a park mode, and in this pattern, precision relaxation oscillator 1 is in disarmed state, has not both had clock pulse output, also without any power consumption.Conversion between the pattern can produce " not working " (" on the fly "), that is the conversion from a kind of pattern to another kind of pattern needn't suspend the ongoing processing activity of CPU.But in a preferred embodiment, CPU or microprocessor will be finished the present instruction cycle before translative mode.
CTAT 200 and PTAT 300 current feedback circuits are realized independently of one another, and the present invention are produced several important function.CTAT 200 and PTAT 300 current feedback circuits are by (offseting) electric current CTAT electric current 220 and the PTAT electric current 320 of affording redress, promptly, with respect to the electric current that temperature has opposite slope, come compensates to the influence that internal part produced device such as resistance, capacitor and the comparator.CTAT electric current 290 and PTAT electric current 390 (Figure 4 and 5) are combined and are formed charging current of condenser I
Ccc190 (I
Ccc190=CTAT electric current 290+PTAT electric current 390).The combination of CTAT electric current 290 and PTAT electric current 390 or addition occur in when being incorporated into 100 pairs first capacitors 110 of clapp oscillator and 120 chargings of second capacitor.Because CTAT 290 and PTAT 390 electric currents are approximately linears, and have opposite slope with respect to temperature, therefore, the result of addition is I
Ccc190 is almost temperature independent.
In a preferred embodiment, clapp oscillator 100 comprises R-S flip-flop 160; Comparator circuit 180 further comprises two comparators 182 and 184; Two capacitors 110 and 120; Four transistor switches 130,132,134 and 136; Two inverters 140 and 142; With the band gap reference voltage that is used to produce reference voltage 152.
In this preferred embodiment, and, used stable reference voltage source such as band gap reference voltage circuit 150 in order to reach optimum performance.Band gap reference voltage circuit 150 provides single reference voltage 152, and it is connected to second input of comparator 182 and 184, and is used for utility mode voltage is provided with (set) at comparator 182 and 184 on each and be arranged on CTAT current feedback circuit 200.The P of band gap reference voltage circuit 150
BIAS Input 325 is the output of the following PTAT bias generator 310 that will illustrate.The advantage of band gap reference voltage circuit 150 is stabilising condenser charging currents and makes because the error minimum that the variation of comparator input swing and propagation delay cause.
In addition, in order to eliminate the influence of reference voltage drift, or the influence of reference voltage drift is reduced to minimum level, CTAT current feedback circuit 200 depends on the reference voltage 152 identical with comparator 182 and 184.For example, if reference voltage 152 raises, its value equals V
REFThe CTAT electric current 290 (Fig. 4) of/R also increases thereupon.If not compensation, the CTAT electric current of this increase will cause clock pulse frequency 166 faster, because produced bigger I
Ccc190, it causes quickly to capacitor 110 and 120 chargings.Yet capacitor 110 and 120 must be charged to higher level, so that the reference voltage 152 of the relative rising with 184 of comparator 182 is triped (trip).Therefore, the present invention needs simpler, cheaper reference voltage source to obtain clock pulse frequency stability.The embodiment that has various band gap reference voltage circuits 150, and other reference voltage source resemble the voltage divider, these all are well known to those of ordinary skill in the art.But the present invention realizes that the new method of band gap reference voltage circuit 150 is not open in the prior art.
The output of comparator 82 is connected to the set input 162 of trigger 160.The output of comparator 184 is connected to the RESET input 164 of trigger 160.Therefore, along with capacitor 110 and 120 alternately discharges and recharges, comparator 182 and 184 output replace R-S flip-flop 160, thereby generate the clock pulse input.
The Q output 166 of trigger 160 provides the stabilizing clock pulse frequency that is independent of variations in temperature INTCLK.In this preferred embodiment, Q output 166 also is sent to transistor switch 132 and arrives transistor switch 130 by inverter 140.Therefore, Q output 166 provides control to open and close capacitor 110 charging and the transistor switch 130 of discharge path and 132 signals.
The complementary Q output 168 of trigger 160 provides and also has been independent of temperature but exports the second stabilizing clock pulse frequency of 166 complementations with Q.Complementary Q output 168 is sent to transistor switch 136, and arrives transistor switch 134 by inverter 142.Therefore, complementary Q output 168 provides control to be used to open and close capacitor 120 charging and the transistor switch 134 of discharge path and 136 signals.
In case receive RSTCLK 402 signals from transition detector 400, the clock pulse inhibitor 500 that can be the simple programmable counter was just forbidden CLKOUT502 is sent to continuous circuit in the clock cycle of a predetermined number, for example, CPU (CPU).Therefore, clock pulse inhibitor 500 is used for preventing because the logic that the clock pulse frequency of unstable clock pulse frequency or conversion causes is unusual.After clock cycle, when the operating state of estimating precision relaxation oscillator 1 tends towards stability, clock pulse inhibitor 500 will allow CLKOUT 502 pass through to continuous circuit at the predetermined number that follows mode switch closely.
In addition, RSTCLK 402 signals is back along triggering SYNCH FAST/SLOW 404 signals.SYNCHFAST/SLOW 402 signals are by CTAT current feedback circuit 200 and PTAT current feedback circuit 300 is used for just fast or corresponding electric current 290 and 390 is adjusted in the slow mode operation, below this are illustrated.
With reference to Fig. 4, wherein identical label is represented identical unit.CTAT current feedback circuit 200 comprises CTAT bias generator 210 and is used to produce the current mirror circuit 205 of CTAT electric current 290.CTAT bias generator 210 comprises amplifier circuit 220; At least one resistance 232,233 and 234 with positive little temperature coefficient is used to be adjusted to the input current of amplifier; With transistor 240, be used for input current is offered amplifier 220.Amplifier 200 is cascode amplifier (cascode) structures, is used for power supply and noise suppressed.Reference voltage 152 is coupled to the input of amplifier 220.
The different resistance 232,233 and 234 of impedance variation are to be used for controlling the electric current that is sent to current mirror circuit 250, determine thus by clapp oscillator 100 specific stabilizing clock pulse frequencies that produce, temperature independent.The invention provides the selection logical block 230 and the resistance selected cell (RSELECT 236) that is used to select one of three resistance 232,233 or 234 of input SYNCH FAST/SLOW 404.If SYNCH FAST/SLOW 404 has enabled slow mode, so, select internal resistance RINT/LP 233.If SYNCH FAST/SLOW 404 has enabled fast mode, so, select logical block 230 to think input R in selecting
SELECTThe 236th, at internal resistance R
INT232 with non-essential resistance R
EXTBetween 234.
In this preferred embodiment, fast mode internal resistance 232 utilizes the polysilicon technology to make, this polysilicon technique guarantee Low ESR, high current is provided thus, this provides very fast clock pulse again.In addition, the polysilicon technology also has low-temperature coefficient (ppm/ ℃), thereby the frequency stability of having improved to temperature is provided.
By contrast, slow mode internal resistance 233 preferably utilizes the silicon-doped chip manufacturing, and by injecting and/or diffusion, for example, light dope exhausts methods such as (LDD, Lightly Doped Drain) usually.Doped silicon has produced high impedance, and it is reduced to the electric current of current mirror circuit 250, therefore allows to operate under low-power.
Slow mode internal resistance 233 also can utilize the manufacturing of polysilicon technology.But the unit area resistance of polysilicon significantly is lower than the unit area resistance of doped silicon.Therefore, for close resistance, polysilicon resistance need have much bigger semiconductor area than doped silicon resistance.In typical application, the power consumption scope of precision relaxation oscillator 1 is 20 μ A or littler under from 250 μ A (microampere) under the fast mode to slow mode.When being in park mode following time, then there is not power consumption.
In this preferred embodiment, current mirror circuit 250 is as shunt well known to those of ordinary skill in the art.In other embodiments, current mirror circuit 250 can be configured to current multiplier.CTAT electric current 290 is the summations from the selected output of current mirror transistor 252.
With reference to Fig. 5, wherein same numeral is represented same unit.Those of ordinary skills are known, as Δ V
BEThe PTAT current feedback circuit 300 of circuit comprises PTAT bias generator 310 and is used to produce the PTAT current mirror circuit 350 of PTAT electric current 390.PTAT bias generator 310 comprises: amplifier circuit 320; First biasing circuit 330 is used for producing first bias voltage at optional resistance 332,333 with little linear temperature coefficient and 334 two ends; With second biasing circuit 340, be used to produce second bias voltage.First and second bias voltages provide the input of pair amplifier 320.The output of amplifier 320 is the P that are coupled to first biasing circuit 330 and second biasing circuit 340, PTAT current mirror circuit 350 and band gap reference voltage generator 150 (Fig. 1)
DIAS325.
The different resistance 332,333 and 334 of impedance variable are to be used to control the electric current that is sent to current mirror circuit 350, determine thus by clapp oscillator 100 specific stabilizing clock pulse frequencies that produce, temperature independent.
Similar to CTAT bias generator 210, PTAT bias generator 310 provides the selection logical block 330 of input SYNCHFAST/SLOW 404 and has been used to select the resistance selected cell R of one of three resistance 332,333 or 334
SELECT236.If SYNCH FAST/SLOW 404 has enabled slow mode, so, select internal resistance R
1NT/LP333.If SYNCH FAST/SLOW has enabled fast mode, so, select logical block 330 to think input R in selecting
SELECTThe 336th, at internal resistance R
INT332 with non-essential resistance R
EXTBetween 334.
In this preferred embodiment, fast mode internal resistance 332 utilizes the polysilicon technology to make, this polysilicon technique guarantee Low ESR, high current is provided thus, this provides very fast clock pulse again.In addition, the polysilicon technology also has low-temperature coefficient (ppm/ ℃), thereby the frequency stability of having improved to temperature is provided.
By contrast, slow mode internal resistance 333 preferably utilizes diffusion technique, and for example, light dope exhausts method manufacturing.Diffusion technique produces the electric current that its high impedance is reduced to current mirror circuit 350 again, therefore allows to operate under low-power.Corresponding resistor in CTAT and PTAT bias generator 210 and 310 be to mating mutually to obtain optimum stabilization, for example, and two resistance R in fast mode
EXT234 and 334 or R
INT232 and 332 all is polysilicon, in slow mode, and two resistance R
INT/LP233 and 333 all is doped silicon.
Slow mode internal resistance 233 also can utilize the manufacturing of polysilicon technology.But the unit area resistance of polysilicon significantly is lower than the unit area resistance of diffusion technique.Therefore, for close resistance, the semiconductor area that polysilicon resistance need be more much bigger than doped silicon resistance.
PTAT current mirror circuit 350 comprises several transistors 352 from 1 to n.Adjustment is through the selection of 354 pairs of one or more current mirror transistor 352 of calibration switch or enable digitally to realize to obtain required PTAT electric current 390 by programming.
Calibration switch 354 also selects decoder 356 to couple mutually with SYNCH FAST/SLOW 404 signals by the PTAT calibration.In fast mode, calibration switch 354 is configured to adjust the electric current I that is used for fast clock pulse
PTATIn slow mode, calibration switch 354 can need different configuration adjustment to be used for the electric current I of slow clock pulse
PTATTherefore, calibration switch 354 is switched between fast mode calibration and slow mode calibration according to the state of SYNCH FAST/SLOW 404 signals.
In this preferred embodiment, current mirror circuit 350 is as shunt well known to those of ordinary skill in the art.In other embodiments, current mirror circuit 350 can be configured to current multiplier.PTAT electric current 390 is the summations from the selected output of current mirror transistor 352.
With reference to Fig. 6, wherein same numeral is represented same unit, and Fig. 6 has shown the general sequential chart (that is, non-pattern is correlated with) about relaxation osillator 1.Discharging and recharging of V1 112 expressions capacitor 110 (Fig. 1).Notice that the positive slope of V1 112 (charging) equals I
Ccc190 capacitances divided by capacitor 110.The amplitude peak of V1 112 equals reference voltage 152.CMP1 represents the output with the comparator 182 of set input 162 coupling of trigger 160.
Discharging and recharging of V2 122 expression capacitors 120.In this case, the positive slope of V2 122 equals I
Ccc190 capacitances divided by capacitor 120.The output of the comparator 184 of the RESET input 164 couplings of CMP 2 expressions and trigger 160.CLK is the Q output 166 of trigger 160.
Duty ratio for 50%, capacitor 110 is identical with 120 value, this has caused V1 122 and V2 122 to have close slope.Along with condenser voltage surpasses reference voltage 152, respective comparator 182 and 184 pulse amplitudes reduce, and this causes trigger 160 change states.RST (resetting) be used for comparator 182 and 184 and trigger 160 be initialized to known state.
With reference to Fig. 7, wherein same numeral is represented same unit, and Fig. 7 has shown that explanation converts the sequential chart of fast mode to from the slow mode of the embodiment of Fig. 3.When fast mode is transformed into slow mode, relaxation osillator will carry out similar operation.
In this sequential chart, relaxation osillator 1 (Fig. 3) is at first operated with slow mode.Transition detector 400 receives from the outside ASYNCH FAST/SLOW signal that generates of the present invention.In this preferred embodiment, logic level " 0 " expression slow mode, logic level " 1 " expression fast mode.The signal that is transformed into park mode is independent, effective high signal.
In case receive be transformed into fast mode, satisfy the ASYNCH FAST/SLOW signal of require the be provided with time relevant with internal clock pulse INTCLK 160, transition detector 400 just generates two outputs.Transition detector 400 outputs to clock pulse inhibitor 500 with reset pulse RSTCLK 402.Transition detector 400 also makes ASYNCH FAST/SLOW signal Synchronization, and on the back edge of RSTCLK 402, transition detector 400 outputs to current feedback circuit 200 and 300 with SYNCH FAST/SLOW 404.At this moment, current feedback circuit 200 and 300 begins conversion, to generate the needed electric current of fast mode.Along with current feedback circuit 200 and 300 their internal conversion of beginning, need make bias current steady (settle) and INTCLK 166 is settled out several clock cycles.
In case receive RSTCLK 402, clock pulse inhibitor 500 just begins to forbid CLKOUT502 at once.On the back edge of RSTCLK 504 pulses, relaxation osillator 1 begins to be transformed into fast mode from slow mode.In one embodiment, before release was forbidden and made CLXOUT 504 beginning fast mode clock pulse, the clock pulse inhibitor was in order to stablize eight fast clock cycles of counting and forbidding INTCLK 166.
The present invention makes because the clock pulse drift due to manufacturing process, supply voltage and the variation of temperature minimizes.This realizes in the following manner: provide when addition and compensation bias current that variations in temperature is irrelevant; Adjust to eliminate technology difference (variations) by programmable current mirror image circuit 250 and 350; And the stable reference voltage of use such as band gap reference voltage circuit 150 and dual-capacitor dual comparator clapp oscillator 110.In addition, board design technology well known to those of ordinary skill in the art, for example, parts match and cascode current source have also improved the stability of circuit.
Although by the present invention having been carried out concrete diagram and description with reference to preferential embodiment of the present invention, those of ordinary skill in the art should be understood that and can carry out in form and the change on the details, but all without departing from the spirit and scope of the present invention outside.
Claims (21)
1. precision relaxation oscillator that has temperature-compensation circuit comprises:
Clapp oscillator;
First current feedback circuit with the clapp oscillator coupling;
Second current feedback circuit with the clapp oscillator coupling;
Clock pulse inhibitor with the clapp oscillator coupling; With
Transition detector with the coupling of clock pulse inhibitor;
Wherein this circuit is realized on single integrated circuit.
2. circuit as claimed in claim 1, wherein, described circuit is used to produce clock pulse output and has multiple modes of operation, and described operator scheme comprises:
First operator scheme; With
Second operator scheme, the clock pulse output of wherein said second operator scheme have the slow frequency of clock pulse output than described first operator scheme.
3. circuit as claimed in claim 2, wherein:
Described first operator scheme produces a charging current of condenser; With
Described second operator scheme produces second charging current of condenser, makes second charging current of condenser less than first charging current of condenser.
4. circuit as claimed in claim 2, wherein:
Described first operator scheme has first rated watt consumption; With
Described second operator scheme has second rated watt consumption, makes second rated watt consumption less than first rated watt consumption.
5. circuit as claimed in claim 2, wherein, described circuit has the 3rd operator scheme that wherein said circuit does not produce clock pulse output.
6. circuit as claimed in claim 5, wherein, described the 3rd operator scheme does not produce charging current of condenser.
7. circuit as claimed in claim 5, wherein, described the 3rd operator scheme has the rated watt consumption that is close to zero.
8. circuit as claimed in claim 2, wherein, described first operator scheme is to be inner resistance and to select with respect to second current feedback circuit be that inner resistance is determined by selecting with respect to first current feedback circuit.
9. circuit as claimed in claim 8, wherein, described first operator scheme is that inner a plurality of calibration switch and programming is that inner a plurality of calibration switch are determined with respect to second current feedback circuit by programming with respect to first current feedback circuit further.
10. circuit as claimed in claim 2, wherein, described second operator scheme is to be the second inner resistance and to select with respect to second current feedback circuit be that the second inner resistance is determined by selecting with respect to first current feedback circuit.
11. circuit as claimed in claim 10, wherein, described second operator scheme is that inner a plurality of calibration switch and programming is that inner a plurality of calibration switch are determined with respect to second current feedback circuit by programming with respect to first current feedback circuit further.
12. circuit as claimed in claim 1, wherein, described clock pulse inhibitor comprises counter.
13. circuit as claimed in claim 12, wherein, described clock pulse inhibitor receives the switching signal from transition detector, and in case receives switching signal just stops clapp oscillator in the clock cycle of predetermined number clock pulse output.
14. circuit as claimed in claim 13, wherein, described clock pulse inhibitor allows tranmitting data register pulse output in process after the clock cycle of predetermined number.
15. circuit as claimed in claim 13, wherein, be programmable the clock cycle of described predetermined number.
16. a precision relaxation oscillator that has temperature-compensation circuit, wherein this circuit produces clock pulse output and has multiple modes of operation, and described operator scheme comprises:
First operator scheme; With
Second operator scheme, the clock pulse output of wherein said second operator scheme have the slow frequency of clock pulse output than described first operator scheme.
17. circuit as claimed in claim 16, wherein:
Described first operator scheme produces a charging current of condenser; With
Described second operator scheme produces second charging current of condenser, makes second charging current of condenser less than first charging current of condenser.
18. circuit as claimed in claim 16, wherein:
Described first operator scheme has first rated watt consumption; With
Described second operator scheme has second rated watt consumption, makes second rated watt consumption less than first rated watt consumption.
19. circuit as claimed in claim 16, wherein:
Described circuit has the 3rd operator scheme that wherein said circuit does not produce clock pulse output.
20. circuit as claimed in claim 19, wherein, described the 3rd operator scheme does not produce charging current of condenser.
21. circuit as claimed in claim 19, wherein, described the 3rd operator scheme has and approaches zero rated watt consumption.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/205,578 | 1998-12-04 | ||
| US09/205,758 US6052035A (en) | 1998-03-19 | 1998-12-04 | Oscillator with clock output inhibition control |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1296665A true CN1296665A (en) | 2001-05-23 |
Family
ID=22763532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99804764A Pending CN1296665A (en) | 1998-12-04 | 1999-12-06 | Precision relaxation oscillator with temperature compensation and various operating modes |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1053596A1 (en) |
| JP (1) | JP2003529227A (en) |
| KR (1) | KR20010040690A (en) |
| CN (1) | CN1296665A (en) |
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1999
- 1999-12-06 KR KR1020007008568A patent/KR20010040690A/en not_active Application Discontinuation
- 1999-12-06 EP EP99963026A patent/EP1053596A1/en not_active Withdrawn
- 1999-12-06 CN CN99804764A patent/CN1296665A/en active Pending
- 1999-12-06 JP JP2000588893A patent/JP2003529227A/en not_active Withdrawn
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| CN100348067C (en) * | 2004-09-02 | 2007-11-07 | 萨基姆通讯公司 | Mobile phone and method for using said mobile phone |
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| CN102356549A (en) * | 2009-03-18 | 2012-02-15 | Nxp股份有限公司 | Process, voltage, temperature compensated oscillator |
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| CN102024426B (en) * | 2009-09-14 | 2013-09-18 | 三星电机株式会社 | Reference signal generator and PWM control circuit for LCD backlight |
| CN102780470B (en) * | 2011-05-10 | 2015-06-24 | Nxp股份有限公司 | Oscillator architecture having fast response time with low current consumption and method for operating the oscillator architecture |
| CN102780470A (en) * | 2011-05-10 | 2012-11-14 | Nxp股份有限公司 | Oscillator architecture having fast response time with low current consumption and method for operating the oscillator architecture |
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| CN102820852A (en) * | 2011-06-09 | 2012-12-12 | 英飞凌科技奥地利有限公司 | Method for generating oscillating signal and oscillator circuit. |
| CN103580655B (en) * | 2012-07-24 | 2017-05-17 | 飞思卡尔半导体公司 | Comparator and relaxation oscillator with comparator |
| CN103580655A (en) * | 2012-07-24 | 2014-02-12 | 飞思卡尔半导体公司 | Comparator and relaxation oscillator with comparator |
| CN108832896B (en) * | 2018-06-25 | 2021-04-02 | 电子科技大学 | Off-chip adjustable relaxation type voltage-controlled oscillator circuit |
| CN108832896A (en) * | 2018-06-25 | 2018-11-16 | 电子科技大学 | A kind of outer adjustable tension and relaxation type voltage-controlled oscillator circuit |
| US11257529B2 (en) | 2018-09-17 | 2022-02-22 | Micron Technology, Inc. | Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay |
| CN112823477A (en) * | 2018-10-17 | 2021-05-18 | 美光科技公司 | Method and apparatus for temperature independent delay circuit |
| WO2020077558A1 (en) * | 2018-10-17 | 2020-04-23 | Micron Technology, Inc. | Methods and apparatuses for temperature independent delay circuitry |
| US11398815B2 (en) | 2018-10-17 | 2022-07-26 | Micron Technology, Inc. | Methods and apparatuses for temperature independent delay circuitry |
| US11929749B2 (en) | 2018-10-17 | 2024-03-12 | Micron Technology, Inc. | Methods and apparatuses for temperature independent delay circuitry |
| CN112823477B (en) * | 2018-10-17 | 2024-04-23 | 美光科技公司 | Method and apparatus for a temperature independent delay circuit |
| CN111147048A (en) * | 2018-11-06 | 2020-05-12 | 智原微电子(苏州)有限公司 | Relaxation oscillation circuit |
| CN111147048B (en) * | 2018-11-06 | 2023-08-18 | 智原微电子(苏州)有限公司 | Relaxation oscillation circuit |
| CN112835409A (en) * | 2019-11-25 | 2021-05-25 | 三星电子株式会社 | Bandgap reference voltage generating circuit |
| CN112835409B (en) * | 2019-11-25 | 2024-04-16 | 三星电子株式会社 | Band gap reference voltage generating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003529227A (en) | 2003-09-30 |
| EP1053596A1 (en) | 2000-11-22 |
| KR20010040690A (en) | 2001-05-15 |
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