CN112234957B - Analog oscillator circuit with negative feedback regulation function - Google Patents
Analog oscillator circuit with negative feedback regulation function Download PDFInfo
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- CN112234957B CN112234957B CN202011037014.2A CN202011037014A CN112234957B CN 112234957 B CN112234957 B CN 112234957B CN 202011037014 A CN202011037014 A CN 202011037014A CN 112234957 B CN112234957 B CN 112234957B
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- 230000009125 negative feedback regulation Effects 0.000 title claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 134
- 230000002035 prolonged effect Effects 0.000 claims abstract description 8
- 230000007423 decrease Effects 0.000 claims description 10
- 230000001276 controlling effect Effects 0.000 claims description 9
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 7
- 238000009966 trimming Methods 0.000 description 4
- 238000007599 discharging Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
An analog oscillator circuit with a negative feedback regulation function utilizes a clock generation module to generate a periodically-changed output clock signal, if the output clock signal is in a first state, the first charging current is controlled to charge a first capacitor and the second capacitor is controlled to discharge, when the voltage value on the first capacitor reaches a first threshold value, the output clock signal is turned over from the first state to a second state, the second charging current is controlled to charge the second capacitor and the first capacitor is controlled to discharge, and when the voltage value on the second capacitor reaches a second threshold value, the output clock signal is turned over from the second state to the first state; the negative feedback regulation module is used for generating a corresponding control signal according to the output clock signal, and when the period of the output clock signal is prolonged, the control signal controls the first charging current and the second charging current to be increased, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal is used for controlling the first charging current and the second charging current to be reduced, and the period of the output clock signal is prolonged.
Description
Technical Field
The invention belongs to the technical field of oscillators in analog integrated circuit designs, relates to an on-chip RC relaxation oscillator, and particularly relates to a relaxation oscillator circuit with a negative feedback regulation function.
Background
The relaxation oscillator generates periodic clock signals through charging and discharging the capacitor, and is influenced by different temperature characteristics of a circuit structure, a resistor, a capacitor and a MOS tube, process changes, voltage changes and the like, and the relaxation oscillator can generate different output frequencies to influence the precision, so that larger deviation is generated between the clock frequency generated by the relaxation oscillator and an ideal value.
In order to solve this problem, various methods for improving the precision of the relaxation oscillator are proposed in the prior art, such as the relaxation oscillator named as the chinese patent with the publication number CN105958943B, the bias current is divided into a plurality of trimming currents, and the capacitor is charged based on the trimming currents, but since trimming is performed independently, the frequency variation of the output clock of the relaxation oscillator cannot be accurately followed without combining with the variation of the output clock of the relaxation oscillator. In another chinese patent, called relaxation oscillator with frequency jitter function, with bulletin number CN103595244B, a set of logic signals is generated by logic control to adjust the capacitance value of the charging capacitor, so as to adjust the frequency of the output clock, and the same logic signals are generated independently and cannot follow the frequency variation of the output clock of the relaxation oscillator accurately. In China patent with patent name of adjustable high-precision relaxation oscillator and publication number CN103051286B, the frequency of the output clock is adjusted by adjusting the threshold level; and the patent name is an improved relaxation oscillator with low drift and local offset elimination, and the Chinese patent with the publication number of CN106062655B is provided with two adjustable current sources for supplementing two comparison points, but an additional design trimming structure is needed, and the circuit design is complex and the occupied area is large.
Disclosure of Invention
In order to solve the problems, the invention improves the traditional relaxation oscillator and introduces a negative feedback regulating module to generate a control signal which is used for controlling the charging current and is changed with the output clock signal, thereby obtaining a high-frequency output clock signal with better temperature characteristic and less influence of process change and voltage change.
The technical scheme of the invention is as follows:
an analog oscillator circuit with a negative feedback regulation function comprises a clock generation module and a negative feedback regulation module.
The clock generation module is used for generating an output clock signal of the analog oscillator circuit, and comprises a first capacitor and a second capacitor, if the output clock signal is in a first state, a first charging current is controlled to charge the first capacitor and simultaneously control the second capacitor to discharge, when the voltage value on the first capacitor reaches a first threshold value, the output clock signal is turned over from the first state to a second state, a second charging current is controlled to charge the second capacitor and simultaneously control the first capacitor to discharge, and when the voltage value on the second capacitor reaches a second threshold value, the output clock signal is turned over from the second state to the first state;
the negative feedback regulation module is used for generating a corresponding control signal according to the output clock signal, when the period of the output clock signal is prolonged, the control signal generated by the negative feedback regulation module is used for controlling the first charging current and the second charging current to be increased, and accelerating the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal generated by the negative feedback regulation module is used for controlling the first charging current and the second charging current to be reduced, and the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value are slowed down, so that the period of the output clock signal is prolonged.
Specifically, the clock generation module also comprises a first switch, a second switch, a first Schmitt trigger, a second Schmitt trigger, a first inverter, a second inverter and an SR trigger,
one end of the first capacitor is connected with the first charging current and the input end of the first Schmitt trigger and is grounded after passing through the first switch, and the other end of the first capacitor is grounded;
the input end of the first inverter is connected with the output end of the first Schmitt trigger, and the output end of the first inverter is connected with the S input end of the SR trigger;
one end of the second capacitor is connected with the second charging current and the input end of the second Schmitt trigger and is grounded after passing through a second switch, and the other end of the second capacitor is grounded;
the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger;
the output end of the SR trigger outputs the output clock signal, when the output clock signal is in a first state, the first switch is controlled to be turned off, and the second switch is controlled to be turned on, and when the output clock signal is in a second state, the first switch is controlled to be turned off.
Specifically, the clock generation module also comprises a first NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a first resistor,
the grid electrode of the first NMOS tube is connected with the control signal, the source electrode of the first NMOS tube is grounded after passing through the first resistor, and the drain electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube and the grid electrodes of the second PMOS tube and the third PMOS tube;
the drains of the second PMOS tube and the third PMOS tube respectively output the first charging current and the second charging current, and the sources of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a power supply voltage;
when the period of the output clock signal becomes longer, the voltage value of the control signal increases; when the period of the output clock signal becomes short, the voltage value of the control signal decreases.
Specifically, the negative feedback regulating module comprises a frequency divider, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a first current source, a second resistor, a fifth capacitor, a sixth capacitor and an amplifier,
the frequency divider divides the frequency of the output clock signal to generate a first clock signal, when the first clock signal is in a first state, the third switch and the sixth switch are controlled to be turned off, the fourth switch and the fifth switch are controlled to be turned on, and when the first clock signal is in a second state, the third switch and the sixth switch are controlled to be turned on, and the fourth switch and the fifth switch are controlled to be turned off;
one end of the third capacitor is connected with one end of the first current source and one end of the fifth switch and is grounded after passing through the third switch, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with one end of the second current source and one end of the sixth switch and is grounded after passing through the fourth switch, and the other end of the fourth capacitor is grounded;
one end of the second resistor is connected with the other end of the fifth switch and the other end of the sixth switch, and the other end of the second resistor is connected with the positive input end of the amplifier and is grounded after passing through the fifth capacitor;
the negative input end of the amplifier is connected with the reference voltage, and the output end of the amplifier outputs the control signal and is grounded after passing through the sixth capacitor.
Specifically, the first current source and the second current source are adjustable current sources.
Specifically, the reference voltage may be trimmed.
The beneficial effects of the invention are as follows: according to the invention, by introducing the negative feedback loop, the charging time of the capacitor for generating the output clock signal can be adjusted according to the change of the output clock signal, so that the output clock signal has better stability to the process change, the voltage change and the temperature change; some embodiments provide a tunable current source and reference voltage that improves the accuracy of the output clock signal clk_m.
Drawings
The following drawings, which schematically illustrate the principal features of some embodiments of the invention, assist in better understanding the following description of various embodiments of the invention. The figures and embodiments provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For simplicity, the same or similar components or structures having the same function in different drawings are given the same reference numerals.
Fig. 1 is a block diagram of an overall structure of an analog oscillator circuit with negative feedback regulation according to the present invention.
Fig. 2 is an internal structure diagram of a negative feedback adjustment module in an embodiment of an analog oscillator circuit with a negative feedback adjustment function according to the present invention.
Fig. 3 is an internal structure diagram of a clock generation module in an embodiment of an analog oscillator circuit with negative feedback regulation according to the present invention.
Fig. 4 is a waveform diagram of key nodes of the clock generation module in the analog oscillator circuit with negative feedback adjustment function according to the present invention when the clock generation module adopts the structure of fig. 3.
Fig. 5 is a schematic flow chart of a negative feedback adjusting module in an analog oscillator circuit with a negative feedback adjusting function according to the present invention.
Fig. 6 is an internal structure diagram of a negative feedback adjustment module in another embodiment of an analog oscillator circuit with a negative feedback adjustment function according to the present invention.
Fig. 7 is a diagram showing an internal implementation of an SR flip-flop and generating an output clock signal clk_m and its inverse in another embodiment of a clock generation module of an analog oscillator circuit with negative feedback regulation according to the present invention.
Fig. 8 is a waveform diagram of key nodes of the clock generation module in the analog oscillator circuit with negative feedback adjustment function according to the present invention when the clock generation module adopts the structure of fig. 7.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and specific embodiments. Specific details of the embodiments described below, such as specific circuit configurations and specific parameters of these circuit elements, are provided for a better understanding of embodiments of the invention. It will be understood by those skilled in the art that embodiments of the invention may be practiced without some of these specific details or with other methods, components, materials, etc.
Fig. 1 is a block diagram of an oscillator circuit according to the present invention, which includes a clock generating module and a negative feedback adjusting module, wherein the clock generating module is configured to generate an output clock signal clk_m of an analog oscillator circuit, and includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is charged by a first charging current I1, the second capacitor C2 is charged by a second charging current I2, and the first capacitor C1 and the second capacitor C2 switch charging and discharging according to a state of the output clock signal clk_m. For example, when the output clock signal clk_m is in the first state, the first charging current I1 is controlled to charge the first capacitor C1 and simultaneously control the second capacitor C2 to discharge, when the voltage value on the first capacitor C1 reaches the first threshold value, the output clock signal clk_m is turned from the first state to the second state, at this time, the second charging current I2 is controlled to charge the second capacitor C2 and simultaneously control the first capacitor C1 to discharge, and when the voltage value on the second capacitor C2 reaches the second threshold value, the output clock signal clk_m is turned from the second state back to the first state again, so that the circuit can generate the stable output clock signal clk_m after being stable. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. For example, the first state may be a high level, and the second state may be a low level, or the first state may be a low level, and the second state may be a high level.
As shown in fig. 3, a specific implementation form of a clock generation module is provided, in this embodiment, two schmitt triggers and SR triggers are used for logic control, and the clock generation module includes a first switch SW1, a second switch SW2, a first schmitt trigger, a second schmitt trigger, a first inverter, a second inverter and SR triggers, where the switching device of the present invention may be implemented by using MOS transistors or other controllable switching structures. One end of the first capacitor C1 is connected with the first charging current I1 and the input end of the first Schmitt trigger and is grounded after passing through the first switch SW1, and the other end of the first capacitor C is grounded; the input end of the first inverter is connected with the output end of the first Schmitt trigger, and the output end of the first inverter is connected with the S input end of the SR trigger; one end of the second capacitor C2 is connected with the second charging current I2 and the input end of the second Schmitt trigger and is grounded after passing through the second switch SW2, and the other end of the second capacitor C is grounded; the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger; the output end of the SR trigger outputs an output clock signal CLK_M, when the output clock signal CLK_M is in a first state, the first switch SW1 is controlled to be turned off so that the first charging current I1 charges the first capacitor C1, and meanwhile, the second switch SW2 is turned on to control the second capacitor C2 to discharge; when the output clock signal clk_m is in the second state, the first switch SW1 is controlled to be turned on so that the second charging current I2 charges the second capacitor C2, and the second switch SW2 is turned off to control the first capacitor C1 to be discharged. The working principle of the clock generation module is described below with reference to the key node waveform diagram in the clock generation module shown in fig. 4, in which the first state of the output clock signal clk_m is at a low level, the second state is at a high level, and the first switch SW1 is turned on by the high level, and the first switch SW1 is turned off by the low level. The control of the charge and discharge time of the first capacitor C1 and the second capacitor C2 is realized by controlling the on-off of the controlled switch, i.e., the first switch SW1 and the second switch SW2, by the output clock signal clk_m, so as to generate the periodically varying output clock signal clk_m.
When the output clock signal clk_m is at a low level, the inverted signal xclk_m of the output clock signal is at a high level, the output clock signal clk_m of the low level controls the first switch SW1 to be turned off, the inverted signal xclk_m of the output clock signal of the high level controls the second switch SW2 to be turned on, so that the first charging current I1 charges the first capacitor C1, the charge stored in the second capacitor C2 at the last moment is rapidly discharged to the ground through the second switch SW2, so that the R end of the SR flip-flop rapidly becomes at a low level, and the voltage VC1 on the first capacitor C1 is linearly increased due to the charging of the first capacitor C1 through the first charging current I1, before reaching the on threshold (i.e., the first threshold) of the first Schmitt flip-flop Schmitt1, the S end of the SR flip-flop will always be at a low level, in this way, after the S end of the SR flip-flop jumps from the high level to the low level, the R end of the SR flip-flop maintains the low level state at the last moment; after the voltage on the first capacitor C1 exceeds the on threshold of the first Schmitt trigger Schmitt1, the S terminal of the SR flip-flop jumps from low level to high level, so that the output clock signal clk_m output by the SR flip-flop quickly changes to high level and the inverted signal xclk_m of the output clock signal quickly changes to low level.
The high-level output clock signal clk_m controls the first switch SW1 to be turned on rapidly, the low-level output clock signal inverse signal xclk_m controls the second switch SW2 to be turned off rapidly, the second charging current I2 starts to charge the second capacitor C2, before the voltage VC2 on the second capacitor C2 rises to the on threshold (i.e., the second threshold) of the second Schmitt trigger Schmitt2, the R end of the SR trigger is always at a low level, and likewise, the S end of the SR trigger jumps from a high level to a low level immediately after the output clock signal clk_m is switched, and the output end of the SR trigger maintains the high-level state at the previous moment; after the voltage on the second capacitor C2 exceeds the on threshold of the second Schmitt trigger Schmitt2, the R terminal of the SR flip-flop jumps from low level to high level, so that the output clock signal clk_m output by the SR flip-flop quickly changes to low level, and the inverted signal xclk_m of the output clock signal quickly changes to high level, thus obtaining a stable output clock clk_m in a circulating manner.
In this embodiment, the flip threshold provided by the two Schmitt triggers Schmitt1 and Schmitt2 is used as a first threshold and a second threshold, and the thresholds are selected as important parameters for adjusting the frequency of the output clock signal, so that the specific threshold can be adjusted according to the clock requirement. The first charging current I1 and the second charging current I2 in the clock generation module can be obtained through current mirror images, as shown in fig. 3, the clock generation module further comprises a first NMOS tube M1, a first PMOS tube M2, a second PMOS tube M3, a third PMOS tube M4 and a first resistor R1, wherein the grid electrode of the first NMOS tube M1 is connected with a control signal, the source electrode of the first NMOS tube M1 is grounded after passing through the first resistor R1, and the drain electrode of the first NMOS tube M2 is connected with the grid electrode and the drain electrode of the first PMOS tube M2, and the grid electrodes of the second PMOS tube M3 and the third PMOS tube M4; the drains of the second PMOS tube M3 and the third PMOS tube M4 respectively output a first charging current I1 and a second charging current I2, and the sources of the first PMOS tube M2, the second PMOS tube M3 and the third PMOS tube M4 are connected with a power supply voltage VDD; the second PMOS tube M3 and the third PMOS tube M4 respectively form a current mirror with the first PMOS tube M2, and the mirrored current is used as a first charging current I1 and a second charging current I2.
The current values of the first charging current I1 and the second charging current I2 can be regulated by a negative feedback regulation module, the negative feedback regulation module generates corresponding control signals according to an output clock signal CLK_M, when the period of the output clock signal CLK_M is prolonged, the control signals generated by the negative feedback regulation module are used for controlling the first charging current I1 and the second charging current I2 to be increased, the time when the voltage value on the first capacitor C1 reaches a first threshold value and the time when the voltage value on the second capacitor C2 reaches a second threshold value are accelerated, and therefore the period of the output clock signal CLK_M is shortened; when the period of the output clock signal clk_m is shortened, the control signal generated by the negative feedback adjustment module is used for controlling the first charging current I1 and the second charging current I2 to be reduced, and slowing down the time when the voltage value on the first capacitor C1 reaches the first threshold value and the time when the voltage value on the second capacitor C2 reaches the second threshold value, so that the period of the output clock signal clk_m is prolonged, and the output clock signal clk_m is stabilized.
In comparison with the structure of fig. 3, the embodiment provides an internal structure diagram of the SR flip-flop and an internal implementation diagram for generating the output clock signal clk_m and its inversion signal, in this embodiment, the SR flip-flop is formed by two-input NOR gates NOR2, the output signal of the SR flip-flop is shaped by two inverters to obtain the output clock signal clk_m, and the inversion signal xclk_m of the output clock signal is obtained by one inverter. And unlike the structure shown in fig. 3, in this embodiment, the output clock signal clk_m is used to control the second switch SW2, the inverted signal xclk_m of the output clock signal is used to control the first switch SW1, and it should be clear to those skilled in the art that the specific implementation structure of the SR flip-flop and the switching control interchange of the output clock signal clk_m and the inverted signal thereof to the first switch SW1 and the second switch SW2 are all based on the design concept of the present invention, and are not used to limit the protection scope of the present invention.
The operation of the present embodiment is described below with reference to the waveform diagram shown in fig. 8, in which the SR flip-flop is formed by a nor gate, when the X point (i.e., the S input terminal of the SR flip-flop) is at a low level and the Y point (i.e., the R input terminal of the SR flip-flop) is at a high level, the inverted signal xclk_m of the output clock signal is at a low level, the first switch SW1 controlled by the inverted signal xclk_m of the output clock signal is turned off, the first charging current I1 charges the first capacitor C1, the second switch SW2 controlled by the output clock signal clk_m is turned on, the charge stored in the second capacitor C2 at the previous time is rapidly discharged to the ground through the second switch SW2, the Y-point potential is rapidly changed from a high level to a low level, at this time, I1 is still charging the first capacitor C1, the X-point potential is kept at a low level before the voltage VC1 on the first capacitor C1 reaches the high level threshold of the first schmitt trigger schmitt1, at this time, the output state of the SR trigger is kept unchanged, the inverted signal xclk_m of the output clock signal is still at a low level, the output clock signal clk_m is still at a high level, and after the voltage VC1 on the first capacitor C1 reaches the high level threshold of the first schmitt trigger schmitt1, the X-point potential is changed from a low level to a high level, so that the output state of the SR trigger is changed, the inverted signal xclk_m of the output clock signal is changed to a high level, and the output clock signal clk_m is at a low level. At this time, the first switch SW1 is turned on, the second switch SW2 is turned off, the charge on the first capacitor C1 is rapidly discharged to the ground through the first switch SW1, the X-point potential is rapidly changed from the high level to the low level, the second capacitor C2 starts to be charged through the second charging current I2, the Y-point potential is kept at the low level before reaching the high level threshold of the second Schmitt trigger Schmitt2, the output of the SR trigger is kept at the state of the last moment, the inverted signal xclk_m of the output clock signal is still at the high level, and the output clock signal clk_m is still at the low level; after the voltage VC2 on the second capacitor C2 reaches the high level threshold of the second Schmitt trigger Schmitt2, the Y-point potential changes from low level to high level, so that the output state of the SR trigger changes, the inverted signal xclk_m of the output clock signal changes to low level, the output clock signal clk_m changes to high level, the first switch SW1 is controlled to be turned off, the second switch SW2 is turned on, so that the first charging current I1 starts to charge the first capacitor C1, and the voltage on the second capacitor C2 at the last moment is rapidly discharged to the ground through the second switch SW2, the X-point potential remains low level, and the Y-point potential rapidly changes from high level to low level, so that the output clock signal clk_m of the required frequency is generated in a cyclic reciprocation. An implementation of the negative feedback adjustment module is shown in fig. 2, and includes a frequency divider div_p, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a third capacitor C3, a fourth capacitor C4, a first current source I3, a second current source I4, a second resistor R2, a fifth capacitor C5, a sixth capacitor C6, and an amplifier Amp, where the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are charge-discharge capacitors, the fifth capacitor C5 and the sixth capacitor C6 are energy storage capacitors, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6 are controlled switches, the first switch SW1 is controlled by an output clock signal clk_m, the second switch SW2 is controlled by an inverted signal xclk_m of the output clock signal, the third switch SW3 and the sixth switch SW6 are controlled by an inverted signal xclk_m of the fourth switch SW 4.
As shown in fig. 6, another implementation form of the negative feedback regulation module is shown, and compared with the structure of fig. 2, the invention adds a third resistor R3 at the output end of the amplifier Amp, and the third resistor R3 and a sixth capacitor C6 are used for RC filtering.
The frequency divider div_p divides the output clock signal clk_m to generate a first clock signal clk_n, when the first clock signal clk_n is in a first state, the third switch SW3 and the sixth switch SW6 are controlled to be turned off, the fourth switch SW4 and the fifth switch SW5 are controlled to be turned on, and when the first clock signal clk_n is in a second state, the third switch SW3 and the sixth switch SW6 are controlled to be turned on, and the fourth switch SW4 and the fifth switch SW5 are controlled to be turned off; one end of the third capacitor C3 is connected with one end of the first current source I3 and one end of the fifth switch SW5 and is grounded after passing through the third switch SW3, and the other end of the third capacitor C is grounded; one end of the fourth capacitor C4 is connected with one end of the second current source I4 and one end of the sixth switch SW6 and is grounded after passing through the fourth switch SW4, and the other end of the fourth capacitor C is grounded; one end of the second resistor R2 is connected with the other end of the fifth switch SW5 and the other end of the sixth switch SW6, and the other end of the second resistor R2 is connected with the positive input end of the amplifier Amp and is grounded after passing through the fifth capacitor C5; the negative input end of the amplifier Amp is connected with the reference voltage, and the output end of the amplifier Amp outputs a control signal and is grounded after passing through the sixth capacitor C6. It can be seen that as the period of the output clock signal clk_m becomes longer, the voltage value of the control signal increases, and the current values of the mirrored first charging current I1 and second charging current I2 also increase; when the period of the output clock signal clk_m becomes shorter, the voltage value of the control signal decreases, and the current values of the mirrored first charging current I1 and the second charging current I2 also decrease.
The following description will be made with reference to the control schematic diagram of the negative feedback adjustment module shown in fig. 5, in which the first clock signal clk_n is obtained after the output clock signal clk_m is divided by the frequency divider div_p, the frequency division multiple is P, xclk_n is the inverted signal of the first clock signal, and they have the same frequency and 180 ° phase difference, and the output clock signal clk_m and its inverted signal xclk_m have the same frequency and 180 ° phase difference. The first clock signal clk_n and the inverted signal xclk_n thereof control the on-off of the third switch SW3, the fourth switch SW4, the fifth switch SW5 and the sixth switch SW6, so that the change of the output clock signal clk_m is reflected to the point B (i.e. the positive input end of the amplifier Amp), the point B voltage (i.e. the voltage VC5 on the fifth capacitor in fig. 5) and the reference voltage VREF are operated by the amplifier Amp to generate a control signal for controlling the gate voltage of the first NMOS tube M1, and further, the change of the output clock signal clk_m is fed back to the first charging current I1 and the second charging current I2, and the magnitudes of the first charging current I1 and the second charging current I2 are adjusted, so that the adjustment of the frequency of the output clock signal clk_m is realized.
Specifically, when the output clock signal clk_m is affected and the period becomes longer, the periods of the divided first clock signal clk_n and the inverted signal xclk_n thereof become longer, the charging time of the third capacitor C3 and the fourth capacitor C4 becomes longer, the average value of the voltage VC5 at the point B becomes larger, exceeding the reference voltage VREF, a level VC6 higher than the last time is obtained at the output terminal C of the amplifier, that is, the gate voltage vgate_m1 of the first NMOS transistor M1 increases, and since the first NMOS transistor M1 is a voltage controlled device whose drain current increases with the increase of the gate voltage, the current flowing through the first NMOS transistor M1 increases when the voltage at the point C increases, the current flowing through the first NMOS transistor M1 synchronously increases by the current mirror formed by the first PMOS transistor M2 and the second PMOS transistor M3, and the second charging current I2 synchronously increases by the current mirror formed by the first PMOS transistor M2 and the third PMOS transistor M4, so that the current flowing through the first NMOS transistor M1 and the second NMOS transistor M2 correspondingly becomes shorter when the voltage at the point C increases, and the charging current of the second NMOS transistor M2 becomes shorter, and the charging threshold signal CLK is triggered when the charging time of the output clock signal CLK becomes shorter.
Similarly, when the output clock signal clk_m is affected, the period becomes shorter, and the periods of the divided clock first clock signal clk_n and the inverted signal xclk_n thereof become shorter, so that the charging time of the third capacitor C3 and the fourth capacitor C4 becomes shorter, the average value of the voltage VC5 at the point B becomes smaller than the reference voltage VREF, a level VC6 lower than the last time is obtained at the output terminal C of the amplifier Amp, that is, the gate voltage vgate_m1 of the first NMOS transistor M1 is reduced, and since the first NMOS transistor M1 is a voltage-controlled device, the drain current decreases with the decrease of the gate voltage, when the voltage at the point C is reduced, the current flowing through the first NMOS transistor M1 decreases, and the current flowing through the first NMOS transistor M1 respectively passes through the current mirror formed by the first PMOS transistor M2 and the second PMOS transistor M3, and the first charging current I1 and the second charging current I2 obtained by the current mirror copy of the first PMOS transistor M2 and the third PMOS transistor M4 are also reduced at the output terminal C point C of the amplifier Amp, so that the drain current decreases with the decrease of the first NMOS transistor M1, and the current flowing through the first NMOS transistor M1 decreases, and the current mirror current becomes longer than the first PMOS transistor M4, and the current is equal to the current, and the current c_c_current becomes longer, and the current is the current when the first NMOS transistor M is turned on, and the current is the current and the third PMOS current 4, and the current is turned on.
In addition, in order to increase the precision, in some embodiments, the first current source I3 and the second current source I4 may be set as tunable current sources, the reference voltage VREF may also be set as tunable voltage, and the tuning manner may be selected and combined arbitrarily, so that the precision of the output clock signal clk_m is improved according to the actual situation.
The clock has poor stability to temperature, process and power supply voltage, which can cause low precision and continuous change of the clock, and the changed clock brings a plurality of problems to a later-stage circuit, so that a clock with high precision and good stability to temperature, power supply voltage and process is necessary to design.
The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention, and the various changes are included in the scope of the present invention. Various modifications and variations of the present invention, such as obtaining the output clock signal by charging the capacitor with the charging current using other structures, or generating the control signal varying with the variation of the output clock signal using other structures, may be made by those skilled in the art, and it is intended that the present invention also includes such modifications and variations without departing from the spirit of the present invention and the scope of the appended claims and their equivalents.
Claims (4)
1. An analog oscillator circuit with a negative feedback regulation function is characterized by comprising a clock generation module and a negative feedback regulation module,
the clock generation module is used for generating an output clock signal of the analog oscillator circuit, and comprises a first capacitor and a second capacitor, if the output clock signal is in a first state, a first charging current is controlled to charge the first capacitor and simultaneously control the second capacitor to discharge, when the voltage value on the first capacitor reaches a first threshold value, the output clock signal is turned over from the first state to a second state, a second charging current is controlled to charge the second capacitor and simultaneously control the first capacitor to discharge, and when the voltage value on the second capacitor reaches a second threshold value, the output clock signal is turned over from the second state to the first state;
the negative feedback regulation module is used for generating a corresponding control signal according to the output clock signal, when the period of the output clock signal is prolonged, the control signal generated by the negative feedback regulation module is used for controlling the first charging current and the second charging current to be increased, and accelerating the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal generated by the negative feedback regulation module is used for controlling the first charging current and the second charging current to be reduced, and the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value are slowed down, so that the period of the output clock signal is prolonged;
the clock generation module further comprises a first switch, a second switch, a first schmitt trigger, a second schmitt trigger, a first inverter, a second inverter and an SR trigger,
one end of the first capacitor is connected with the first charging current and the input end of the first Schmitt trigger and is grounded after passing through the first switch, and the other end of the first capacitor is grounded;
the input end of the first inverter is connected with the output end of the first Schmitt trigger, and the output end of the first inverter is connected with the S input end of the SR trigger;
one end of the second capacitor is connected with the second charging current and the input end of the second Schmitt trigger and is grounded after passing through a second switch, and the other end of the second capacitor is grounded;
the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger;
the output end of the SR trigger outputs the output clock signal, when the output clock signal is in a first state, the first switch is controlled to be turned off, and the second switch is controlled to be turned on, and when the output clock signal is in a second state, the first switch is controlled to be turned off;
the clock generating module also comprises a first NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a first resistor,
the grid electrode of the first NMOS tube is connected with the control signal, the source electrode of the first NMOS tube is grounded after passing through the first resistor, and the drain electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube and the grid electrodes of the second PMOS tube and the third PMOS tube;
the drains of the second PMOS tube and the third PMOS tube respectively output the first charging current and the second charging current, and the sources of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a power supply voltage;
when the period of the output clock signal becomes longer, the voltage value of the control signal increases; when the period of the output clock signal becomes short, the voltage value of the control signal decreases;
the negative feedback regulating module comprises a frequency divider, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a first current source, a second resistor, a fifth capacitor, a sixth capacitor and an amplifier,
the frequency divider divides the frequency of the output clock signal to generate a first clock signal, when the first clock signal is in a first state, the third switch and the sixth switch are controlled to be turned off, the fourth switch and the fifth switch are controlled to be turned on, and when the first clock signal is in a second state, the third switch and the sixth switch are controlled to be turned on, and the fourth switch and the fifth switch are controlled to be turned off;
one end of the third capacitor is connected with one end of the first current source and one end of the fifth switch and is grounded after passing through the third switch, and the other end of the third capacitor is grounded;
one end of the fourth capacitor is connected with one end of the second current source and one end of the sixth switch and is grounded after passing through the fourth switch, and the other end of the fourth capacitor is grounded;
one end of the second resistor is connected with the other end of the fifth switch and the other end of the sixth switch, and the other end of the second resistor is connected with the positive input end of the amplifier and is grounded after passing through the fifth capacitor;
the negative input end of the amplifier is connected with the reference voltage, and the output end of the amplifier outputs the control signal and is grounded after passing through the sixth capacitor.
2. The analog oscillator circuit with negative feedback regulation function according to claim 1, wherein the negative feedback regulation module further comprises a third resistor, the third resistor is connected between the output terminal of the amplifier and the sixth capacitor, and a connection point of the third resistor and the sixth capacitor outputs the control signal.
3. The analog oscillator circuit with negative feedback regulation function according to claim 1 or2, wherein the first and second current sources are trimmable current sources.
4. An analog oscillator circuit with negative feedback regulation according to claim 1 or2, characterized in that the reference voltage is trimmable.
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| CN113162586B (en) * | 2021-04-16 | 2024-02-13 | 南京大学 | Clock duty cycle trimming method and system |
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| CN113676159B (en) * | 2021-08-25 | 2022-07-05 | 微龛(广州)半导体有限公司 | Oscillator, chip and electronic equipment |
| CN114279595B (en) * | 2021-12-28 | 2022-09-27 | 中国科学院半导体研究所 | Temperature sensing circuit, CMOS temperature sensor based on temperature sensing circuit and calibration method thereof |
| CN114280464B (en) * | 2022-01-04 | 2023-10-13 | 上海南芯半导体科技股份有限公司 | Test circuit for PAD test point |
| CN115296651B (en) * | 2022-10-09 | 2023-04-18 | 深圳英集芯科技股份有限公司 | Voltage-controlled frequency circuit and related product |
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