CN217135466U - Oscillator circuit and chip - Google Patents
Oscillator circuit and chip Download PDFInfo
- Publication number
- CN217135466U CN217135466U CN202220649455.6U CN202220649455U CN217135466U CN 217135466 U CN217135466 U CN 217135466U CN 202220649455 U CN202220649455 U CN 202220649455U CN 217135466 U CN217135466 U CN 217135466U
- Authority
- CN
- China
- Prior art keywords
- circuit
- switch
- comparator
- switching tube
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses oscillator circuit and chip relates to integrated circuit technical field. The oscillator circuit comprises an oscillation resistor, an oscillation capacitor, a first switching tube circuit, a second switching tube circuit, a comparator, a charging and discharging circuit and a control circuit, wherein the first switching tube circuit comprises a plurality of first switching tubes which are connected in parallel, and the second switching tube circuit comprises at least one second switching tube; the first input end of the comparator is connected with the first end of the oscillating resistor through a first switching tube circuit, the second input end of the comparator is connected with the first end of the oscillating capacitor through a second switching tube circuit, and the output end of the comparator is used for outputting a clock signal; the charge and discharge circuit is connected with the oscillation capacitor and is used for charging and discharging the oscillation capacitor; the control circuit is connected with the output end of the comparator and the charging and discharging circuit and is used for controlling the charging and discharging circuit to charge and discharge the oscillating capacitor according to the clock signal. The method and the device aim at reducing the temperature drift influence of the clock in the chip and improving the precision of the clock signal in the chip.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to an oscillator circuit and a chip.
Background
In an integrated circuit, a clock signal is typically generated by an oscillator. The relaxation oscillator is the most commonly used oscillator, and outputs an oscillation signal by charging and discharging a capacitor, and the frequency of the oscillation signal can be adjusted by adjusting the charging and discharging current or the size of the capacitor. Therefore, relaxation oscillators are widely used and studied because of their low power consumption, easily controllable frequency, and simple structure.
The existing bandgap reference circuit is generally adopted to generate bias current or bias voltage to the relaxation oscillator to suppress temperature drift, and the scheme has the defects that the dependence on the bandgap reference circuit is high, the relaxation oscillator is influenced by other common bandgap reference circuits at the same time, and the cost for independently designing the bandgap reference circuit for the relaxation oscillator is too high.
SUMMERY OF THE UTILITY MODEL
The application provides an oscillator circuit and a chip, which aim to reduce the temperature drift influence of an on-chip clock and improve the precision of an on-chip clock signal.
In order to achieve the above object, the present application provides an oscillator circuit, where the oscillator circuit includes an oscillation resistor, an oscillation capacitor, a first switching tube circuit, a second switching tube circuit, a comparator, a charging and discharging circuit, and a control circuit, where a first end of the oscillation resistor is connected to a preset power voltage, and a second end of the oscillation resistor is grounded; the first end of the oscillation capacitor is connected with the preset power supply voltage, and the second end of the oscillation capacitor is grounded; the first switching tube circuit comprises a plurality of first switching tubes connected in parallel, and the second switching tube circuit comprises at least one second switching tube; a first input end of the comparator is connected with a first end of the oscillating resistor through the first switching tube circuit, a second input end of the comparator is connected with a first end of the oscillating capacitor through the second switching tube circuit, and an output end of the comparator is used for outputting a clock signal; the charging and discharging circuit is connected with the oscillating capacitor and is used for charging and discharging the oscillating capacitor; the control circuit is connected with the output end of the comparator and the charging and discharging circuit and is used for controlling the charging and discharging circuit to charge and discharge the oscillating capacitor according to the clock signal.
In addition, in order to achieve the above object, the present application also provides a chip including the oscillator circuit as described above, the oscillator circuit being configured to provide a clock signal to a clock using circuit in the chip.
In the oscillator circuit and the chip, the first end of the oscillating resistor is connected with a preset power voltage, and the second end of the oscillating resistor is grounded; the first end of the oscillation capacitor is connected with the preset power supply voltage, and the second end of the oscillation capacitor is grounded; the first switching tube circuit comprises a plurality of first switching tubes connected in parallel, and the second switching tube circuit comprises at least one second switching tube; a first input end of the comparator is connected with a first end of the oscillating resistor through the first switching tube circuit, a second input end of the comparator is connected with a first end of the oscillating capacitor through the second switching tube circuit, and an output end of the comparator is used for outputting a clock signal; the charging and discharging circuit is connected with the oscillating capacitor and is used for charging and discharging the oscillating capacitor; the control circuit is connected with the output end of the comparator and the charging and discharging circuit and is used for controlling the charging and discharging circuit to charge and discharge the oscillating capacitor according to the clock signal. Therefore, the number of the first switching tubes connected into the first switching tube circuit can be controlled, so that the current difference input by the first input end and the second input end of the comparator is zero temperature characteristic, the temperature drift influence of the clock in the chip is reduced, the precision of the clock signal in the chip is improved, and the clock period can be kept unchanged.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a structure of an oscillator circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an oscillator circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another oscillator circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another oscillator circuit provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of another oscillator circuit provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of another oscillator circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of another oscillator circuit provided in an embodiment of the present application.
Description of the main elements and symbols:
100. an oscillator circuit;
10. an oscillation resistor;
20. an oscillation capacitor;
30. a first switching tube circuit; 31. a first switch tube; 32. a first switch;
40. a second switching tube circuit; 41. a second switching tube;
50. a comparator;
60. a charge and discharge circuit; 61. a second switch; 62. a third switch;
70. a control circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
In an integrated circuit, the clock signal is typically generated by an oscillator. Along with the change of the environmental temperature, because the oscillation resistor and the oscillation capacitor are affected by the temperature, for example, the higher the temperature is, the resistance value of the oscillation resistor is reduced, and the capacitance value of the oscillation capacitor is increased, thereby causing the frequency deviation of the system clock of the chip, so that the precision of the clock signal in the chip is lower, and the stable clock signal cannot be output.
The existing crystal oscillator circuit is mostly adopted to inhibit temperature drift, and has great advantages, but because the crystal oscillator circuit is an external clock source circuit, the crystal oscillator circuit cannot be well integrated in a chip, and the crystal cost can be increased during product design, the scheme cannot meet the requirements of an integrated circuit and the cost.
For an on-chip clock circuit, a bandgap reference circuit is generally adopted to generate a bias current or a bias voltage to a relaxation oscillator to suppress temperature drift, and the scheme has the defects that the dependence on the bandgap reference circuit is high, the relaxation oscillator is simultaneously influenced by other common bandgap reference circuits, and the cost for independently designing the bandgap reference circuit for the relaxation oscillator is too high.
Therefore, it is desirable to design an oscillator circuit with low cost, so as to reduce the temperature drift of the on-chip clock, improve the accuracy of the on-chip clock signal, and keep the clock period unchanged.
The embodiment of the invention provides an oscillator circuit and a chip. The oscillator circuit can be applied to a chip, so that the temperature drift influence of an on-chip clock is reduced, the precision of an on-chip clock signal is improved, and the clock period can be kept unchanged.
Referring to fig. 1 and 2, as shown in fig. 1, the oscillator circuit 100 includes an oscillating resistor 10, an oscillating capacitor 20, a first switching tube circuit 30, a second switching tube circuit 40, a comparator 50, a charging/discharging circuit 60, and a control circuit 70. As shown in fig. 2, a first end of the oscillating resistor 10 is connected to a predetermined power voltage, and a second end of the oscillating resistor 10 is grounded; a first terminal of the oscillating capacitor 20 is connected to a predetermined power voltage, and a second terminal of the oscillating capacitor 20 is grounded. Since the oscillator circuit 100 is applied to the inside of the chip, the preset power voltage is an operating voltage inside the chip, and may be 3.3V. The first switch tube circuit 30 includes a plurality of first switch tubes 31 connected in parallel, and the second switch tube circuit 40 includes at least one second switch tube 41, it is understood that the first switch tube circuit 30 may include a plurality of first switch tubes 31 connected in parallel, and the second switch tube circuit 40 may also include a plurality of second switch tubes 41 connected in parallel, but generally speaking, the second switch tube circuit 40 may be provided with one second switch tube 41 for cost saving.
A first input terminal of the comparator 50 is connected to the first terminal of the oscillating resistor 10 through the first switching tube circuit 30, a second input terminal of the comparator 50 is connected to the first terminal of the oscillating capacitor 20 through the second switching tube circuit 40, and an output terminal of the comparator 50 is configured to output a clock signal, wherein the comparator 50 may be a current comparator or a voltage comparator, and is configured to compare currents or voltages received by the first input terminal and the second input terminal, so as to output the clock signal carrying the comparison result. The charge and discharge circuit 60 is connected to the oscillation capacitor 20, and is configured to charge and discharge the oscillation capacitor 20; the control circuit 70 is connected to the output terminal of the comparator 50 and the charging and discharging circuit 60, and is configured to control the charging and discharging circuit 60 to charge and discharge the oscillation capacitor 20 according to the clock signal.
The control circuit 70 may be a control Unit such as a Microcontroller Unit (MCU), and is generally selected to be a control Unit that can be integrated in a chip, and is not limited herein.
For example, as shown in fig. 2, the operation principle of the oscillator circuit 100 will be described by taking the first switching transistor 31 and the second switching transistor 41 as MOS transistors as an example. First, when a reference current passes through the oscillation resistor 10, a plurality of first MOS transistors connected in parallel in the first MOS transistor circuit generate corresponding gate voltages at their gates, which can be obtained according to the MOS device characteristics:
wherein, I 2 Is the drain current of the first MOS transistor, U n Cox is the gate oxide capacitance per unit area, which is the electron mobility,
to the oxide width-to-length ratio, vdd is the preset power supply voltage, I 0 Is a reference current value, R is a resistance value of the oscillation resistor 10, I 0 R is the grid voltage of the first MOS tube, V th_p Is the threshold voltage.
Meanwhile, the reference current charges the capacitor, and a corresponding gate voltage is generated at the gate of the second MOS transistor in the second MOS transistor circuit and can be obtained according to the characteristics of the MOS transistor device,
wherein, I 3 Is the drain current of the second MOS transistor, I 1 C is a capacitance value of the oscillation capacitor 20,
is the gate voltage of the second MOS transistor, t 1 Is the charging time.
In the oscillation process of the oscillator, the drain current of the first MOS transistor and the drain current of the second MOS transistor are respectively input to the comparator 50 through the first input end and the second input end of the comparator 50, the comparator 50 compares the drain current of the first MOS transistor and the drain current of the second MOS transistor, outputs a clock signal carrying a current comparison result at an output end, and sends the clock signal to the control circuit 70, so that the control circuit 70 controls the charge and discharge circuit 60 to charge and discharge the oscillation capacitor 20 according to the current comparison result carried by the clock signal.
Specifically, when the drain current of the first MOS transistor is greater than the drain current of the second MOS transistor, the comparator 50 inverts to output 0, and the control circuit 70 controls the charge/discharge circuit 60 to discharge the oscillation capacitor 20, while during the discharge process, the drain current of the first MOS transistor is smaller than the drain current of the second MOS transistor, the comparator 50 outputs 1, the discharge of the oscillation capacitor 20 is completed rapidly, and the oscillation capacitor 20 starts to charge. Because of the delay in the circuit, the capacitor will still be in the discharge state when the discharge of the oscillation capacitor 20 is completed, but the delay time is much shorter than the charge time, so that the delay time can be ignored, and the oscillation period (i.e. clock period) can be equivalent to t 1 。
Since the resistor R and the capacitor C are non-ideal devices, it is assumed that the resistance of the oscillating resistor 10 decreases by Δ R when the ambient temperature rises, which can be obtained from the characteristics of the MOS device,
it can be seen that since the resistance of the oscillating resistor 10 is reduced by Δ R, I 2 Become larger, assume I 3 Still keeps the normal temperature state because of I 2 When the voltage increases, the comparator 50 flips earlier and the clock period T decreases, so that Δ I2- Δ I3 have positive temperature characteristics.
When the ambient temperature rises, the capacitance value of the oscillation capacitor 20 is increased by the temperature, and if the capacitance value of the oscillation capacitor 20 is increased by Δ C, it can be obtained from the MOS device characteristics,
it can be seen that since the capacitance of the oscillation capacitor 20 is reduced by Δ C, I 3 Become larger, assume I 2 Still keeps the normal temperature state because of I 3 When the output voltage increases, the comparator 50 is turned over for a delay, and the clock period increases, where Δ I 2 -△I 3 Is a negative temperature characteristic.
It is due to Delta I 2 -△I 3 There may be a positive or negative temperature characteristic resulting in inaccurate clock cycles. In the present application, the temperature drift of the oscillating resistor 10 and the oscillating capacitor 20 is compensated by setting the switching tube threshold value influenced by the temperature, and if the oscillating capacitor 20 and the oscillating resistor 10 are not influenced by the temperature, the first switching tube circuit 30 and the second switching tube circuit 40 have a ratio n, I 2 And I 3 The relationship with temperature change is:
where n may be the number of the first switch tubes 31 connected in parallel in the first switch tube circuit 30.
In general, in practical cases, Δ I 2 -△I 3 Will exhibit a negative temperature characteristic, i.e. Δ I 2 <△I 3 Therefore, by increasing the number of the first switch tubes 31 connected in parallel in the first switch tube circuit 30, the width (i.e. W) of the oxide layer can be increased, thereby increasing I 2 Is enlarged to compensate for DeltaI 2 -△I 3 So that the negative temperature characteristic caused by the temperature change can be offset, and by setting a proper value of n, the mutual offset of the positive temperature characteristic and the negative temperature characteristic can be realized, and when the current difference input at the two ends of the comparator 50 is the zero temperature characteristic, the temperature drift influence of the on-chip clock can be reduced, the precision of the on-chip clock signal can be improved, and the clock period can be kept unchanged.
The n value is actually the ratio of the number of the first switching tubes connected to the first switching tube circuit to the number of the second switching tubes connected to the second switching tube circuit. For example, if the value of n is 3, the first switching tube circuit includes 3 first switching tubes connected in parallel, and the second switching tube circuit includes 1 second switching tube. And the quantity of the second switch tubes can also be a plurality of, if the width (W) of the oxide layer of the second switch tube is smaller than the width (W) of the oxide layer of the first switch tube, the effect of mutual offset of the positive temperature characteristic and the negative temperature characteristic can be realized by setting the ratio of the quantity of the first switch tubes connected into the first switch tube circuit to the quantity of the second switch tubes connected into the second switch tube circuit, so that the temperature drift influence of the clock in the chip can be reduced, the precision of the clock signal in the chip is improved, and the clock period is kept unchanged.
It should be noted that, specifically, a computer simulation may be used in advance to test curves of frequency drifts with temperature of different n values at different environmental temperatures, and the n value corresponding to the minimum difference between the maximum temperature and the minimum temperature frequency is used as the optimal n value; and testing curves of frequency drifts of different n values along with the temperature by an experimental test method at different environmental temperatures, and taking the n value corresponding to the minimum difference between the maximum temperature and the minimum temperature frequency as the optimal n value.
In some embodiments, as shown in fig. 3, the first switch tube circuit 30 further includes a plurality of first switches 32, each first switch 32 is disposed between every two first switch tubes 31 at intervals; the control circuit 70 is connected to each first switch 32, and is configured to control on/off of each first switch 32. Therefore, the access quantity of the first switch tube 31 in the first switch tube circuit 30 can be quickly controlled by controlling the first switch 32, which is very convenient and convenient, and is convenient for subsequent regulation and control according to different application environments.
The first switch tube circuit 30 further includes a plurality of first switches 32, and since the oscillator circuit 100 is generally integrated in a chip, a MOS transistor can be used as the first switch 32, and at this time, the MOS transistor plays a role of a switch, so that the oscillator circuit can be well integrated in a chip.
Specifically, the first switches 32 may be disposed between every two first switch tubes 31 at intervals, wherein the gates of each first switch tube 31 are communicated with each other, the first switches 32 may be disposed on the path between the gates of every two first switch tubes 31, and the control circuit 70 is connected to the first switches 32 for controlling the on/off of the first switches 32, so as to control the access number of the first switch tubes 31 in the first switch tube circuit 30 according to the n value determined in advance.
For example, as shown in fig. 4, for example, if the predetermined n value is 3, the number of the first switch tubes 31 connected to the first switch tubes may be controlled to be 3, and since each first switch 32 is arranged between every two first switch tubes 31 at intervals, the first two first switches 32 may be controlled to be closed by the control circuit 70, and the second first switch 32 may be controlled to be opened.
In some embodiments, each first switch tube 31 may be provided with a corresponding first switch 32, and the control circuit 70 is connected to each first switch 32 for controlling on/off of each first switch 32, so as to control the access number of the first switch tubes 31 in the first switch tube circuit 30 according to a predetermined n value.
For example, as shown in fig. 5, for example, if the predetermined n value is 2, the number of the first switch tubes 31 connected to the first switch tubes 31 may be controlled to be 2, and since each first switch tube 31 is correspondingly provided with a first switch 32, the first two first switches 32 may be controlled to be closed by the control circuit 70, and the second first switch 32 may be controlled to be opened.
In some embodiments, the first switch tube 31 and the second switch tube 41 may be MOS tubes or triodes. And the MOS tube and the triode can be well integrated in the chip.
As described in the foregoing analysis, if the first switch tube 31 and the second switch tube 41 are MOS tubes, the comparator 50 compares the drain current of the first MOS tube with the drain current of the second MOS tube, so that the control circuit 70 controls the charge/discharge circuit 60 to charge/discharge the oscillation capacitor 20 according to the current comparison result carried by the clock signal output by the comparator 50.
The source electrode, the grid electrode and the drain electrode of the MOS tube respectively correspond to the emitter electrode, the base electrode and the collector electrode c of the triode, and the functions of the source electrode, the grid electrode and the drain electrode are similar. Therefore, if the first switch tube 31 and the second switch tube 41 are triodes, the comparator 50 compares the collector current of the first triode with the collector current of the second triode, so that the control circuit 70 controls the charging and discharging circuit 60 to charge and discharge the oscillating capacitor 20 according to the current comparison result carried by the clock signal output by the comparator 50. Similar to the analysis of the MOS transistor, the negative temperature characteristic caused by the temperature change can be offset by increasing the number of the first triodes connected in parallel in the first triode circuit, and thus the positive temperature characteristic and the negative temperature characteristic can be offset by setting an appropriate n value.
In some embodiments, the first switch tube 31 and the second switch tube 41 are of the same type. Therefore, the threshold voltages of the first switch tube 31 and the second switch tube 41 are the same, and the temperature influence of the first switch tube 31 and the second switch tube 41 is the same.
For example, if the first switch tube 31 is a MOS tube, the second switch tube 41 is also a MOS tube; if the first switch tube 31 is a triode, the second switch tube 41 is also a triode. The parameters of the first switch tube 31 and the second switch tube 41 are also the same.
In some embodiments, the gate of each first MOS transistor is connected to the first terminal of the oscillating resistor 10, the drain of each first MOS transistor is connected to the first input terminal of the comparator 50, and the source of each first MOS transistor is connected to the predetermined power supply voltage. Therefore, the negative temperature characteristic caused by temperature change can be counteracted by connecting a plurality of first MOS tubes in parallel.
Specifically, the reference current passes through the oscillating resistor 10, and a corresponding gate voltage is generated at each of the gates of a plurality of first MOS transistors connected in parallel in the first MOS transistor circuit, so as to generate a drain current of the first MOS transistor, and the drain current of the first MOS transistor is transmitted to the first input terminal of the comparator 50.
It should be noted that, if the type of the first MOS transistor is a PMOS transistor, a gate of each first MOS transistor is connected to the first end of the oscillating resistor 10, a drain of each first MOS transistor is connected to the first input end of the comparator 50, and a source of each first MOS transistor is connected to a preset power supply voltage; correspondingly, if the first MOS transistors are NMOS transistors, the gate of each first MOS transistor is connected to the first end of the oscillating resistor 10, the drain of each first MOS transistor is connected to the first input end of the comparator 50, and the source of each first MOS transistor is grounded.
In some embodiments, as shown in fig. 6, a gate of the second MOS transistor is connected to the first end of the oscillation capacitor 20, a drain of the second MOS transistor is connected to the second input terminal of the comparator 50, and a source of the second MOS transistor is connected to the predetermined power voltage.
Specifically, the reference current charges the capacitor, and generates a corresponding gate voltage at the gate of the second MOS transistor in the second MOS transistor circuit, so as to generate a drain current of the second MOS transistor, and the drain current of the second MOS transistor is supplied to the second input terminal of the comparator 50.
It should be noted that, if the type of the second MOS transistor is a PMOS transistor, a gate of the second MOS transistor is connected to the first end of the oscillation capacitor 20, a drain of the second MOS transistor is connected to the second input end of the comparator 50, and a source of the second MOS transistor is connected to the preset power voltage; correspondingly, if the type of the second MOS transistor is an NMOS transistor, the gate of the second MOS transistor is connected to the first end of the oscillation capacitor 20, the drain of the second MOS transistor is connected to the second input end of the comparator 50, and the source of the second MOS transistor is grounded.
Illustratively, the first input of the comparator 50 may be a non-inverting input, and the second input of the comparator 50 may be an inverting input. At this time, if the drain current of the second MOS transistor is greater than the drain current of the first MOS transistor, the output terminal of the comparator 50 outputs a high level, and if the drain current of the second MOS transistor is less than the drain current of the first MOS transistor, the output terminal of the comparator 50 outputs a low level.
Illustratively, the first input of the comparator 50 may be an inverting input, and the second input of the comparator 50 may be a non-inverting input. At this time, if the drain current of the second MOS transistor is greater than the drain current of the first MOS transistor, the output terminal of the comparator 50 outputs a low level, and if the drain current of the second MOS transistor is less than the drain current of the first MOS transistor, the output terminal of the comparator 50 outputs a high level.
In some embodiments, as shown in fig. 7, the charging and discharging circuit 60 includes a second switch 61 and a third switch 62, a first terminal of the second switch 61 is connected to the preset power voltage, and a second terminal of the second switch 61 is connected to a first terminal of the third switch 62; a second terminal of the third switch 62 is connected to ground.
Since the oscillator circuit 100 is generally integrated in a chip, MOS transistors may be used as the second switch 61 and the third switch 62, and at this time, the MOS transistors function as switches, so that the oscillator circuit 100 can be well integrated in a chip.
Specifically, when the drain current of the first MOS transistor is greater than the drain current of the second MOS transistor, the comparator 50 inverts and outputs 0, the control circuit 70 controls the second switch 61 to be open, the third switch 62 is closed, and the charge and discharge circuit 60 discharges the oscillation capacitor 20 at this time; when the drain current of the first MOS transistor is smaller than the drain current of the second MOS transistor, the comparator 50 outputs 1, the control circuit 70 controls the second switch 61 to be closed, the third switch 62 to be opened, and the charging and discharging circuit 60 charges the oscillation capacitor 20, so that a complete cycle is achieved.
In some embodiments, oscillator circuit 100 is integrated within a chip. By integrating the oscillator circuit 100 in a chip, on one hand, the use of external clock sources such as a crystal oscillator can be avoided, and the crystal cost does not need to be increased; on the other hand, the oscillator circuit 100 provided by the application can solve the problem that the on-chip clock low-temperature drift technology depends on a band-gap reference circuit.
The oscillator circuit 100 provided by the application does not need to design a dedicated band-gap reference circuit independently, thereby reducing the area overhead of a chip, saving the use space and the manufacturing cost, simultaneously avoiding the interference of non-ideal factors of other modules to a clock circuit, reducing the temperature drift influence of an on-chip clock, improving the precision of a clock signal in the chip, and keeping the clock period unchanged.
In some embodiments, the first terminal of the oscillating resistor 10 is connected to the predetermined power voltage via a first current source, and the first terminal of the second switch 61 is connected to the predetermined power voltage via a second current source.
The first current source is used for providing reference current for the oscillation resistor 10, the second current source is used for providing reference current for the oscillation capacitor 20, and the current values of the reference current provided by the first current source and the reference current provided by the second current source are the same.
In some embodiments, the present application further provides a chip, where the chip includes the oscillator circuit 100 described above, and the oscillator circuit 100 is configured to provide a clock signal to a clock using circuit in the chip.
The oscillator circuit 100 provided by the embodiment of the present application is applied to a chip, so that a clock signal with a stable frequency can be provided for a clock using circuit in the chip, the clock using circuit is a circuit that needs to be triggered by the clock signal, such as a digital circuit for timing control, and the like, and the oscillator circuit 100 has a simple structure, a few modules, low power consumption, and a high current utilization rate, and can enable the chip to achieve beneficial effects such as high frequency stability and low power consumption.
Specifically, the chip is further provided with a preset input/output interface, and n can be adjusted through the input/output interface in a software or hardware mode, so that the zero temperature drift clock frequency is realized.
The above-mentioned serial numbers of the embodiments of the present application are merely for description, and do not represent the advantages and disadvantages of the embodiments. While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and various equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An oscillator circuit, characterized in that the oscillator circuit comprises:
the first end of the oscillating resistor is connected with a preset power supply voltage, and the second end of the oscillating resistor is grounded;
the first end of the oscillation capacitor is connected with the preset power supply voltage, and the second end of the oscillation capacitor is grounded;
the circuit comprises a first switching tube circuit and a second switching tube circuit, wherein the first switching tube circuit comprises a plurality of first switching tubes which are connected in parallel, and the second switching tube circuit comprises at least one second switching tube;
a first input end of the comparator is connected with the first end of the oscillating resistor through the first switching tube circuit, a second input end of the comparator is connected with the first end of the oscillating capacitor through the second switching tube circuit, and an output end of the comparator is used for outputting a clock signal;
the charging and discharging circuit is connected with the oscillating capacitor and is used for charging and discharging the oscillating capacitor;
and the control circuit is connected with the output end of the comparator and the charging and discharging circuit and is used for controlling the charging and discharging circuit to charge and discharge the oscillating capacitor according to the clock signal.
2. The oscillator circuit according to claim 1, wherein the first switching tube circuit further comprises a plurality of first switches, each of the first switches being spaced between every two of the first switching tubes; the control circuit is connected with each first switch and used for controlling the on-off of each first switch.
3. The oscillator circuit according to claim 1, wherein the first switch tube and the second switch tube are MOS tubes or transistors.
4. The oscillator circuit according to claim 3, wherein a gate of each of the first MOS transistors is connected to the first terminal of the oscillating resistor, a drain of each of the first MOS transistors is connected to the first input terminal of the comparator, and a source of each of the first MOS transistors is connected to the predetermined power supply voltage.
5. The oscillator circuit according to claim 3, wherein a gate of the second MOS transistor is connected to the first end of the oscillation capacitor, a drain of the second MOS transistor is connected to the second input terminal of the comparator, and a source of the second MOS transistor is connected to the predetermined power supply voltage.
6. The oscillator circuit according to claim 1, wherein the charge and discharge circuit comprises a second switch and a third switch, a first end of the second switch is connected to the preset power voltage, and a second end of the second switch is connected to a first end of the third switch; the second end of the third switch is grounded.
7. The oscillator circuit of claim 1, wherein the first switching tube and the second switching tube are of the same type.
8. The oscillator circuit of claim 1, wherein the oscillator circuit is integrated within a chip.
9. The oscillator circuit according to any one of claims 1 to 8, wherein the first terminal of the oscillating resistor is connected to the predetermined power supply voltage via a first current source, and the first terminal of the second switch is connected to the predetermined power supply voltage via a second current source.
10. A chip comprising the oscillator circuit of any of claims 1 to 9, the oscillator circuit to provide a clock signal to a clock usage circuit in the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220649455.6U CN217135466U (en) | 2022-03-23 | 2022-03-23 | Oscillator circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220649455.6U CN217135466U (en) | 2022-03-23 | 2022-03-23 | Oscillator circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217135466U true CN217135466U (en) | 2022-08-05 |
Family
ID=82645862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220649455.6U Active CN217135466U (en) | 2022-03-23 | 2022-03-23 | Oscillator circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217135466U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117134710A (en) * | 2023-08-02 | 2023-11-28 | 北京伽略电子股份有限公司 | RC oscillator with high frequency stability |
-
2022
- 2022-03-23 CN CN202220649455.6U patent/CN217135466U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117134710A (en) * | 2023-08-02 | 2023-11-28 | 北京伽略电子股份有限公司 | RC oscillator with high frequency stability |
| CN117134710B (en) * | 2023-08-02 | 2024-04-12 | 北京伽略电子股份有限公司 | RC oscillator with high frequency stability |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106374881B (en) | Quick-start low-power-consumption clock oscillator | |
| CN106059538B (en) | A kind of relaxor of included process deviation calibration function | |
| JP3752107B2 (en) | Power-on reset circuit for integrated circuits | |
| US7884679B2 (en) | Process, voltage, temperature compensated oscillator | |
| CN112234957B (en) | Analog oscillator circuit with negative feedback regulation function | |
| CN110504920B (en) | Oscillator | |
| CN111697947B (en) | High-precision wide-range relaxation oscillator insensitive to temperature | |
| JP2012070224A (en) | Semiconductor device | |
| JPH0888565A (en) | Resistorless voltage-controlled oscillator | |
| US7038967B2 (en) | Semiconductor apparatus capable of performing refresh control | |
| CN217135466U (en) | Oscillator circuit and chip | |
| CN111464152A (en) | Circuit and method for realizing low temperature drift and low power consumption of on-chip clock | |
| CN103823494B (en) | The timer circuit related to temperature | |
| CN107437931B (en) | RC relaxation oscillator | |
| CN210490799U (en) | SoC built-in oscillating circuit | |
| CN117060890A (en) | RC relaxation oscillator | |
| CN116015267A (en) | Power-on and power-off reset method and device for protecting chip low-voltage device | |
| CN212435662U (en) | Low-temperature drift low-power consumption on-chip clock circuit | |
| CN114268297A (en) | Relaxation oscillator circuit with temperature compensation | |
| CN108649928B (en) | Oscillator circuit with freely adjustable frequency and duty ratio | |
| CN107565935B (en) | Circuit for reducing power consumption of oscillator | |
| CN102193576B (en) | Reference voltage generation circuit | |
| TWI605325B (en) | Current source circuit | |
| CN111884591A (en) | High-precision low-temperature-drift oscillator | |
| CN113258878B (en) | Oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |