CN107437931B

CN107437931B - RC relaxation oscillator

Info

Publication number: CN107437931B
Application number: CN201710198179.XA
Authority: CN
Inventors: 蔡俊; 卢君明; 黄继颇
Original assignee: Anhui Saiteng Microelectronics Co ltd
Current assignee: Anhui Saiteng Microelectronics Co ltd
Priority date: 2017-03-29
Filing date: 2017-03-29
Publication date: 2023-05-12
Anticipated expiration: 2037-03-29
Also published as: CN107437931A

Abstract

The invention discloses an RC relaxation oscillator, which comprises a charge-discharge capacitor C1 and a digital logic circuit for outputting square wave signals with specified frequency according to charge-discharge current on the charge-discharge capacitor C1, and is characterized in that: the relaxation oscillator further comprises a charge-discharge current regulating circuit and a voltage reference circuit, wherein the voltage reference circuit is connected with the charge-discharge current regulating circuit, and the charge-discharge current outputted by the charge-discharge current regulating circuit charges and discharges the charge-discharge capacitor C1. The invention has the advantages that the frequency of the square wave signal output by the oscillator can be conveniently controlled by the control signal TRIM2[7:0] through the charge-discharge current regulating circuit, and the square wave signal with the specified frequency is generated; meanwhile, the influence of temperature change on charge and discharge current can be eliminated through reasonable configuration of control signals TRIM1[7:0], SETP and SETN, and a square wave signal with specified frequency, which is not influenced by the temperature change, is obtained.

Description

RC relaxation oscillator

Technical Field

The invention belongs to the field of oscillator circuits, and particularly relates to an RC relaxation oscillator capable of automatically adjusting according to temperature change, keeping charge and discharge current stable and outputting specified frequency.

Background

There are various kinds of oscillators, one of which is to be classified into a sine wave oscillator and a relaxation oscillator according to the oscillation waveform generated by the oscillator, wherein the output waveform of the relaxation oscillator is a rectangular square wave. While classified according to the circuit implementation of the oscillator, one circuit implementation is implemented using a resistive-capacitive circuit, referred to as a resistive-capacitive oscillator, also referred to as an RC oscillator.

In early electronics, RC oscillators were implemented using resistor and capacitor charge-discharge circuits. In modern integrated circuits, the resistor is often replaced by a current source. The circuit of the conventional RC relaxation oscillator is shown in FIG. 1, and the circuit structure of the conventional RC relaxation oscillator mainly comprises constant current sources (I1 and I2), charge and discharge capacitors C, analog comparators (COMP 1 and COMP 2), RS triggers and the like. The working principle is that a constant current is utilized to charge and discharge a capacitor C, so that a pulse waveform is generated. In the relaxation oscillator, the voltage VC across the capacitor C is compared with the reference voltages VH and VL at the input ends of the comparators COMP1 and COMP2, and when the voltage is higher than the reference voltage VH or lower than the reference voltage VL, the output state of the comparator is inverted, and finally rectangular square wave signals with a certain frequency are sent out at the output ends Q and QB of the RS flip-flop. In the case of constant charging current, the voltage across the capacitor C is approximately linear with the time of charging and discharging, and therefore, the time of charging and discharging the capacitor can be changed by setting the charging current, thereby changing the pulse width and period of the pulse waveform.

The RC relaxation oscillator has the advantages of simple structure, small required power consumption, low cost, convenient frequency adjustment, easy integration into a standard CMOS process integrated circuit and wide application. However, because the semiconductor process is affected by the power supply voltage change and the temperature change, the accuracy of the output frequency of the RC relaxation oscillator also generates larger deviation, and the accuracy requirement of the system cannot be met. If an external high-precision resistor is used instead of an internal constant current, an oscillation frequency with higher precision can be obtained, but in this way, the complexity of the system is increased, and the area and the cost are increased. In the prior art, the relaxation oscillator circuit design can adjust the frequency of the output oscillation signal by adopting a mode of adjusting an internal resistor and a capacitor, but the change of the power supply voltage and the change of the temperature cannot be automatically and accurately adjusted to stabilize the output frequency.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides an RC relaxation oscillator, which aims to improve the stability of the square wave signal frequency output by the relaxation oscillator, and can control the square wave signal frequency output by the oscillator through a control signal to generate a square wave signal with a specified frequency; meanwhile, the influence of temperature change on charge and discharge current can be eliminated through reasonable configuration of other control signals, and the square wave signal with the specified frequency, which is not influenced by the temperature change, is obtained.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: an RC relaxation oscillator, includes charge-discharge capacitor C1 and according to charge-discharge capacitor C1 on charge-discharge current output assigned frequency square wave signal's digital logic circuit, its characterized in that: the relaxation oscillator further comprises a charge-discharge current regulating circuit and a voltage reference circuit, wherein the voltage reference circuit is connected with the charge-discharge current regulating circuit, and the charge-discharge current outputted by the charge-discharge current regulating circuit charges and discharges the charge-discharge capacitor C1.

The charge-discharge current regulating circuit comprises a trimming resistor R3, a trimming resistor R4, an amplifier, transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15 and M18, wherein a reference voltage signal VREF output by the voltage reference circuit is input to the negative input end of the amplifier, the output end of the amplifier is connected with the grid electrode of the transistor M12, the source electrode of the transistor M12 is respectively connected with the positive input end of the amplifier and one end of the trimming resistor R4, the other end of the trimming resistor R4 is grounded, the control input end of the trimming resistor R4 is input with a control signal TRIM2[7:0] to regulate the resistance value of the trimming resistor R4, the drain electrode of the transistor M12 is connected with the drain electrode of the transistor M11, the source electrode of the transistor M11 is connected with a power supply VDD, the grid electrodes of the transistor M11 are respectively connected with the drain electrode of the transistor M11, the grid electrodes of the transistor M13 and the grid electrodes of the transistor M15, the source electrodes of the transistor M13 and the drain electrodes of the transistor M15 are respectively connected with the power supply VDD, the drain electrodes of the transistor M13 and the drain electrodes of the transistor M14 are respectively connected with the drain electrodes of the transistor M14 and the drain electrode of the transistor M18; the source of the transistor M8 is connected with the drain of the transistor M7, the source of the transistor M7 is connected with the power supply VDD, the grid electrode of the transistor M7 is input with the control signal SETP, the grid electrode of the transistor M8 is respectively connected with the grid electrode and the drain electrode of the transistor M6, the source electrode of the transistor M6 is connected with the power supply VDD, the drain electrode of the transistor M6 is connected with the drain electrode of the transistor M19, the source electrode of the transistor M19 is grounded, the grid electrode of the transistor M19 is respectively connected with the grid electrode of the transistor M5, the drain electrode of the transistor M5 and the grid electrode of the transistor M9, the source electrode of the transistor M9 is connected with the drain electrode of the transistor M10, the source electrode of the transistor M5 is grounded, the drain electrode of the transistor M5 is connected with the drain electrode of the transistor M4, the source electrode of the transistor M4 is connected with the power supply VDD through a trimming resistor R3, the control input end of the trimming resistor is input with the control signal TRIM1[7:0], the drain electrode of the transistor M15 is connected with the capacitor C1, the capacitor C1 is provided with the charging current through the first switch, and the capacitor C1 is provided with the discharging current through the second switch C1.

The trimming resistor R3 and the trimming resistor R4 are digital adjustable resistors.

The digital logic circuit comprises a comparator COMP1, a comparator COMP2, an RS trigger and a NOT gate circuit, wherein voltages at two ends of the charge-discharge capacitor C1 are respectively input to a positive input end of the comparator COMP1 and a negative input end of the comparator COMP2, reference voltage VH and reference voltage VL are respectively input to the negative input end of the comparator COMP1 and the positive input end of the comparator COMP2, an output end of the comparator COMP1 and an output end of the comparator COMP2 are respectively input to an S pin and an R pin of the RS trigger, a square wave signal CLK is output by the Q output end of the RS trigger through the NOT gate circuit, and a QB output signal of the RS trigger is input to the second switch and is connected with the first switch.

The first switch and the second switch are respectively a transistor M16 and a transistor M17, the drain electrode of the transistor M15 is connected with the source electrode of the transistor M16, the grid electrode of the transistor M16 is connected with the QB pin of the RS trigger, the drain electrode of the transistor M16 is respectively connected with the drain electrode of the transistor M17 and one end of the charge-discharge capacitor C1, the other end of the charge-discharge capacitor C1 is grounded, the source electrode of the transistor M17 is connected with the drain electrode of the transistor M18, and the grid electrode of the transistor M17 is connected with the Q pin output end of the RS trigger.

The voltage reference circuit comprises a transistor M1, a transistor M2, a transistor M3, an analog operational amplifier, a bipolar transistor Q1, a bipolar transistor Q2 and a bipolar transistor Q3, wherein sources of the transistors M1, M2 and M3 are all connected with a power supply VDD, drains of the transistor M1 are respectively connected with an emitter of the bipolar transistor Q1 and an inverting input end of the analog operational amplifier, and a base and a collector of the transistor Q1 are grounded; the drain electrode of the transistor M2 is respectively connected with the non-inverting input end of the analog operational amplifier, and is connected with the emitter electrode of the bipolar transistor Q2 through a resistor R1, and the base electrode and the collector electrode of the bipolar transistor Q2 are grounded; the drain electrode of the transistor M3 is connected with the emitter electrode of the bipolar transistor Q3, the base electrode and the collector electrode of the bipolar transistor Q3 through the resistor R2 and grounded, the output end of the analog operational amplifier is respectively connected with the grid electrode of the transistor M1, the grid electrode of the transistor M2, the grid electrode of the transistor M3 and the grid electrode of the transistor M4, and the drain electrode of the transistor M3 outputs the reference voltage VREF.

The invention has the advantages that the frequency of the square wave signal output by the oscillator can be conveniently controlled by the control signal TRIM2[7:0] through the charge-discharge current regulating circuit, and the square wave signal with the specified frequency can be generated; meanwhile, the influence of temperature change on charge and discharge current can be eliminated through reasonable configuration of control signals TRIM1[7:0], SETP and SETN, and a square wave signal with specified frequency, which is not influenced by the temperature change, is obtained.

Drawings

The present specification includes the following drawings, the contents of which are respectively:

FIG. 1 is a schematic diagram of a prior art RC relaxation oscillator;

fig. 2 is a circuit schematic of an RC relaxation oscillator of the present invention.

Detailed Description

The following detailed description of the embodiments of the invention, given by way of example only, is presented in the accompanying drawings to aid in a more complete, accurate and thorough understanding of the concepts and aspects of the invention, and to aid in its practice, by those skilled in the art.

The RC relaxation oscillator comprises a charge-discharge capacitor C1, a digital logic circuit, a charge-discharge current regulating circuit and a voltage reference circuit, wherein the digital logic circuit outputs square wave signals with specified frequencies according to charge-discharge currents on the charge-discharge capacitor C1, the voltage reference circuit is connected with the charge-discharge current regulating circuit, and the charge-discharge currents outputted by the charge-discharge current regulating circuit charge-discharge the charge-discharge capacitor C1. The voltage reference circuit provides reference voltage VREF for the charge-discharge regulating circuit, the charge-discharge current regulating circuit can regulate the charge-discharge current, the charge-discharge time of the capacitor C1 is different due to different charge-discharge current, and the frequency of the output square wave signal is changed.

The constituent circuits of the oscillator are further described below in conjunction with fig. 2.

The charge-discharge current regulating circuit comprises a trimming resistor R3, a trimming resistor R4, an amplifier, transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15 and M18, wherein the trimming resistor R3 and the trimming resistor R4 are digital adjustable resistors. The reference voltage signal VREF output by the voltage reference circuit is input to the inverting input end of the amplifier, the output end of the amplifier is connected with the grid electrode of the transistor M12, the source electrode of the transistor M12 is respectively connected with the non-inverting input end of the amplifier and one end of the trimming resistor R4, the other end of the trimming resistor R4 is grounded, the control input end of the trimming resistor R4 is input with a control signal TRIM2[7:0] to adjust the resistance value of the trimming resistor R4, the drain electrode of the transistor M12 is connected with the drain electrode of the transistor M11, the source electrode of the transistor M11 is connected with the power supply VDD, the grid electrode of the transistor M11 is respectively connected with the drain electrode of the transistor M11, the grid electrode of the transistor M13 and the grid electrode of the transistor M15, the source electrodes of the transistor M13 and the M15 are respectively connected with the power supply VDD, the drain electrode of the transistor M13 is respectively connected with the drain electrode of the transistor M8, the drain electrode of the transistor M9, the drain electrode of the transistor M14 is connected with the grid electrode of the transistor M18, and the source electrodes of the transistor M14 are grounded; the source of the transistor M8 is connected with the drain of the transistor M7, the source of the transistor M7 is connected with the power supply VDD, the grid electrode of the transistor M7 is input with the control signal SETP, the grid electrode of the transistor M8 is respectively connected with the grid electrode and the drain electrode of the transistor M6, the source electrode of the transistor M6 is connected with the power supply VDD, the drain electrode of the transistor M6 is connected with the drain electrode of the transistor M19, the source electrode of the transistor M19 is grounded, the grid electrode of the transistor M19 is respectively connected with the grid electrode of the transistor M5, the drain electrode of the transistor M5 and the grid electrode of the transistor M9, the source electrode of the transistor M9 is connected with the drain electrode of the transistor M10, the source electrode of the transistor M5 is grounded, the drain electrode of the transistor M5 is connected with the drain electrode of the transistor M4, the source electrode of the transistor M4 is connected with the power supply VDD through a trimming resistor R3, the control input end of the trimming resistor is input with the control signal TRIM1[7:0], the drain electrode current of the transistor M15 is connected with the capacitor C1, the drain electrode of the transistor M18 is connected with the drain electrode of the transistor M9 is grounded, the transistor M18 is connected with the drain electrode of the transistor C1, the capacitor C1 is connected with the drain electrode of the transistor C1.

The digital logic circuit comprises a comparator COMP1, a comparator COMP2, an RS trigger and a NOT gate, wherein voltages at two ends of a charge-discharge capacitor C1 are respectively input to a positive input end of the comparator COMP1 and a negative input end of the comparator COMP2, reference voltage VH and reference voltage VL are respectively input to a negative input end of the comparator COMP1 and a positive input end of the comparator COMP2, an output end of the comparator COMP1 and an output end of the comparator COMP2 are respectively input to an S pin and an R pin of an R pin end of the RS trigger, a square wave signal CLK is output by the Q output end of the RS trigger through the NOT gate, and QB output signals of the RS trigger are input to a second switch M17 and the QB output signal of the RS trigger and are connected with a first switch M16.

The voltage reference circuit comprises a transistor M1, a transistor M2, a transistor M3, an analog operational amplifier, a bipolar transistor Q1, a bipolar transistor Q2 and a bipolar transistor Q3, wherein sources of the transistors M1, M2 and M3 are all connected with a power supply VDD, drains of the transistor M1 are respectively connected with an emitter of the bipolar transistor Q1 and a negative input end of the amplifier, and a base electrode and a collector of the transistor Q1 are grounded; the drain electrode of the transistor M2 is respectively connected with the non-inverting input end of the analog operational amplifier, and is connected with the emitter electrode of the bipolar transistor Q2 through a resistor R1, and the base electrode and the collector electrode of the bipolar transistor Q2 are grounded; the drain electrode of the transistor M3 is connected with the emitter electrode of the bipolar transistor Q3, the base electrode and the collector electrode of the bipolar transistor Q3 through the resistor R2 and grounded, the output end of the analog operational amplifier is respectively connected with the grid electrode of the transistor M1, the grid electrode of the transistor M2, the grid electrode of the transistor M3 and the grid electrode of the transistor M4, and the drain electrode of the transistor M3 outputs the reference voltage VREF.

The drain current of the transistor M15 is used as the charging current of the charging/discharging current C1, and the drain current of the transistor M18 is used as the discharging current of the capacitor C1. The transistor M15 and the transistor M11 form a mirror circuit, the drain current of the transistor M15 is obtained by mirroring the drain of the transistor M11, the drain current of the transistor M11 is related to the trimming resistor R4 and the input signal VREF of the amplifier, namely, the charging current of the capacitor C1 is related to the reference voltage VREF output by the voltage reference circuit and the trimming resistor R4, the trimming resistor is a digital adjustable resistor, and the input control signal TRIM2[7:0] is used for controlling the size of the trimming resistor R4 so as to adjust the charging current.

The drain current of transistor M18 is mirrored by the drain current of transistor M14, and the drain current of transistor M14 consists of three parts: the drain current of the transistor M13, the drain current of the transistor M8, and the drain current of the transistor M9, and the drain current of the transistor M14 is obtained by adding the drain current of the transistor M13 to the drain current of the transistor M8 and subtracting the drain current of the transistor M9. The drain current of the transistor M13 is mirrored by the drain current of the transistor M11, and in the case where the charging current is unchanged, that is, the drain current of the transistor M11 is unchanged, that is, the trimming resistor R4 and the input reference voltage VREF are unchanged, the discharging current is only related to the drain current of the transistor M8 and the drain current of the transistor M9. When the drain current of the transistor M8 increases, the discharge current increases; when the drain current of M9 increases, the discharge current can be reduced. The transistor M8 and the transistor M6 form a current mirror circuit, and the transistor M7 compensates the drain current of the transistor M8, so that the drain current of the transistor M8 is related to the drain current of the transistor M6 and the drain current of the transistor M7, the drain current of the transistor M6 is related to the drain current of the transistor M4 after passing through the current mirror circuit formed by the transistors M5 and M19, and similarly the drain current of the transistor M9 is related to the drain currents of the transistor M10 and M4, the drain current of the transistor M4 is controlled by the trimming resistor R3, and when the trimming resistor R3 increases, the drain current of the transistor M4 decreases. Thus, the drain currents of M8 and M9 are related to the trimming resistor R3, and M8 is also related to M7, and when the input control signal SETP of M7 is high, the transistor M7 is turned off, the drain compensation current of the transistor M8 is turned off, and M9 is also related to M10, and when the input control signal SETN of M10 is low, the transistor M10 is turned off, and the drain compensation current of M9 is turned off.

Accordingly, the discharge current is related to the input control signals SETP and SETN of the input control signals SETP and M10 of the M7 and the control signal TRIM1[7:0] of the trimming resistor R3, and the charge current is related to the trimming resistor R4 and the voltage reference signal VREF.

When the square waves with different frequencies are required to be output or the frequency of the square waves is required to be finely adjusted, the size of the fine adjustment resistor R4 can be adjusted through TRIM2[7:0], so that the size of charging current is adjusted, the frequency of the square waves is further adjusted or finely adjusted, the purpose of adjusting the output frequency of the square waves is achieved, the frequency adjustability of the oscillator circuit is improved, and when process deviation occurs, the frequency of the square waves can be adjusted to a designated frequency.

At normal temperature, such as 25deg.C, the control signal STEN is set to low level, the control signal STEP is set to high level, and the charging current is adjusted by TRIM2[7:0] configuration, so as to control the output frequency of the oscillator, and make the output frequency of the oscillator consistent with the design expected frequency. When the temperature changes, the corresponding adjustment control signals SETN, SETP, TRIM [7:0] are needed to generate a discharge current with the temperature changes, so as to counteract the influence caused by the temperature changes, and further stabilize the frequency of the output signal. When the oscillator is actually used, if the output frequency of the chip shows positive temperature coefficient change along with the temperature rise, the discharge current with a negative temperature coefficient can be generated, the discharge speed of the capacitor can be reduced through the reduction of the discharge current, and the change of the oscillation frequency caused by the positive temperature coefficient of the original circuit can be counteracted. When the temperature changes, if the output frequency increases with the temperature rise, STEN is configured to be high level, M10 is conducted, and the drain current of M9 is a positive temperature coefficient current, so that the drain current of M14 is the initial discharge current minus the drain current of M9, thereby reducing the discharge current with the temperature rise and reducing the frequency; if the output frequency decreases with increasing temperature, STEP is set to a low level, M7 is turned on, the drain electrode of M8 is also a positive temperature coefficient current, the current of M8 is added to the current of M13, and the added current flows into M14, so as to form a compensation current which increases with increasing temperature, thereby increasing the discharge current and finally increasing the frequency of the output oscillation signal. The temperature coefficient of the discharge current is controlled by the control signal TRIM1[7:0] to control the size of the trimming resistor, and the control signals SETN and STEP are used for controlling the temperature coefficient of the discharge current, so that the purpose that the compensation current generates the discharge current along with the temperature change under the temperature change to stabilize the output frequency of the oscillator is realized.

The RC relaxation oscillator adopting the circuit can adjust or fine tune the output frequency according to the actual output requirement, and the adjusting method is that the size of the fine tuning resistor R4 is adjusted, and the size of R4 can be adjusted according to the size of the control signal TRIM2[7:0] because R4 is a digital adjustable resistor, so that the oscillator can output different frequencies. In actual operation, the characteristic of the discharge current increasing or decreasing along with the temperature can be adjusted by adjusting the control signal SETN, SETP, TRIM [7:0] due to the change of the output square wave frequency caused by the change of the ambient temperature, and when the temperature is changed, the compensation circuit generates the discharge current increasing along with the temperature or the discharge current decreasing along with the temperature to counteract the change of the output square wave frequency, so that the frequency of the output square wave is stabilized.

The invention is described above by way of example with reference to the accompanying drawings. It will be clear that the invention is not limited to the embodiments described above. As long as various insubstantial improvements are made using the method concepts and technical solutions of the present invention; or the invention is not improved, and the conception and the technical scheme are directly applied to other occasions and are all within the protection scope of the invention.

Claims

The RC relaxation oscillator comprises a charge-discharge capacitor C1 and a digital logic circuit for outputting a square wave signal with a specified frequency according to charge-discharge current on the charge-discharge capacitor C1, and is characterized in that: the relaxation oscillator further comprises a charge-discharge current regulating circuit and a voltage reference circuit, wherein the voltage reference circuit is connected with the charge-discharge current regulating circuit, and the charge-discharge current outputted by the charge-discharge current regulating circuit charges and discharges the charge-discharge capacitor C1;

the charge-discharge current regulating circuit comprises a trimming resistor R3, a trimming resistor R4, an amplifier, transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15 and M18, wherein a reference voltage signal VREF output by the voltage reference circuit is input to the negative input end of the amplifier, the output end of the amplifier is connected with the grid electrode of the transistor M12, the source electrode of the transistor M12 is respectively connected with the positive input end of the amplifier and one end of the trimming resistor R4, the other end of the trimming resistor R4 is grounded, the control input end of the trimming resistor R4 is input with a control signal TRIM2[7:0] to regulate the resistance value of the trimming resistor R4, the drain electrode of the transistor M12 is connected with the drain electrode of the transistor M11, the source electrode of the transistor M11 is connected with a power supply VDD, the grid electrodes of the transistor M11 are respectively connected with the drain electrode of the transistor M11, the grid electrodes of the transistor M13 and the grid electrodes of the transistor M15, the source electrodes of the transistor M13 and the drain electrodes of the transistor M15 are respectively connected with the power supply VDD, the drain electrodes of the transistor M13 and the drain electrodes of the transistor M14 are respectively connected with the drain electrodes of the transistor M14 and the drain electrode of the transistor M18; the source of the transistor M8 is connected with the drain of the transistor M7, the source of the transistor M7 is connected with a power supply VDD, the grid electrode of the transistor M7 is input with a control signal SETP, the grid electrode of the transistor M8 is respectively connected with the grid electrode and the drain electrode of the transistor M6, the source electrode of the transistor M6 is connected with the power supply VDD, the drain electrode of the transistor M6 is connected with the drain electrode of the transistor M19, the source electrode of the transistor M19 is grounded, the grid electrode of the transistor M19 is respectively connected with the grid electrode of the transistor M5, the drain electrode of the transistor M5 and the grid electrode of the transistor M9, the source electrode of the transistor M9 is connected with the drain electrode of the transistor M10, the source electrode of the transistor M5 is grounded, the drain electrode of the transistor M5 is connected with the drain electrode of the transistor M4, the source electrode of the transistor M4 is connected with the power supply VDD through a trimming resistor R3, the control input end of the trimming resistor is input with a control signal TRIM1[7:0], the drain electrode current of the transistor M15 is connected with the capacitor C1 through a first switch to provide charging current, the drain electrode of the transistor M18 is connected with the drain electrode of the capacitor C1 through a second switch to provide discharging current;

the digital logic circuit comprises a comparator COMP1, a comparator COMP2, an RS trigger and a NOT gate circuit, wherein voltages at two ends of the charge-discharge capacitor C1 are respectively input to a positive input end of the comparator COMP1 and a negative input end of the comparator COMP2, reference voltage VH and reference voltage VL are respectively input to the negative input end of the comparator COMP1 and the positive input end of the comparator COMP2, an output end of the comparator COMP1 and an output end of the comparator COMP2 are respectively input to an S pin and an R pin of the RS trigger, a square wave signal CLK is output by the Q output end of the RS trigger through the NOT gate circuit, and a Q output end signal of the RS trigger is input to the second switch and a QB output signal of the RS trigger is connected with the first switch;

the first switch and the second switch are respectively a transistor M16 and a transistor M17, the drain electrode of the transistor M15 is connected with the source electrode of the transistor M16, the grid electrode of the transistor M16 is connected with the QB pin of the RS trigger, the drain electrode of the transistor M16 is respectively connected with the drain electrode of the transistor M17 and one end of the charge-discharge capacitor C1, the other end of the charge-discharge capacitor C1 is grounded, the source electrode of the transistor M17 is connected with the drain electrode of the transistor M18, and the grid electrode of the transistor M17 is connected with the Q pin output end of the RS trigger;

the voltage reference circuit comprises a transistor M1, a transistor M2, a transistor M3, an analog operational amplifier, a bipolar transistor Q1, a bipolar transistor Q2 and a bipolar transistor Q3, wherein sources of the transistors M1, M2 and M3 are all connected with a power supply VDD, drains of the transistor M1 are respectively connected with an emitter of the bipolar transistor Q1 and an inverting input end of the analog operational amplifier, and a base and a collector of the transistor Q1 are grounded; the drain electrode of the transistor M2 is respectively connected with the non-inverting input end of the analog operational amplifier, and is connected with the emitter electrode of the bipolar transistor Q2 through a resistor R1, and the base electrode and the collector electrode of the bipolar transistor Q2 are grounded; the drain electrode of the transistor M3 is connected with the emitter electrode of the bipolar transistor Q3, the base electrode and the collector electrode of the bipolar transistor Q3 through the resistor R2 and grounded, the output end of the analog operational amplifier is respectively connected with the grid electrode of the transistor M1, the grid electrode of the transistor M2, the grid electrode of the transistor M3 and the grid electrode of the transistor M4, and the drain electrode of the transistor M3 outputs the reference voltage VREF.
2. The RC relaxation oscillator of claim 1, wherein: the trimming resistor R3 and the trimming resistor R4 are digital adjustable resistors.