JP2004349831A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit with a simple configuration and low power consumption wherein a consumed current is small. <P>SOLUTION: The oscillation circuit is provided with: a capacitor Co for charging / discharging a current; a charge / discharge circuit 1 for controlling the current; a first comparator (COMP1) 2 for detecting a charging voltage across the capacitor Co with a first reference voltage Vref1; a second comparator (COMP2) 3 for detecting a charging voltage across the capacitor Co with a second reference voltage Vref2; and a bias current control circuit 4 for respectively receiving an output of the first comparator 2 and an output of the second comparator 3. The bias current control circuit 4 cuts off bias currents of the first and second comparators 2, 3 and alternately invalidates the comparators to control a charging / discharging period of the capacitor Co. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillating circuit configured by a semiconductor integrated circuit or the like and capable of reducing power consumption when applied to generation of a reference clock or the like, and particularly to an oscillating circuit that generates a fundamental frequency used in a power supply device.
[0002]
[Prior art]
Patent Literature 1 describes a conventional technique of a signal generator capable of generating a linear triangular waveform with a simple configuration and low power consumption.
[0003]
FIG. 6 is a circuit diagram showing a configuration of a conventional oscillation circuit, which is shown in FIG. This oscillation circuit includes an amplifier 12, a current mirror 14, a first comparator 16, a second comparator 18, an RS flip-flop 24, a first multiplexer 26, a second multiplexer 28, and a third multiplexer 32. These circuit components constitute a means for linearly charging and discharging the externally connected capacitor 22. Capacitor 22 is connected to the current output node of this circuit via integrated circuit external connection pad 36. According to these configurations, the direction in which the charge / discharge current flows is switched, and the power consumption of the circuit can be reduced by flowing the discharge current through this new current path.
[0004]
Although this oscillation circuit has a one-shot operation mode and a free-run operation mode, only the free-run operation mode of continuous oscillation will be described here.
FIG. 7 is a circuit diagram showing an equivalent circuit of the oscillation circuit of FIG. 6 in a free-run operation mode. As shown in FIG. 7, the equivalent circuit in the free-run operation mode can be represented as a fixed connection state by omitting a multiplexer. The amplifier 12 is a differential bipolar transistor pair in which the emitters of the transistors Q1 and Q2 are coupled, and a bias current is supplied from a current source 34. The input voltage of the amplifier 12 is supplied to the bases of Q1 and Q2, and the output current is output from the collectors of the transistors Q1 and Q2. The discharge current of the capacitor 22 flows to the collector of the transistor Q1. The current input terminal of the super-Wilson type PNP current mirror 14 is connected to the second current output terminal of the amplifier 12 (collector of the transistor Q2), and the current output terminal is connected to the first current output terminal of the amplifier 12 (the transistor Q1). Collector). The output current of the current mirror 14 becomes the charging current of the external capacitor 22.
[0005]
The positive input terminal (non-inverting input) of the first comparator 16 is connected to the first current output terminal of the amplifier 12, and the negative input terminal (inverting input) of the comparator 16 receives the high-level threshold voltage VH of the circuit node 42. receive. The positive input of the second comparator 18 is also connected to the first current output of the amplifier 12, and the negative input receives the low level threshold voltage VL of the circuit node 38. The reset input terminal R of the RS flip-flop 24 is connected to the output terminal of the first comparator 16, the set input terminal S is connected to the output terminal of the second comparator 18, and the output terminal Q of the RS flip-flop 24 is It is connected to the second voltage input terminal of the amplifier 12 (the base of Q2). The first voltage input terminal of the amplifier 12 is supplied with only the reference voltage VREF. The S input terminal of the RS flip-flop 24 directly receives only the output of the second comparator 18. Free-run output V of this oscillation circuit _OUT Is obtained from the output terminal Q of the RS flip-flop 24. The remaining circuits such as the amplifier 12, the current mirror 14, the first comparator 16, the second comparator 18, the RS flip-flop 24, and the external capacitor 22 and their connections are the same as those of the oscillation circuit of FIG.
[0006]
FIG. 8 is a timing waveform chart for explaining the operation of the equivalent circuit in the free-run operation mode. In FIG. 8, the output of the second comparator 18 (S input of the RS flip-flop 24), the output of the first comparator 16 (R input of the RS flip-flop 24), the voltage of the capacitor 22, and the free-run output of the oscillation circuit (Q output of the RS flip-flop 24), respectively, and these waveforms are represented by S, R, C, and V, respectively. _OUT As shown. In the free-run operation mode, the external capacitor 22 is repeatedly charged and discharged continuously.
[0007]
In the following description, first, the voltage C of the capacitor 22 is the median of VL and VH, and the Q output V of the RS flip-flop 24 _OUT Is at a high level. Since the base of the transistor Q2 has a higher potential than the base of the transistor Q1, the current corresponding to the current flowing through the transistor Q2 and the current mirror 14 charges the capacitor 22. When the voltage of the capacitor 22 reaches the high level threshold value VH, the output voltage of the comparator 16 becomes high level, the RS flip-flop 24 is reset, and the Q output of the RS flip-flop 24 changes to low level. As a result, the current flow of the amplifier 12 is switched, and the current flows through the transistor Q1, and the discharge of the capacitor 22 is started. When the voltage of the capacitor 22 reaches the low-level threshold voltage VL, the output of the comparator 18 becomes low, and the state is switched by setting the RS flip-flop 24. When the Q output of the RS flip-flop 24 becomes high in this way, current flows again through the transistor Q2 and the current mirror 14, and the above-described charge / discharge operation is continuously repeated.
[0008]
The oscillation circuit disclosed in Patent Literature 1 includes a charge / discharge circuit including a first comparator 16, a second comparator 18, an RS flip-flop 24, an amplifier 12, and a current mirror 14, and a capacitor. 22 is one of the basic configurations of the triangular wave oscillation circuit composed of S.22 and S.22. In this oscillation circuit, if a bias current always flows through the current source 34 of the amplifier 12 during charging and discharging, and if the first comparator 16 and the second comparator 18 are operated, further lower power consumption can be achieved. There is room to do it.
[0009]
Patent Document 2 discloses another conventional technique.
FIG. 9 is a diagram showing a basic configuration of the oscillation circuit described in Patent Document 2. There are voltage sources 101 and 102 for generating first and second reference voltages Vref1 and Vref2, and first and second comparators (COMP1 and COMP2) 103 and 104 for comparing the output voltage Vo of the oscillation circuit. , 104 are connected to first and second inputs of a driver circuit 105, respectively, and the output of the driver circuit 105 is connected to the input of a charge / discharge control circuit 106, so that the output of the charge / discharge control circuit 106, There is an oscillating circuit that controls charging and discharging of a capacitor Co connected to an output terminal Vo of the circuit and outputs a triangular wave, and receives an output Vo of the oscillating circuit and a first arbitrary voltage V1 from a power supply 109 as first inputs. Of the first comparator (COMP1) 103. The bias control circuit 107 is provided with a bias control voltage input provided for bias control of the first comparator (COMP1) 103. And a second bias control circuit 108 which receives the output Vo of the oscillation circuit and the second arbitrary voltage V2 from the power supply 110 as inputs, and uses the output to control the bias of the second comparator (COMP2) 104. Is an oscillation circuit connected to the bias control voltage input provided in.
[0010]
The operation of this oscillation circuit will now be described. For the comparators 103 and 104, the driver circuit 105, and the charge / discharge control circuit 106, when the capacitor Co is discharging, the output Vo of the oscillation circuit is compared with the reference voltage Vref1 by the comparator 103, and the output Vo is lower than the reference voltage Vref1. Then, the comparator 103 is inverted from the Low level to the High level. Then, the output of the driver circuit 105 is also inverted to supply a charge signal to the charge / discharge control circuit 106, and the charge / discharge control circuit 106 operates to charge the capacitor Co with a constant current. When the capacitor Co starts to be charged and the output Vo becomes higher than the reference voltage Vref1, the output of the comparator 103 returns from the high level to the low level.
[0011]
When the capacitor Co is charged, the output Vo of the oscillation circuit is compared with the reference voltage Vref2 by the comparator 104, and when the output Vo becomes higher than the reference voltage Vref2, the comparator 104 inverts from the low level to the high level. Then, the output of the driver circuit 105 is also inverted to give a discharge signal to the charge / discharge control circuit 106, and the charge / discharge control circuit 106 operates to discharge the capacitor Co with a constant current. When the capacitor Co starts to be discharged and the output Vo becomes lower than the reference voltage Vref2, the output of the comparator 104 returns from the high level to the low level.
[0012]
By repeating charging and discharging of the capacitor Co, a triangular wave is output from the output Vo of the oscillation circuit. In the bias control circuits 107 and 108, when the arbitrary voltage V1 is set higher than the reference voltage Vref1, the arbitrary voltage V2 is set lower than the reference voltage Vref2, and the arbitrary voltage V1 is set lower than the arbitrary voltage V2, When the output Vo is lower than the arbitrary voltage V1, the first bias control circuit 107 operates, its output changes, the applied bias voltage of the bias control input of the comparator 103 changes, and the bias current of the comparator 103 increases, A minimum bias current flows through one comparator 104 by a bias voltage applied to a bias input. Then, when the output voltage Vo becomes the reference voltage Vref1 and the comparator 103 performs the inverting operation, an optimal bias current that flows to a desired delay time flows with good timing.
[0013]
When the output Vo of the oscillation circuit is higher than the arbitrary voltage V2, the second bias control circuit 108 operates, the output changes, the applied bias voltage of the bias control input of the comparator 104 changes, and the bias current of the comparator 104 decreases. The minimum bias current flows to one comparator 103 due to the bias voltage applied to the bias input. Then, when the output voltage Vo becomes the reference voltage Vref2 and the comparator 104 performs the inverting operation, an optimal bias current flows with good timing so as to have a desired delay time.
[0014]
As described above, the oscillation circuit described in Patent Document 2 increases the bias current of the comparator 103 or the comparator 104 that performs the inversion operation, and decreases the bias current that does not perform the inversion operation, thereby reducing the operation of the oscillation circuit. Current consumption can be reduced.
[0015]
[Patent Document 1]
JP-A-06-1996976 (Pages 2 to 4, FIGS. 1, 3 and 5)
[Patent Document 2]
JP-A-2002-217687 (pages 6 to 12, FIG. 1)
[0016]
[Problems to be solved by the invention]
However, the conventional triangular wave oscillation circuit as disclosed in Patent Document 1 requires two comparators, consumes a large amount of current during operation, and requires circuit contrivance to reduce power consumption. Further, since two comparators, an RS flip-flop, and a capacitor charge / discharge circuit are required, the circuit configuration tends to be large.
[0017]
On the other hand, in the oscillation circuit of Patent Document 2 described above, as a specific embodiment of the driver circuit, a logic circuit such as an RS flip-flop is required, and a bias control circuit for reducing current consumption is used. However, since a differential circuit is used, there is a problem that the circuit scale becomes large. Further, even if a circuit is devised to reduce the power consumption as in Patent Document 2, there is a problem that the circuit configuration is further increased.
[0018]
An object of the present invention is to provide a low power consumption oscillation circuit having a simpler circuit configuration and low current consumption.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, there is provided an oscillation circuit capable of simultaneously outputting a triangular wave and a rectangular wave by charging and discharging a capacitor. The oscillation circuit includes a charge / discharge circuit for charging / discharging the capacitor, a first comparator for detecting a charge voltage of the capacitor, a second comparator for detecting a discharge voltage of the capacitor, and a first comparator. A bias current control circuit that inputs the output and the output of the second comparator and connects to the charging and discharging circuit to control charging and discharging of the capacitor.
[0020]
In this oscillation circuit, the bias current control circuit controls the charge / discharge period of the capacitor by cutting the bias currents of the first and second comparators and disabling them alternately. Therefore, low power consumption can be achieved.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a block diagram showing a basic configuration of an oscillation circuit according to the present invention. As shown here, a capacitor Co for charging / discharging a current includes a charging / discharging circuit 1 for controlling the current, and a first comparator (COMP1) 2 for detecting a charging voltage of the capacitor Co with a first reference voltage Vref1. A second comparator (COMP2) 3 for detecting the discharge voltage of the capacitor Co with the second reference voltage Vref2, and a bias current having the output of the first comparator 2 and the output of the second comparator 3 as inputs. And a control circuit 4. The bias current control circuit 4 is connected to the charge / discharge circuit 1 and controls charging / discharging of the capacitor Co. The bias current control circuit 4 is connected to the first comparator 2 to control the bias current, and is connected to the second comparator 3 to control the bias current. Here, the first reference voltage Vref1 is supplied from the input terminal 5 to the inverting input terminal of the first comparator 2, and the second reference voltage Vref2 is supplied from the input terminal 6 to the inverting input terminal of the second comparator 3. Supplied. The output voltage Vpulse of the output terminal 7 is a rectangular wave, and the output voltage Vtri of the output terminal 8 is a triangular wave.
[0022]
Next, the operation of the oscillation circuit shown in FIG. 1 will be described.
Here, the first reference voltage Vref1 supplied to the input terminal 5 is set higher than the second reference voltage Vref2 supplied to the input terminal 6, and the first comparator (COMP1) 2 detects the charging voltage. And the second comparator (COMP2) 3 is used for detecting the discharge voltage.
[0023]
Regarding the operation of the first and second comparators 2 and 3 during charging of the capacitor Co, the output voltage Vtri of the charge / discharge circuit 1 to the output terminal 8 is lower than the first reference voltage Vref1, The resulting output voltage Vpulse of the first comparator 2 is in a low state (ground potential). Thereafter, when the capacitor Co is charged by the charging / discharging circuit 1 and the output voltage Vtri of the charging / discharging circuit 1 exceeds the first reference voltage Vref1, the output voltage Vpulse of the first comparator 2 changes to a high state (power supply potential). Change.
[0024]
Regarding the operation of the first and second comparators 2 and 3 when the capacitor Co is discharged, since the output voltage Vtri of the charge / discharge circuit 1 is higher than the second reference voltage Vref2, the output voltage Vpulse of the second comparator 3 Is in a high state (power supply potential), but when the capacitor Co is discharged by the charge / discharge circuit 1 and the output voltage Vtri of the charge / discharge circuit 1 falls below the second reference voltage Vref2, the output voltage Vpulse of the second comparator 3 Changes to a low state (ground potential).
[0025]
During the charging period of the capacitor Co, the output voltage Vpulse of the first and second comparators 2 and 3 is in a low state (ground potential). The bias current is supplied, the supply of the bias current to one second comparator 3 is stopped, and only the first comparator 2 is operated. Further, the charging / discharging circuit 1 is set to the charge control state by the bias current control circuit 4, and the charging current is supplied to the capacitor Co.
[0026]
During the discharging period of the capacitor Co, the output voltage Vpulse of the first and second comparators 2 and 3 is in a high state (power supply potential). The bias current is supplied, the supply of the bias current to one first comparator 2 is stopped, and only the second comparator 3 is operated. Further, the charge / discharge circuit 1 is set in a discharge control state by the bias current control circuit 4, and current is drawn from the capacitor Co.
[0027]
With the above operation, when the charge / discharge current of the charge / discharge circuit 1 is a constant current, the output voltage Vtri output from the charge / discharge circuit 1 to the output terminal 8 becomes a triangular wave. The output voltage Vpulse output from the first and second comparators 2 and 3 to the output terminal 7 is a rectangular wave. Therefore, the oscillation circuit can output a triangular wave and a rectangular wave simultaneously.
[0028]
FIG. 2 is a circuit diagram showing a specific configuration of the oscillation circuit according to the first embodiment.
The charge / discharge circuit 1 as an output stage includes constant current sources I3, I4, PMOS transistors M11, M13, M15, and NMOS transistors M12, M14, M16. Connected between output terminal and ground. The drains of the PMOS transistor M11 and the NMOS transistor M12 are connected to each other, and the output voltage Vtri at the connection point is output to the output terminal 8. On the charging side, a current mirror is formed by the PMOS transistor M11 and the PMOS transistor M13, and the drain of the PMOS transistor M15, which is a switch, and the charging constant current source I3 are connected to the drain of the diode-connected PMOS transistor M13. ing. On the discharging side, a current mirror is formed by the NMOS transistor M12 and the NMOS transistor M14, and the drain of the NMOS transistor M16, which is a switch, and the constant current source for discharging are connected to the drain of the diode-connected NMOS transistor M14, respectively. I4 is connected.
[0029]
The first comparator (COMP1) 2 uses the NMOS transistor M21 as a constant current source, uses the differential input terminals as the gates of the NMOS transistor M22 and the NMOS transistor M23, and connects the diode-connected PMOS transistors M24 and M25 respectively. A differential stage serving as a differential input load, a PMOS transistor M26 which is a current mirror with the PMOS transistor M24, a PMOS transistor M27 which is a current mirror with the PMOS transistor M25, an NMOS transistor M28 which is a current mirror and an NMOS transistor And an output stage connected to the transistor M29. A connection point between the drains of the PMOS transistor M27 and the NMOS transistor M29 is referred to as an output terminal 7. Further, the gate of the NMOS transistor M22 is connected to the input terminal 5 to which the first reference voltage Vref1 is supplied as an inverting input terminal of the first comparator 2, and the gate of the NMOS transistor M23 is connected to the first comparator 2. 2 is connected to an output terminal 8 to which the output voltage Vtri of the charge / discharge circuit 1 is supplied.
[0030]
The second comparator (COMP2) 3 uses an NMOS transistor M34 in which a PMOS transistor M31 is used as a constant current source, a differential input terminal is used as each gate of the PMOS transistor M32 and the PMOS transistor M33, and a differential input load is diode-connected. , An NMOS transistor M35, a NMOS transistor M36 having a current mirror with the NMOS transistor M34, an NMOS transistor M37 having a current mirror with the NMOS transistor M35, and a PMOS transistor M38 having a current mirror with the PMOS transistor M38. And an output stage connected to the transistor M39. The connection point between the drains of the NMOS transistor M37 and the PMOS transistor M39 is connected to the output terminal 7. Further, the gate of the PMOS transistor M32 is connected to the input terminal 6 to which the second reference voltage Vref2 is supplied as an inverting input terminal of the second comparator 3, and the gate of the PMOS transistor M33 is connected to the second comparator 3. 3 is connected to an output terminal 8 to which the output voltage Vtri of the charge / discharge circuit 1 is supplied.
[0031]
The bias current control circuit 4 connects the output terminals of the first and second comparators (COMP1, COMP2) 2 and 3 to each other, connects the input terminals of the first inverter INV1, and outputs the output of the first inverter INV1. The terminal is connected to the input side of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the gate of the NMOS transistor M43 which is a switch and the gate of the PMOS transistor M44 which is also a switch. The drain of the NMOS transistor M43 is connected to the first constant current source I1, the drain of the NMOS transistor M41 is diode-connected, and the drain of the PMOS transistor M44 is connected to the second constant current source I2. In addition, it is connected to the drain of the PMOS transistor M42 which is diode-connected.
[0032]
Here, the output terminal of the first inverter INV1 is connected to the gate of the PMOS transistor M15 and the gate of the NMOS transistor M16 which are the inputs of the charge / discharge circuit 1 as the output of the bias current control circuit 4. Further, the drain of the NMOS transistor M41 is connected to the gate of the NMOS transistor M21 constituting a constant current source of a differential stage in the first comparator 2. Further, the drain of the PMOS transistor M42 is connected to the gate of the PMOS transistor M31 which forms a constant current source of the differential stage in the second comparator 3. The NMOS transistor M21 and the NMOS transistor M41 form a current mirror, and the PMOS transistor M31 and the PMOS transistor M42 form a current mirror.
[0033]
Note that the first power supply potential is supplied from the positive power supply VDD, and the second power supply potential is ground (ground potential). Also, as in the case of FIG. 1, the first reference voltage Vref1 is set higher than the second reference voltage Vref2.
[0034]
The operation of the oscillation circuit having the above configuration will be described below.
During the charging period of the capacitor Co, the output voltage Vtri of the charge / discharge circuit 1 is lower than the first reference voltage Vref1, so that the output voltage Vpulse of the first comparator (COMP1) 2 is in a low state (ground potential). In this state, in the bias current control circuit 4, the NMOS transistor M43 is turned off and the PMOS transistor M44 is turned on to supply a bias current to the NMOS transistor M21 of the first comparator 2 and the PMOS transistor of the second comparator 3 The supply of the bias current to M31 is stopped.
[0035]
Here, in the NMOS transistor M34 and the NMOS transistor M35 of the second comparator 3, the total capacitance components (gate capacitance, junction capacitance of the drain, stray capacitance due to wiring, etc.) connected to their gate and drain are indicated by broken lines in FIG. Are inevitable as capacitance components C1 and C2 indicated by. Therefore, when the PMOS transistor M31 is turned off, the on / off of the NMOS transistor M34 and the NMOS transistor M35 is controlled by a voltage (= charge / capacitance value) determined by the charges accumulated in these capacitance components C1 and C2. If this voltage is equal to or higher than the threshold voltage of the NMOS transistor M34 and the NMOS transistor M35, they turn on and discharge the accumulated charge. In addition, when the voltages of the capacitance components C1 and C2 decrease to the threshold voltage as the charges are discharged, they are turned off. Therefore, in the second comparator 3, when the supply of the bias current is stopped, the PMOS transistor M31 is turned off, and the drain sides of the NMOS transistor M34 and the NMOS transistor M35 are opened. It turns off almost instantaneously even if it is on. When the NMOS transistors M34 and M35 are turned off, the NMOS transistors M36 and M37 are also turned off. When the NMOS transistor M36 is turned off, the PMOS transistors M38 and M39 are turned off by the same mechanism as the NMOS transistors M34 and M36, and the connection point between the drains of the NMOS transistor M37 and the PMOS transistor M39 becomes high impedance.
[0036]
As described above, when the first comparator 2 operates and the operation of the second comparator 3 stops, the output terminal of the second comparator 3 has a high impedance. In the charge / discharge circuit 1, since the output of the bias current control circuit 4 is in the high state, that is, the level of the positive power supply VDD, the PMOS transistor M15 is turned off, the NMOS transistor M16 is turned on, and a constant current is supplied from the PMOS transistor M11. Then, the capacitor Co is charged with a constant current, and the voltage signal Vtri at the output terminal 8 rises. When the output voltage Vtri of the charging / discharging circuit 1 exceeds the first reference voltage Vref1, the output voltage Vpulse of the first comparator 2 becomes High, that is, the level of the positive power supply VDD, and shifts to the discharging period of the capacitor Co.
[0037]
During the discharging period of the capacitor Co, in the bias current control circuit 4, the PMOS transistor M44 is turned off and the NMOS transistor M43 is turned on, and a bias current is supplied to the PMOS transistor M31 of the second comparator 3 so that the second comparator 3 3 operates, the supply of the bias current to the PMOS transistor M21 of the first comparator 2 is stopped, and the first comparator 2 is stopped. At this time, the output terminal of the first comparator 2 becomes high impedance, and the output voltage Vtri of the charge / discharge circuit 1 is higher than the second reference voltage Vref2, so that the output voltage of the second comparator 3 becomes High. , The output voltage Vpulse is in the High state, that is, the positive power supply VDD level.
[0038]
In the charge / discharge circuit 1, the output of the bias current control circuit 4 is in a low state (ground potential), so that the NMOS transistor M16 is turned off, the PMOS transistor M15 is turned on, and a constant current flows from the NMOS transistor M12. The capacitor Co is discharged at a constant current, and the output voltage Vtri falls. When the output voltage Vtri of the charging / discharging circuit 1 falls below the second reference voltage Vref2, the output voltage Vpulse of the second comparator 3 goes to a low state (ground potential), and shifts to the charging period of the capacitor Co.
[0039]
In the above-described oscillation circuit, by repeating such a charging period and a discharging period, the triangular wave voltage Vtri is output from the output terminal 8 of the charging / discharging circuit 1 and the output terminal 7 of the first and second comparators 2 and 3 is output. Outputs a rectangular wave voltage Vpulse.
[0040]
As described above, in the oscillation circuit according to the first embodiment, as the charge / discharge circuit 1, the gate of the first PMOS transistor M11 whose drain is the output of the charge / discharge circuit 1 is connected to the gate of the second PMOS transistor M13. Is connected to the drain of the second PMOS transistor M13, the gate of the second PMOS transistor M13 and the constant current source I3 for charging are connected, and the drain of the third PMOS transistor M15 and the drain of the second PMOS transistor M13 are connected. The drain is connected, the gate of the third PMOS transistor M15 is connected to the output of the bias current control circuit 4, and the sources of the first, second, and third PMOS transistors M11, M13, and M15 are connected to the first. A first NMOS transistor which is connected to the power supply VDD to form a charge side circuit and has a drain as an output of the charge / discharge circuit 1 The gate of the transistor M12 is connected to the gate of the second NMOS transistor M14, the drain of the second NMOS transistor M14 is connected to the gate of the second NMOS transistor M14 and the constant current source I4 for discharging, and the third The drain of the NMOS transistor M16 is connected to the drain of the second NMOS transistor M14, the gate of the third NMOS transistor M16 is connected to the output of the bias current control circuit 4, and the first, second, and third The source of the NMOS transistors M12, M14, and M16 is connected to the second power supply GND to form a discharge side circuit. The first and second comparators 2 and 2 are connected during the charging and discharging periods of the capacitor Co. 3 during the charging period, focusing on the operation of comparing with the reference voltage in only one of the three cases. Together to comparator operation by supplying a bias current only to over motor 2 has stopped its operation by cutting the bias current of the second comparator 3. In the discharging period, a bias current is supplied only to the second comparator 3 to perform the comparator operation, and the bias current of the first comparator 2 is cut to stop the operation.
[0041]
Therefore, by operating only one of the comparators 2 and 3, the oscillation operation can be performed with about half the current consumption as compared with the oscillation circuit shown in the related art, and the power consumption can be reduced. It becomes.
[0042]
In particular, the bias current control circuit 4 connects the output of the first comparator 2 and the output of the second comparator 3 to the input of the first inverter INV1, and connects the output of the first inverter INV1 to the output of the bias current control circuit 4. As an output, the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output of the second inverter INV2 is connected to the gate of the fourth NMOS transistor M43 and the gate of the fourth PMOS transistor M44. Then, the drain and gate of the fifth NMOS transistor M41 are connected to the drain of the fourth NMOS transistor M43, the first constant current source I1 is connected to the drain of the fifth NMOS transistor M41, and the fifth NMOS transistor The drain of M41 is connected to the first comparator 2 and the bus of the first comparator 2 is connected. Control the ass current, connect the drain and gate of the fifth PMOS transistor M42 to the drain of the fourth PMOS transistor M44, connect the second constant current source I2 to the drain of the fifth PMOS transistor M42, The drain of the fifth PMOS transistor M42 is connected to the second comparator 3 to control the bias current of the second comparator 3, and includes two inverters INV1 and INV2 and MOS transistors M41 to M41. Since the bias current control circuit 4 is composed of only two switches M44, the circuit configuration can be further simplified as compared with the oscillation circuit of Patent Document 2. Further, since the charging / discharging control signal is generated by the bias current control circuit 4 and the first and second comparators 2 and 3, a simpler RS flip-flop like a conventional oscillation circuit is not required. It becomes a circuit configuration.
[0043]
Even if the first power supply VDD or the second power supply GND has a trouble immediately after the power is turned on and the output voltage Vtri at the output terminal 8 is higher than the first reference voltage Vref1, the charging / discharging circuit 1 performs the discharging operation. Starts, and when the output voltage Vtri is lower than the second reference voltage Vref2, the charging operation starts.
[0044]
(Second embodiment)
FIG. 3 is a circuit diagram showing a specific configuration of the oscillation circuit according to the second embodiment.
The configuration of the first and second comparators (COMP1, COMP2) 2, 3 is the same as that of the oscillation circuit of FIG. In the configuration of the charge / discharge circuit 1, the drains of the PMOS transistor M11 and the NMOS transistor M12 are connected as an output stage, and the output voltage Vtri at the connection point is output to the output terminal 8. On the charging side, a current mirror is formed by the PMOS transistor M11 and the PMOS transistor M13, and the drain of the diode-connected PMOS transistor M13 is replaced with the drain of the NMOS transistor M17 instead of the charging constant current source I3 of FIG. Are connected. On the discharging side, a current mirror is formed by the NMOS transistor M12 and the NMOS transistor M14. Are connected.
[0045]
The bias current control circuit 4 connects the output terminals of the first and second comparators (COMP1, COMP2) 2 and 3 to each other and connects the input terminals of the buffer BUF, and the output terminal of the buffer BUF is an NMOS which is a switch. The gate of the transistor M43 is connected to the gate of a PMOS transistor M44, which is also a switch. The drain of the NMOS transistor M43 is connected to the first constant current source I1, the drain of the NMOS transistor M41 is diode-connected, and the drain of the PMOS transistor M44 is connected to the second constant current source I2. In addition, it is connected to the drain of the PMOS transistor M42 which is diode-connected. The drain of the NMOS transistor M41 is connected to the gate of the NMOS transistor M21 constituting a constant current source of a differential stage in the first comparator 2, as in the circuit of FIG. Further, the drain of the PMOS transistor M42 is connected to the gate of the PMOS transistor M31 which forms a constant current source of the differential stage in the second comparator 3. Further, the NMOS transistor M41 and the PMOS transistor M42 are both connected to the gate of the NMOS transistor M17 and the gate of the PMOS transistor M18, which constitute the input terminal of the charge / discharge circuit 1, respectively, as the output terminal of the bias current control circuit 4. Have been. The NMOS transistor M41 forms a current mirror with the NMOS transistor M21 and the NMOS transistor M17, respectively, and the PMOS transistor M42 also forms a current mirror with the PMOS transistor M31 and the PMOS transistor M18.
[0046]
Note that the positive power supply VDD is used as the first power supply, and the second power supply is ground (GND).
The operation of the oscillation circuit having the above configuration will be described below.
[0047]
During the charging period of the capacitor Co, the output voltage Vpulse of the first comparator (COMP1) 2 is in a low state (ground potential), whereby the NMOS transistor M43 of the bias current control circuit 4 is turned off and the PMOS transistor M44 is turned on. . Therefore, a bias current is supplied from the bias current control circuit 4 to the NMOS transistor M21 of the first comparator 2 and a constant current is supplied to the NMOS transistor M17 of the charge / discharge circuit 1 so that the capacitor is supplied with a constant current from the PMOS transistor M11. Charge Co.
[0048]
During the discharging period of the capacitor Co, the output voltage Vpulse of the second comparator (COMP2) 3 is in a high state (power supply potential), whereby the PMOS transistor M44 of the bias current control circuit 4 is turned off and the NMOS transistor M43 is turned on. . Therefore, a constant current is caused to flow from the bias current control circuit 4 to the PMOS transistor M31 of the second comparator 3 at the same time as a constant current is caused to flow to the PMOS transistor M18 of the charge / discharge circuit 1 so that the NMOS transistor M12 extracts a constant current. The capacitor Co is discharged.
[0049]
By repeating such a charging period and a discharging period, in the above-described oscillation circuit, the triangular wave voltage Vtri is output from the output terminal 8 of the charging / discharging circuit 1, and the rectangular voltage is output from the output terminal 7 of the first and second comparators 2 and 3. The wave voltage Vpulse is output.
[0050]
As described above, in the oscillation circuit according to the second embodiment, as the charge / discharge circuit 1, the gate of the first PMOS transistor M11 whose drain is the output of the charge / discharge circuit 1 is connected to the gate of the second PMOS transistor M13. Are connected, the gate of the second PMOS transistor M13 and the drain of the sixth NMOS transistor M17 are connected to the drain of the second PMOS transistor M13, and the gate of the sixth NMOS transistor M17 and the fifth NMOS transistor M41 are connected. And the source of the sixth NMOS transistor M17 is connected to the second power supply GND to form a charging-side circuit, and the drain of the first NMOS transistor M12 whose drain is the output of the charging / discharging circuit 1 is connected. The gate of the second NMOS transistor M14 is connected to the gate of the second NMOS transistor M14. The drain of the transistor M14 is connected to the gate of the second NMOS transistor M14 and the drain of the sixth PMOS transistor M18, the gate of the sixth PMOS transistor M18 is connected to the gate of the fifth PMOS transistor M42, 6, the source of the PMOS transistor M18 is connected to the first power supply VDD to form a discharge side circuit, and the first comparator 2 and the second comparator 3 are connected during the charging period and the discharging period of the capacitor Co. Paying attention to the operation of comparing with the reference voltage by only one of them, in the charging period, the bias current is supplied only to the first comparator 2 to perform the comparator operation, and the bias current of the second comparator 3 is cut. Its operation has stopped. In the discharging period, a bias current is supplied only to the second comparator 3 to perform the comparator operation, and the bias current of the first comparator 2 is cut to stop the operation.
[0051]
By operating only one of the comparators 2 or 3 in this manner, the oscillation operation can be performed with about half the current consumption as compared with the oscillation circuit shown in the related art, and the power consumption can be reduced. Becomes possible.
[0052]
In particular, since the bias current control circuit 4 includes only two switches including the buffer BUF and the MOS transistors M41 to M44, the circuit configuration can be further simplified as compared with the oscillation circuit of Patent Document 2. In addition, since the bias current control circuit 4 and the first and second comparators 2 and 3 generate charge / discharge control signals, an RS flip-flop unlike a conventional oscillation circuit is not required. Circuit configuration.
[0053]
(Third embodiment)
FIG. 4 is a block diagram showing a basic configuration of another oscillation circuit. As shown here, a capacitor Co for charging / discharging a current includes a charging / discharging circuit 1 for controlling the current, and a first comparator (COMP1) 2 for detecting a charging voltage of the capacitor Co with a first reference voltage Vref1. A second comparator (COMP2) 3 for detecting the discharge voltage of the capacitor Co with the second reference voltage Vref2, and a bias current having the output of the first comparator 2 and the output of the second comparator 3 as inputs. And a control circuit 4. The first comparator 2 and the second comparator 3 are respectively composed of differential stages 2a, 3a and output stages 2b, 3b.
[0054]
The non-inverted output from the differential stage 2a of the first comparator 2 and the non-inverted output from the differential stage 3a of the second comparator 3 are connected to the input side of the charge / discharge circuit 1, respectively. Controls the charging and discharging of the capacitor Co by the non-inverted outputs of the differential stages 2a and 3a. The bias current control circuit 4 is connected to the first comparator 2 to control the bias current, and is connected to the second comparator 3 to control the bias current. Here, the first reference voltage Vref1 is supplied from the input terminal 5 to the inverting input terminal of the differential stage 2a of the first comparator 2, and the second reference voltage Vref2 is supplied from the input terminal 6 to the second comparator 3 Are supplied to the inverting input terminal of the differential stage 3a. The output voltage Vpulse of the output terminal 7 is a rectangular wave, and the output voltage Vtri of the output terminal 8 is a triangular wave.
[0055]
Next, the operation of the oscillation circuit shown in FIG. 4 will be described.
Here, the first reference voltage Vref1 supplied to the input terminal 5 is set higher than the second reference voltage Vref2 supplied to the input terminal 6, and the first comparator (COMP1) 2 detects the charging voltage. And the second comparator (COMP2) 3 is used for detecting the discharge voltage. The charge / discharge circuit 1 for charging / discharging the capacitor Co is controlled by the non-inverted output from the differential stage 2a of the first comparator 2 and the non-inverted output from the differential stage 3a of the second comparator 3. .
[0056]
Regarding the operation of the first and second comparators 2 and 3 during charging of the capacitor Co, the output voltage Vtri of the charge / discharge circuit 1 to the output terminal 8 is lower than the first reference voltage Vref1, The resulting output voltage Vpulse of the first comparator 2 is in a low state (ground potential), but when the capacitor Co is charged by the charge / discharge circuit 1 and the output voltage Vtri of the charge / discharge circuit 1 exceeds the first reference voltage Vref1. The output voltage Vpulse of the first comparator 2 changes to a high state (power supply potential).
[0057]
Regarding the operation of the first and second comparators 2 and 3 when the capacitor Co is discharged, since the output voltage Vtri of the charge / discharge circuit 1 is higher than the second reference voltage Vref2, the output voltage Vpulse of the second comparator 3 Is in a High state (power supply potential), but when the capacitor Co is discharged by the charge / discharge circuit 1 and the output voltage Vtri of the charge / discharge circuit 1 falls below the second reference voltage Vref2, the output voltage Vpu1se of the second comparator 3 Changes to a low state (ground potential).
[0058]
During the charging period of the capacitor Co, the output voltage Vpulse of the first and second comparators 2 and 3 is in a low state (ground potential). The bias current is supplied, the supply of the bias current to one second comparator 3 is stopped, and only the first comparator 2 is operated. Then, a control signal for the charge / discharge circuit 1 is output by the non-inverted output from the differential stage 2a of the first comparator 2, and the charge / discharge circuit 1 is set to a charge control state to supply a charge current to the capacitor Co.
[0059]
During the discharging period of the capacitor Co, the output voltage Vpulse of the first and second comparators 2 and 3 is in a high state (power supply potential). The bias current is supplied, the supply of the bias current to one first comparator 2 is stopped, and only the second comparator 3 is operated. Then, a control signal for the charging / discharging circuit 1 is output by the non-inverted output from the differential stage 3a of the second comparator 3, and the charging / discharging circuit 1 is set to a discharge control state to draw a current from the capacitor Co. When the charge / discharge current of the charge / discharge circuit 1 is a constant current, the output voltage Vtri of the charge / discharge circuit 1 becomes a triangular wave.
[0060]
By the above operation, the output voltage Vpulse of the first and second comparators 2 and 3 becomes a rectangular wave, and thus an oscillation circuit capable of simultaneously outputting a triangular wave and a rectangular wave.
[0061]
FIG. 5 is a circuit diagram showing a specific configuration of the oscillation circuit according to the third embodiment.
The charge / discharge circuit 1 includes a PMOS transistor M11 and an NMOS transistor M12 having drains connected to each other, and outputs an output voltage Vtri at a connection point between the PMOS transistor M11 and the NMOS transistor M12 to an output terminal 8. A charge / discharge capacitor Co is connected between the output terminal 8 of the charge / discharge circuit 1 and the ground.
[0062]
The differential stage 2a of the first comparator (COMP1) 2 uses a NMOS transistor M21 as a constant current source, a differential input terminal as each gate of an NMOS transistor M22 and an NMOS transistor M23, and a diode-connected PMOS transistor M24. And the PMOS transistor M25 as a differential input load, and the drain of the PMOS transistor M24 is supplied to the charge / discharge circuit 1 as its non-inverted output. The output stage 2b of the first comparator 2 includes a PMOS transistor M26 which is a current mirror with the PMOS transistor M24, a PMOS transistor M27 which is a current mirror with the PMOS transistor M25, and an NMOS transistor M28 which is connected with the current mirror. And an NMOS transistor M29. The connection point between the drains of the PMOS transistor M27 and the NMOS transistor M29 is connected to the output terminal 7. Further, the gate of the NMOS transistor M22 is connected to the input terminal 5 to which the first reference voltage Vref1 is supplied as an inverting input terminal, and the gate of the NMOS transistor M23 serves as a non-inverting input terminal of the first comparator 2. The output terminal 8 to which the output voltage Vtri of the charge / discharge circuit 1 is supplied is connected.
[0063]
The non-inverting output terminal of the differential stage 2a is constituted by the drain of the PMOS transistor M24, and is connected to the gate of the PMOS transistor M11 of the charge / discharge circuit 1. Here, the PMOS transistor M11 of the charge / discharge circuit 1 and the PMOS transistor M24 of the first comparator 2 have a current mirror configuration.
[0064]
The differential stage 3a of the second comparator (COMP2) 3 includes a PMOS transistor M31 as a constant current source, a differential input terminal as a gate of each of the PMOS transistor M32 and the PMOS transistor M33, and a diode-connected NMOS transistor M34. And the NMOS transistor M35 as a differential input load, and the drain of the NMOS transistor M34 is supplied to the charge / discharge circuit 1 as its non-inverted output. The output stage 3b of the second comparator 3 includes an NMOS transistor M36 which is a current mirror with the NMOS transistor M34, an NMOS transistor M37 which is a current mirror with the NMOS transistor M35, and a PMOS transistor M38 which is current mirror connected. And a PMOS transistor M39. The connection point between the drains of the NMOS transistor M37 and the PMOS transistor M39 is connected to the output terminal 7. Further, the gate of the PMOS transistor M32 is connected to the input terminal 6 to which the second reference voltage Vref2 is supplied as an inverting input terminal of the differential stage 3a, and the gate of the PMOS transistor M33 is connected to the differential stage 3a. The non-inverting input terminal is connected to the output terminal 8 to which the output voltage Vtri of the charge / discharge circuit 1 is supplied.
[0065]
The non-inverting output terminal of the differential stage 3a is constituted by the drain of the PMOS transistor M34, and is connected to the gate of the NMOS transistor M12 of the charge / discharge circuit 1. Here, the NMOS transistor M12 of the charge / discharge circuit 1 and the NMOS transistor M34 of the second comparator 3 have a current mirror configuration.
[0066]
The bias current control circuit 4 connects the output terminals of the first and second comparators (COMP1, COMP2) 2 and 3 to each other and connects the input terminals of the buffer BUF, and the output terminal of the buffer BUF is an NMOS which is a switch. The gate of the transistor M43 is connected to the gate of a PMOS transistor M44, which is also a switch. The drain of the NMOS transistor M43 is connected to the first constant current source I1, the drain of the NMOS transistor M41 is diode-connected, and the drain of the PMOS transistor M44 is connected to the second constant current source I2. In addition, it is connected to the drain of the PMOS transistor M42 which is diode-connected. The drain of the NMOS transistor M41 is connected to the gate of the NMOS transistor M21 forming a constant current source in the differential stage 2a of the first comparator 2. Further, the drain of the PMOS transistor M42 is connected to the gate of the PMOS transistor M31 constituting a constant current source in the differential stage 3a of the second comparator 3. The NMOS transistor M41 forms a current mirror with the NMOS transistor M21, and the PMOS transistor M42 also forms a current mirror with the PMOS transistor M31.
[0067]
The operation of the oscillation circuit having the above configuration will be described below.
During the charging period of the capacitor Co, the output voltage Vtri of the charge / discharge circuit 1 is lower than the first reference voltage Vref1, so that the output voltage Vpulse of the first comparator (COMP1) 2 is in a low state (ground potential). In this state, in the bias current control circuit 4, the NMOS transistor M43 is turned off and the PMOS transistor M44 is turned on to supply a bias current to the NMOS transistor M21 of the first comparator 2 and the PMOS transistor of the second comparator 3 The supply of the bias current to M31 is stopped.
[0068]
Therefore, the first comparator 2 operates, and the operation of the second comparator 3 stops. Here, the output terminal of the second comparator 3 has a high impedance. In the charge / discharge circuit 1, a bias current flows through the NMOS transistor M21 of the first comparator 2, and a constant current also flows through the PMOS transistor M24. Therefore, a current proportional to the current of the PMOS transistor M24 flows through the PMOS transistor M11. . As a result, the capacitor Co is charged with the constant current, and the voltage signal Vtri at the output terminal 8 rises. When the output voltage Vtri of the charging / discharging circuit 1 exceeds the first reference voltage Vref1, the output voltage Vpulse of the first comparator 2 becomes High, that is, the level of the positive power supply VDD, and shifts to the discharging period of the capacitor Co.
[0069]
At this time, in the first comparator 2, the bias current of the NMOS transistor M21 also flows to the NMOS transistor M23, the current flowing to the PMOS transistor M24 decreases, and the charging current from the PMOS transistor M11 of the charge / discharge circuit 1 decreases. .
[0070]
During the discharging period of the capacitor Co, in the bias current control circuit 4, the PMOS transistor M44 is turned off and the NMOS transistor M43 is turned on, and a bias current is supplied to the PMOS transistor M31 of the second comparator 3 so that the second comparator 3 3 operates, the bias current to the PMOS transistor M21 of the first comparator 2 is cut, and the first comparator 2 stops. At this time, the output terminal of the first comparator 2 becomes high impedance, and the output voltage Vtri of the charge / discharge circuit is higher than the second reference voltage Vref2, so that the output voltage of the second comparator 3 becomes High. The output voltage Vpulse is in the High state, that is, the positive power supply VDD level.
[0071]
Further, in the charging / discharging circuit 1, since the bias current of the PMOS transistor M31 of the second comparator 3 flows through the NMOS transistor M34, a current proportional to the NMOS transistor M34 flows through the NMOS transistor M12 to discharge the capacitor Co with a constant current. The output voltage Vtri decreases. When the output voltage Vtri of the charging / discharging circuit 1 falls below the second reference voltage Vref2, the output voltage Vpulse of the second comparator 3 goes to a low state (ground potential), and shifts to the charging period of the capacitor Co.
[0072]
At this time, in the second comparator 3, the bias current of the PMOS transistor M31 also flows to the PMOS transistor M33, the current flowing to the NMOS transistor M34 decreases, and the discharge current from the NMOS transistor M12 of the charge / discharge circuit 1 decreases. .
[0073]
By repeating such a charging period and a discharging period, a triangular wave is output from the output terminal 8 of the charge / discharge circuit 1 in the above-described oscillation circuit, and a rectangular wave voltage is output from the output terminals 7 of the first and second comparators 2 and 3. Vpulse outputs.
[0074]
As described above, the oscillation circuit according to the third embodiment includes, as the charge / discharge circuit 1, the first PMOS transistor M11 whose drain is the output of the charge / discharge circuit 1, and the source of the first PMOS transistor M11 is connected. There is a first NMOS transistor M12 connected to the first power supply VDD to form a charge side circuit and having a drain as an output of the charge / discharge circuit 1, and a source of the first NMOS transistor M12 is connected to the second power supply GND. And the discharge side circuit is connected to the first comparator 2 and the second comparator 3 to compare with the reference voltage during the charging period and the discharging period of the capacitor Co. Paying attention, during the charging period, the bias current is supplied only to the first comparator 2 to perform the comparator operation, and the bias current of the second comparator 3 is supplied. It has stopped its operation to cut. In the discharging period, a bias current is supplied only to the second comparator 3 to perform the comparator operation, and the bias current of the first comparator 2 is cut to stop the operation.
[0075]
Therefore, by operating only one of the comparators 2 and 3, the oscillation operation can be performed with about half the current consumption as compared with the oscillation circuit shown in the related art, and the power consumption can be reduced. It becomes.
[0076]
In particular, since the bias current control circuit 4 includes only two switches including the buffer BUF and the MOS transistors M41 to M44, the circuit configuration can be further simplified as compared with the oscillation circuit of Patent Document 2. In addition, since the bias current control circuit 4 and the first and second comparators 2 and 3 generate charge / discharge control signals, an RS flip-flop unlike a conventional oscillation circuit is not required. Circuit configuration.
[0077]
【The invention's effect】
As described above, according to the oscillation circuit of the present invention, low power consumption and simplification of the circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of an oscillation circuit according to the present invention.
FIG. 2 is a circuit diagram showing a specific configuration of the oscillation circuit according to the first embodiment.
FIG. 3 is a circuit diagram showing a specific configuration of an oscillation circuit according to a second embodiment.
FIG. 4 is a block diagram showing a basic configuration of another oscillation circuit.
FIG. 5 is a circuit diagram showing a specific configuration of an oscillation circuit according to a third embodiment.
FIG. 6 is a circuit diagram showing a configuration of a conventional oscillation circuit.
FIG. 7 is a circuit diagram showing an equivalent circuit of the oscillation circuit of FIG. 6 in a free-run operation mode.
FIG. 8 is a timing waveform chart for explaining the operation of the equivalent circuit in the free-run operation mode.
FIG. 9 is a diagram showing a basic configuration of an oscillation circuit according to another related art.
[Explanation of symbols]
1 Charge / discharge circuit
2 First comparator (COMP1)
3 Second comparator (COMP2)
4 Bias current control circuit
5, 6 input terminals
7, 8 output terminal
VDD First power supply (positive power supply voltage)
Co capacitor
Vref1 First reference voltage
Vref2 Second reference voltage
I1 First constant current source
I2 Second constant current source
I3 constant current source for charging
I4 constant current source for discharging
Vtri Output voltage of charge / discharge circuit (triangular wave output)
Vpulse output voltage (square wave output)
INV1 First inverter
INV2 Second inverter
BUF buffer
M11 to M17, M21 to M29, M31 to M39, M41 to M44 PMOS transistor or NMOS transistor

Claims (9)

In an oscillation circuit that can output a triangular wave and a rectangular wave simultaneously by charging and discharging a capacitor,
A charging and discharging circuit for charging and discharging the capacitor;
A first comparator for detecting a charging voltage of the capacitor;
A second comparator for detecting a discharge voltage of the capacitor;
A bias current control circuit that inputs the output of the first comparator and the output of the second comparator and connects to the charge / discharge circuit, and controls the charge / discharge of the capacitor;
Wherein the bias current control circuit controls the charge / discharge period of the capacitor by cutting bias currents of the first and second comparators and disabling them alternately. Characteristic oscillation circuit. 2. The oscillation circuit according to claim 1, wherein when one output of the first and second comparators is not invalidated, the other output is invalidated. 3. The oscillation circuit according to claim 1, wherein the bias current control circuit invalidates the output of the first and second comparators by alternately setting the outputs to high impedance. The bias current control circuit,
An output of the first comparator and an output of the second comparator are connected to an input of a first inverter circuit, and an output of the first inverter circuit is used as an output of the bias current control circuit;
Connecting an output of the first inverter circuit to an input of a second inverter circuit, connecting a gate of a fourth NMOS transistor and a gate of a fourth PMOS transistor to an output of the second inverter circuit, A drain and a gate of a fifth NMOS transistor are connected to a drain of the fourth NMOS transistor, a first constant current bias source is connected to a drain of the fifth NMOS transistor, and a drain of the fifth NMOS transistor is connected to the drain of the fifth NMOS transistor. Connected to the first comparator to control a bias current of the first comparator;
The drain and the gate of a fifth PMOS transistor are connected to the drain of the fourth PMOS transistor, the second constant current bias source is connected to the drain of the fifth PMOS transistor, and the drain of the fifth PMOS transistor is connected. 4. The oscillation circuit according to claim 1, wherein the oscillation circuit is connected to the second comparator to control a bias current of the second comparator. The charge and discharge circuit,
A gate of a second PMOS transistor is connected to a gate of a first PMOS transistor having a drain as an output of the charge / discharge circuit, and a gate of the second PMOS transistor is connected to a drain of the second PMOS transistor for charging. A constant current source, a drain of a third PMOS transistor and a drain of the second PMOS transistor, a gate of the third PMOS transistor and an output of the bias current control circuit, Connecting the sources of the first, second, and third PMOS transistors to a first power supply to form a charging-side circuit;
A gate of a second NMOS transistor is connected to a gate of a first NMOS transistor having a drain as an output of the charge / discharge circuit, and a drain of the second NMOS transistor is connected to a gate of the second NMOS transistor for discharging. Connecting a constant current source, connecting a drain of a third NMOS transistor to a drain of the second NMOS transistor, connecting a gate of the third NMOS transistor to an output of the bias current control circuit, 5. The oscillation circuit according to claim 1, wherein the sources of the first, second, and third NMOS transistors are connected to a second power supply to form a discharge side circuit. . The charge and discharge circuit,
The gate of a second PMOS transistor is connected to the gate of a first PMOS transistor whose drain is the output of the charge / discharge circuit, and the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor. Connecting the drain of the fifth NMOS transistor, connecting the gate of the sixth NMOS transistor to the gate of the fifth NMOS transistor, and connecting the source of the fifth NMOS transistor to a second power supply; Configure the charging side circuit,
The gate of a second NMOS transistor is connected to the gate of a first NMOS transistor whose drain is the output of the charge / discharge circuit, and the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor. Connecting the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor and the gate of the fifth PMOS transistor, and connecting the source of the sixth PMOS transistor to a first power supply; The oscillation circuit according to claim 4, wherein a discharge side circuit is configured. The bias current control circuit,
Connecting the output of the first comparator and the output of the second comparator to the input of a buffer circuit, connecting the gate of a fourth NMOS transistor and the gate of a fourth PMOS transistor to the output of the buffer circuit, A drain and a gate of a fifth NMOS transistor are connected to a drain of the fourth NMOS transistor, a first constant current bias source is connected to a drain of the fifth NMOS transistor, and a drain of the fifth NMOS transistor is connected. Is connected to the first comparator to control a bias current of the first comparator,
The drain and the gate of a fifth PMOS transistor are connected to the drain of the fourth PMOS transistor, the second constant current bias source is connected to the drain of the fifth PMOS transistor, and the drain of the fifth PMOS transistor is connected. 4. The oscillation circuit according to claim 1, wherein the oscillation circuit is connected to the second comparator to control a bias current of the second comparator. The first and second comparators each include a differential stage and an output stage,
The bias current control circuit controls the bias currents of the first comparator and the second comparator, and outputs the non-inverted output of the differential stage of the first comparator and the non-inverted output of the differential stage of the second comparator. 4. The oscillation circuit according to claim 1, wherein an inverted output is input to said charge / discharge circuit to control a charge / discharge period of said capacitor. The charge and discharge circuit,
There is a first PMOS transistor having a drain as an output of the charge / discharge circuit, and a source of the first PMOS transistor is connected to the first power supply to form a charge side circuit;
3. A discharge-side circuit comprising a first NMOS transistor having a drain as an output of the charge / discharge circuit, and a source of the first NMOS transistor connected to the second power supply. 8. The oscillation circuit according to 8.

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