JPH06140884A - Cmos-type semiconductor cr oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce current consumption permitted to flow in an oscillation circuit by changing-over a differential circuit and two high/low reference voltages which are inputted to the differential circuit by means of a differential output signal outputted from an inverter string connected to the differential circuit. CONSTITUTION:Unless an electric load is charged to a time-limit capacitor C as the initial state of oscillation, the differential output signal SZ becomes an L level and the reverse differential output signal SZR outputted form an inverter 11 becomes an H level so that the transfer gate TG 1 of a reference voltage change-over part 2 is turned on and the TG 2 is turned off. Therefore the reference high voltage V1 is inputted to the input end - of the differential circuit Z1, the charge/discharge SW transistor(Tr) P is turned on and the electric load is charged in the time-limit capacitor C. When the oscillation voltage SN1 becomes more than the voltage V1, the inverters 11 and 12 are inverted. Therefore, the gate TG 1 is turned off, TG 2 is turned on Zd Tr P is turned off. Thus, the electric load of the capacitor C starts discharging through a time-limit resistor R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor CR oscillator circuit.

[0002]

2. Description of the Related Art A conventional CMOS semiconductor CR oscillator circuit has reference voltage dividing resistors R1 to R3 as shown in FIG.
Are connected in series between the high voltage terminal TH and the low voltage terminal TL, and the reference high voltage V1 generated at the nodes N1 and N2 by voltage division is applied to the non-inverting input terminal + of the first differential circuit Z1. Further, the reference low voltage V2 is input to the non-inverting input terminal + of the second differential circuit Z2.

In the charging / discharging section 1, one end of a time constant element 1tc in which a time delay capacitor C and a time delay resistor R are connected in parallel is a low voltage terminal TL, and the other end is a node N and a discharge charge P-type transistor P. Is connected to the high voltage terminal TH via.

The node N of the charging / discharging unit 1 is connected to both differential circuits Z1, Z.
2 and the output signal of the first differential circuit Z1 is connected to the gate of the P-type transistor forming the first inverter I1, and the output signal of the second differential circuit Z2 is connected to the inverting input terminal −2 of the second differential circuit Z1. The signals are input to the gates of N-type transistors that form the inverter I1.

The output terminal of the inverter I1 has two CMOs.
It is connected to the oscillation output terminal To via the latch circuit 3 composed of the S inverter and the second inverter I2, and is also connected to the gate of the P-type transistor P of the charging / discharging unit 1.

Next, the operation of the circuit will be described with reference to the waveform diagram of each signal in FIG. First, as the initial state of oscillation, when the time-delay capacitor C is not charged,
Since both the differential circuits Z1 and Z2 output "H" level, the oscillation output signal So is "L" level, the P-type transistor P of the charging / discharging unit 1 is turned on, and the time-delay capacitor from the high voltage terminal TH. The C starts to be charged.

Next, the oscillation voltage SN2 input to the inverting input terminals-of both differential circuits Z1 and Z2 is the reference low voltage V2.
With the above, the output signal of the second differential circuit Z2 is "L".
The level becomes high and the two transistors of the inverter I1 are both turned off, but the oscillation output signal So, which is the voltage at the node N, holds the previous level by the latch circuit 3.

Next, when the oscillation voltage SN2 rises above the reference high voltage V1, both differential circuits Z1 and Z2 are both "
Since the L "level is output, the oscillation output signal So becomes the" H "level, the P-type transistor P is turned off, and the electric charge charged in the time delay capacitor C is discharged through the time delay resistor R.

Next, when the oscillation voltage SN2 falls below the reference high voltage V1, the output signal of the differential circuit Z1 is "H".
The level becomes high, and the two transistors of the inverter I1 are both turned off, but the latch circuit 3 holds the previous state.

Finally, when the oscillation voltage SN2 falls below the reference high voltage V1, the output signals of both differential circuits Z1 and Z2 both output "H" level, so that the P-type transistor P is turned on. After that, since the above-mentioned state is automatically repeated, the continuous oscillation output signal So is output to the oscillation output terminal To.
Occurs.

[0011]

The conventional CMOS semiconductor CR oscillator circuit has two differential circuits, so that the current consumption of the circuit is large, and the difference in the offset potential between the two differential circuits in the semiconductor manufacturing process is caused. There is a drawback that the oscillation frequency varies due to the variation.

[0012]

In the CMOS type semiconductor CR oscillator circuit of the present invention, a charge / discharge switch transistor is connected in series via a node N to one end of a time constant element in which a time delay capacitor and a time delay resistor are connected in parallel. Both ends of the charging / discharging part are connected between a high voltage terminal and a low voltage terminal with the other end of the time constant element being on the low voltage side, and the node N is connected to one input terminal of a differential circuit to obtain a reference voltage. Voltage or low reference voltage is input to the other input terminal of the differential circuit, and the differential output signal of the differential circuit is fed back to the gate of the charge / discharge switch transistor through an inverter string and also oscillates. In a CMOS type semiconductor CR oscillation circuit output to a terminal, an N type transistor and a P type
A reference voltage switching unit having an analog switching element or an inverter formed by a transistor is provided, and the reference high voltage and the reference low voltage are input to the reference voltage switching unit, and the two are controlled by the differential output signal. The voltage is switched to any one of the voltages and input to the other input terminal of the differential circuit.

[0013]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. The CMOS semiconductor CR oscillator circuit of this embodiment has a high voltage terminal T
Charge / discharge unit 1 and reference voltage dividing resistors R1 to R3 inserted between H and the low voltage terminal TL, and oscillation output terminal T
The CMOS inverter I2 connected to o is the same as that of the conventional circuit shown in FIG.
The reference voltage switching unit 2 is inserted between the connection nodes N1 and N2 of R3 to R3 and the inverting input terminal − of the differential circuit Z1.

That is, the time delay capacitor C and the time delay resistor R
Both ends of the charging / discharging portion 1 in which the drain of the charging / discharging SW P-type transistor P is connected to the node N on the high voltage side of the time constant element 1tc in which the and are connected in parallel, the source of the transistor P is connected to the high voltage terminal TH, The other end of the time constant element 1tc is connected to the low voltage terminal TL.

The oscillating voltage SN1 at the node N is input to the non-inverting input terminal + of the differential circuit Z1 and the differential output signal S output by the input.
Z is supplied to the oscillation output terminal To through the first inverter I1, the node N3, and the second inverter I2, and is also feedback-connected to the gate of the transistor P.

A connection node N of the reference voltage dividing resistors R1 to R3 connected between the high voltage terminal TH and the low voltage terminal TL.
The reference high voltage V1 and the reference low voltage V2 generated at 1 and N2 are selected by the differential output signal SZ via the reference voltage switching unit 2 and supplied to the inverting input terminal − of the differential circuit Z1.

The reference voltage switching section 2 is composed of two transfer gates TG1 and T1 formed of CMOS transistors.
G2, whose gates are controlled by a pair of differential output signal SZ and inverted differential output signal SZR, respectively.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the waveform diagrams of the signals shown in FIG. First, in the initial state of oscillation, when the time delay capacitor C is not charged, the differential output signal SZ becomes "L" level and the inverted differential output signal SZR output from the inverter I1 is "H".
Since it becomes the level, the transfer gate TG1 of the reference voltage switching unit 2 is turned on and the transfer gate TG2 is turned off.

Therefore, the reference high voltage V1 is input to the inverting input terminal-of the differential circuit Z1, the charging / discharging SW P-type transistor P is turned on, and the time delay capacitor C starts to be charged from the high voltage terminal TH.

Next, when the oscillation voltage SN1 which is the voltage at the node N input to the non-inverting input terminal + of the differential circuit Z1 rises above the reference high voltage V1, the differential circuit Z1 outputs "H" level, The inverters I1 and I2 are also inverted.

Therefore, the first transfer gate TG1
Is off, the second transfer gate TG2 is on,
The reference low voltage is switched and input to the inverting input terminal − of the differential circuit Z1.

Further, since the inverter I2 outputs the oscillation output signal So of "H" level, the transistor P is turned off. Therefore, the electric charge charged in the time delay capacitor C starts discharging through the time delay resistor R.

Further, when the input voltage SN1 at the non-inverting input terminal + of the differential circuit Z1 falls below the reference low voltage V2, the differential output signal SZ becomes "L" level and the inverters I1 and I2 are also inverted.

Therefore, the first transfer gate TG1
Is on, the second transfer gate TG2 is off,
The reference high voltage V1 is switched and input to the inverting input terminal-.

Since the oscillation output signal So becomes "L" level, the transistor P is turned on. Therefore, the time delay capacitor C starts charging again. After that, oscillation is continued by automatically repeating the above-mentioned state.

Further, the number of inverter rows in FIG. 1 may be increased, and an N-type transistor may be used instead of the P-type transistor P for charging / discharging SW depending on the polarity of the power source, and the same effect can be obtained.

In the circuit of this embodiment, two conventional differential circuits are combined into one, and the consumption current iC1 flowing through the circuit is reduced. Further, the oscillation frequency does not fluctuate due to the difference in offset potential between the two differential circuits. Furthermore, the conventional differential circuit Z
Since 2 and the latch circuit 3 are eliminated, the number of transistors is reduced by 7 and the chip can be miniaturized.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. In this embodiment, the reference voltage switching unit 2 of the first embodiment of FIG. 1 is replaced with an inverter type reference voltage switching unit 2a in which drains of P-type transistors and N-type transistors are connected. The configuration other than that is the same as the circuit of FIG.

Also in this embodiment, the differential output signal SZ
Is at the "L" level, the P-type transistor of the CMOS inverter is turned on and the N-type transistor is turned off, so that the reference high voltage V1 is input to the inverting input terminal-.

When the differential output signal SZ is at "H" level, the P-type transistor of the inverter is turned off and the N-type transistor is turned on, and the reference low voltage is input to the inverting input terminal-. Therefore, as in the first embodiment, oscillation is performed by charging and discharging the time delay capacitor C, but this embodiment has the advantage that the number of transistors in the circuit is reduced by 9 and the chip can be further downsized.

[0031]

As described above, according to the present invention, the high and low reference voltages input to the differential circuit are switched by the differential output signal output from the differential circuit and the inverter train connected thereto. The conventional two differential circuits are combined into one, and the current consumption flowing through the oscillator circuit is reduced.

Further, the fluctuation of the oscillation frequency due to the difference between the offset potentials of the two differential circuits is eliminated. Further, since one differential circuit and the latch circuit are eliminated, the number of transistors is reduced and the chip layout area can be reduced and downsized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a waveform diagram of current and voltage for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a conventional CMOS semiconductor CR oscillator circuit.

5 is a waveform diagram of current and voltage for explaining the operation of the circuit of FIG.

[Explanation of symbols]

 1 Charge / Discharge Unit 1tc Time Constant Element 2, 2a Reference Voltage Switching Unit C Time Capacitor I1, I2 CMOS Inverter iC1 Circuit Current Consumption N, N1 to N3 Nodes P P Transistor for Charge / Discharge SW R Time Resistor R1 to R3 Reference Components Piezoresistor SN1 Oscillation voltage So Oscillation output voltage SZ Differential output signal SZR Differential output inversion signal To Oscillation output terminal TH High voltage terminal TL Low voltage terminal TG1, TG2 Transfer gate V1 Reference high voltage V2 Reference low voltage VH High voltage VL Low Voltage Z1 Differential circuit − Inverting input terminal + Non-inverting input terminal

Claims (1)

[Claims] 1. A charging / discharging portion in which a charging / discharging switch transistor is connected in series via a node N to one end of a time constant element in which a time-constant capacitor and a time-limit resistor are connected in parallel is connected to the other end of the time-constant element. The low voltage side is connected between the high voltage terminal and the low voltage terminal, the node N is connected to one input terminal of the differential circuit, and the reference high voltage or the reference low voltage is connected to the other input terminal of the differential circuit. And a differential output signal of the differential circuit is fed back to the gate of the charging / discharging switch transistor through an inverter array and is output to an oscillation output terminal.
In the R oscillator circuit, a reference voltage switching unit having an analog switching element or an inverter formed of an N-type transistor and a P-type transistor is provided, and the reference high voltage and the reference low voltage are input to the reference voltage switching unit, A CMOS characterized in that it is controlled by a differential output signal and switched to one of the two voltages and input to the other input terminal of the differential circuit.
Type semiconductor CR oscillator circuit.