JPS62117411A - Delay circuit - Google Patents

Abstract

PURPOSE:To constitute a delay circuit having a function which widens pulse widths and, at the same time, to output pulse signals having optional widths, by combining three CMS inverters and a capacitor connected with the output terminals of the inverters. CONSTITUTION:When the initial state of an input signal is at a low level '0', the node A of the output of a CMOS inverter 1 becomes high in level VCC and a capacitor 4 is set to its charged state, and then, an output signal becomes low in level '0'. When the input signal changes to a high level VCC thereafter, an output signal quickly becomes a high level VCC. At this time, the charge of the capacitor 4 is discharged. When the input signal again changes to the low level '0', TP 10 and TP 30 are turned on and it is started to charge the capacitor 4 with electric charges. Therefore, the electric potential at the node A slowly changes to a high level VCC and, when reaching the threshold potential of another CMOS inverter 2, the output signal changes to a low level '0'. In other words, a large delayed time is obtained at the dropped end of the pulse of the input signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a delay circuit, particularly a complementary type (hereinafter referred to as CMO8).
This invention relates to a delay circuit using an inverter.

[Conventional technology]

Conventionally, this type of delay circuit, particularly a delay circuit which receives a pulse signal and whose purpose is to widen the pulse width, is usually constructed as shown in FIG. .

FIG. 4 is a circuit diagram showing an example of a conventional delay circuit. In the same figure, an input signal is applied to one input terminal of a two-person NOR circuit 10, and is also applied to an inverter row 41 connected in cascade in even number stages (here, two stages), and the output of the inverter row 41 is is connected to the other input end of the two-person NOR circuit 40. The output of the two-person NOR circuit 40 is further connected to an inverter 42 to generate an output signal.

FIG. 5 is a timing chart showing the operation of one example of use of the delay circuit of FIG. 4. Inverter row 4 in Figure 4
The waveform at node B of one output is expressed by shifting the pulse of the input signal by the delay time caused by the inverter array 41, and by performing a NOR logic between this signal and the input signal, the pulse width is widened, and the pulse width is further increased by the inverter array. 42, it is possible to create an output signal with the same phase as the input signal and an expanded pulse width.In addition, when the input signal is a pulse of opposite phase according to the conventional circuit 3 mentioned above, the 41st Noah I'ii in ゛4
By replacing the J path portion with a NAND I''J path, the pulse width can be similarly widened.

[Problems to be solved by the invention] Conventionally, the extension circuit is used to widen the pulse width, but CMO
When configured with three circuits, at least 10 transistors must be used. Therefore, in 1, SI, which requires a higher degree of integration, there is a drawback that the pattern area becomes excessively large.

[Means for solving problems]

The delay circuit of the present invention is configured such that the first CM to which the input signal is applied
an OS inverter, a second CMOS inverter cascade-connected to the first CMOS inverter and generating an output signal;
A third cM whose potential supply source is the output of the OS inverter.
08 inverter and a capacitive load connected to the output terminal of the third CMOS inverter.

[Example 1] Next, the present invention will be explained with reference to the first country to the third country L7.

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a timing chart showing the operation of the first embodiment, and Fig. 3 is a circuit diagram showing a second embodiment of the invention. be.

The first embodiment is as shown in FIG. 2nd, 3rd
CMOS inverters 1, 2.3, and a capacitor connected to the output terminal of MOS inverter 3 (hereinafter referred to as C) 4
It consists of (Input signals are input to both the MMOS inverters 1 and 3, and the CMOS inverter 2 is connected in cascade with the CMOS inverter through node A to generate an output signal. This is the power supply potential supply source for MO8 inverter 3.CMOS inverters 1, 2, and 3 each have 1) channel MOsFET.
(hereinafter referred to as ``Ding゛p'') and N-channel MO8FET (hereinafter referred to as ``''
For example, the CMOS inverter 1 consists of "rP]o and TN1.]6.Next, the operation of the first embodiment will be explained with reference to FIG. 2.

When the initial state of the input signal is low level O, Tp 10
．． Tr 30 is on, TN 11. , TN 3
] is in the off state, node A of the CMOS inverter 1 output is at high level VCC, and C4 is in the charging state through T''r30. Also, since TN21 is in the on state and Tl2O is in the off state, the output The signal is at low level O, then the input signal goes high and the bell ■
When it changes to cc, TN 1 ] and Tr follow it.
2(l and 'D) N31 turns on, and the output signal quickly becomes a high level ■Cc.At this time, the electric charge charged in C4 is quickly discharged to the ground potential because TN31 turns on. When the input signal changes to low level 0 again, TPIO and TP30 turn on, and C4 starts to be charged. Therefore, the potential at node A suddenly shifts to high level VCC, and the CM OS Inverter 2
When the voltage reaches the threshold potential of 24, the output signal changes to low level 0. In other words, according to this embodiment,
At the rising edge of the input signal pulse, the delay time is small, and at the falling edge of the input signal pulse, the output signal falls after a delay time corresponding to the capacitive load, so a large delay time can be obtained.

Next, a second embodiment will be described in which a pulse signal having a phase opposite to the above input signal is used as an input signal.

The second embodiment differs from the first embodiment described above in the third embodiment.
As shown in the figure, this is the point where the node A' of the output of the CMC inverter 1 is connected as the ground potential supply source of the CMOS inverter 3. The circuit operation of the second embodiment is as follows:
TPIO and TNl, 1, Tp20 and TN 21. ,
This can be explained by replacing Tp 30 and '1'' N31, charging and discharging, and power supply and ground, respectively, the delay time at the 1-4 rising edge of the input signal pulse is large, and the delay time at the falling edge of the input signal pulse is large. It is clear that the time will be short.6 [Effect of the invention] As explained above, the Kiito Akira can generate pulses as well as the conventional example by using only 0 tow/sisters and 1 capacitor. It is possible to configure a delay circuit with the function of increasing the width, and by appropriately adjusting the capacitance and the size of the t1 load, it is possible to output a pulse signal with an arbitrary width. In 8.2, there is a very large effect in terms of pattern reduction.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the first embodiment, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. FIG. 1 is a circuit diagram showing an example of a conventional delay circuit, and FIG. 5 is a timing chart showing the operation of an example of using the delay circuit of FIG. 1.2.3...CMOS Innovator, 411. Capacitor (C), 10.20.30...P channel M
O8pF, T (Tp >, 11.2], 3] ・N-channel MOS FET (TN > , 40...2
Human circuit, 41. Inverter row, 42... Inverter. Fig. 82 Fig. M3'7 Section 83 Fig. 4

Claims (1)

[Claims] a first complementary inverter to which an input signal is applied; a second complementary inverter cascaded to the first complementary inverter to generate an output signal; A delay circuit comprising: a third complementary inverter using the output of the inverter as a potential supply source; and a capacitive load connected to the output terminal of the third complementary inverter.