KR930009425B1 - System initial reset circuit - Google Patents

Abstract

This circuit comprises a capacitor section (1), which connects with a node and earth terminal for charging the node to a supply voltage level in case of power on, a pumping section (2) for discharging electric charges charged in the capacitor (1) into the earth terminal at pumping rate according to the period of clock pulse, a buffer section (3) for generating reset signal by buffering the node voltage, and an electric charge transferring circuit (4).

Description

System initial reset circuit

1 is a circuit diagram of a conventional power-on reset circuit.

2 is an operation timing diagram of FIG.

3 is a circuit diagram of a preferred embodiment of the power-on reset circuit of the present invention.

4 is an operation timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

1 capacitor means 2 charge pumping means

3: buffer means 4: charge transfer circuit

P1, P2, P3: PMOS transistors N1, N2, N3: NMOS transistors

Cj: junction capacitance C1, C2, C3, C4: capacitor

TG: Transmission Gate

INV1, INV2, INV3, INV4, INV5, INV6: Inverter

CK1, CK2: Clock input

The present invention relates to a system initial circuit, and more particularly, to a system initial reset circuit at power on.

The power-on reset circuit is used to bring the system back to a predetermined initial state when the supply voltage is applied. The power-on reset circuit typically includes a resistor connected in series with the capacitor between the power supply voltage and the ground voltage and the ground voltage.

This arrangement allows the power-on-set pulse to follow the change in supply voltage after a delay. This delay is determined by the time constant of the coupling of the resistor and capacitor and the rise time of the supply voltage.

FIG. 1 shows an example of a conventional power-on reset circuit. The operation of FIG. 1 will be described with reference to the operation timing diagram of FIG.

When the power supply voltage is supplied, the capacitor C1 begins to charge according to the time constant of the resistor and capacitor combination and the rise time of the supply voltage as the divided values of the load (P1, P2, P3) resistance and the driver (N1) resistance. (C2) is also charged. When the voltage of the capacitor C1 reaches the threshold of the inverter INV1, the charges charged in the capacitor C2 are discharged through the inverter INV1. When the charges of the capacitor C2 reach the threshold of the inverter INV2, the capacitor C3 starts to charge. When the charge charged in the capacitor C3 reaches the threshold of the inverter INV3, the butters INV3 and INV4 are inverted and buffered to generate a power-on reset pulse POR.

However, when the power-on reset circuit shown in FIG. 1 is used, when the power supply time is long for each system or the power supply part becomes somewhat unstable, the initialization of the system is often unstable and malfunctions. The reason is that the conventional power-on reset type is small in the order of tens to hundreds of microwatts, so the system operates in an unstable state when the power-on reset is released. Therefore, by lengthening the power-on reset time until the system is stable, the system operates normally in a stable state.

Conventional power-on reset circuits can be solved by increasing the number of capacitors or by using multiple capacitors. In this case, the power-on reset time can be improved by several ms. Even if it can not be improved and improved to several ms, the capacitors (C1, C2, C3) should have a large value, which greatly affects the chip size during integration and quickly discharges the charges stored in the capacitor even when the power is turned off. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power on reset circuit which lengthens the power on reset time in order to stabilize the initialization of the system.

It is still another object of the present invention to provide a power-on reset circuit which reduces the size and number of capacitors and makes it easy to implement an integrated form when integrated.

In order to achieve the above object, the system initial reset circuit of the present invention comprises: capacitor means connected between a power supply terminal and a node to charge the node to a supply voltage level at initial power-on; Charge pumping means connected between the node and the ground terminal for discharging the charge charged in the node to the ground terminal at a pumping rate according to a cycle of a clock pulse; And buffer means for buffering the potential difference applied to the node to generate a reset signal.

Referring to the accompanying drawings, the configuration of the power-on reset circuit of the present invention will be described.

In FIG. 3, the capacitor means C4 is connected between the supply voltage terminal and the node C. As shown in FIG. The charge pumping means 2 consists of the discharge circuits N2 and N3 and the discharge time adjusting capacitance Cj.

The discharge circuit 2 inputs the clock CK1 to the control electrode of the NMOS transistor N2, the clock CK2 to the control electrode of the NMOS transistor N3, and the drain of the NMOS transistor N2 is connected to the node B. The source of the NMOS transistor N2 is connected to the drain of the NMOS transistor N3, and the source of the NMOS transistor N3 is connected to the ground voltage.

The discharge time adjustment capacitor is a junction capacitance Cj formed at the junction of the source of the NMOS transistor N2 and the drain of the NMOS transistor N3.

The charge transfer circuit 4 has a common connection between each drain and each source of the transfer gate TG of two NMOS transistors, and a power supply terminal is connected to the control electrode of the transfer gate TG. It is constructed by connecting.

The buffer circuit 3 is connected to the power on reset capacitor 1 to shape a waveform and generate a power on reset pulse.

The operation of the present invention based on the above configuration will be described with reference to FIG.

When the power supply voltage Vcc is supplied, the charge is charged in the capacitor C4 and the transfer gate TG is turned on. Charge charged in the capacitor C4 is discharged through the discharge circuit 2 through the transfer gate TG. The discharge is performed by applying the clock input signals CK1 and CK2 to the control electrodes of the two NMOS transistors N2 and N3. Here, the frequency of the clock input signal CK2 is higher than the frequency of the clock input signal CK1. The clock input signal CK1 is applied to the control electrode of the NMOS transistor N2 to discharge through the junction capacitance Cj through the transfer gate TG. After discharge is performed through the junction capacitance Cj during the clock CK1 pulse time, the clock input signal CK2 is turned on to discharge the charge charged in the junction capacitance Cj through the NMOS transistor N3.

The junction capacitance Cj is a discharge time adjustment capacitor. When the junction capacitance Cj is increased in size, the discharge time is shortened and the power-on reset time is shortened by moving the charge of the node B to the node A a lot.

If the junction capacitance Cj is small in size, the discharge time is longer and the power-on reset time is longer by moving the charge of the node B to the node A little by little. The electric charge charged in the capacitor C4 is discharged in the same manner as above, and when the voltage of the node C is less than or equal to the threshold of the inverter INV5, the buffer circuits INV5 and INV6 generate power ON reset pulses (POR). Buffers to a low level.

Here, the reset time can be adjusted by adjusting the thresholds of the buffer circuits INV5 and INV6.

Therefore, the system initial reset circuit of the present invention can make the initialization of the system stable by lengthening the reset time. In addition, the system initial reset circuit of the present invention can reduce the area of the chip during integration by reducing the size and number of capacitors.

Claims (6)

Capacitor means connected between a power supply terminal and a node to charge the node to a supply voltage level at initial power-on; Charge pumping means connected between the node and the ground terminal to discharge the charge charged in the capacitor to the ground terminal at a pumping rate according to a cycle of a clock pulse; And buffer means for buffering the voltage across the node to generate a reset signal. The first NMOS transistor of claim 1, wherein the charge pumping means has a drain connected to the node, a first clock pulse applied to a gate, and a drain connected to a source of the first NMOS transistor. And a second NMOS transistor having a source connected to the ground terminal when a pulse is applied to the gate. 3. The system initial reset circuit of claim 2, wherein a frequency of the second clock pulse is higher than a frequency of the first clock pulse. 4. The system initial reset circuit according to claim 3, further comprising a charge transfer gate conducted by a supply voltage between said node and said charge pumping means. 5. The system initial reset circuit according to claim 4, wherein said buffer means has cascaded CMOS inverters. 6. The system initial reset circuit according to claim 5, wherein the pulse width of said reset signal is set according to a threshold of said CMOS inverter.

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