JPS5997222A - Clock pulse generating circuit - Google Patents

Abstract

PURPOSE:To attain a two-phase colok pulse having less time delay, by making the input of the first row, where two stages of inverters are connected in series, and the input of the second row, where a gate and an inverter are connected in series, common and giving the output signal of the inverter of the first stage of the first row to both gate electrodes of the gate. CONSTITUTION:Two stages of inverters consisting of FETs 5-8 are connected in series to constitute the first row. An inverter consisting of FETs 9 and 10 and a transmission gate consisting of MOSFETs 15 and 16 are connected in series to constitute the second row. Both gates of FETs 15 and 16 are connected to the output of the inverter consisting of FETs 5 and 6. Gates of FETs 5 and 6 and sources of FETs 15 and 16 are connected to an input terminal 1. By this constitution, the two-phase clock pulse having less time delay is generated from the inverter of the rear stage in each row.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-phase clock pulse generation circuit, and more particularly to a clock generation circuit that can reduce the time delay between two mutually inverted clocks.

Conventional configurations and their problems For example, to drive signal transfer circuits and logic circuits with complementary MO3FET configurations, P-channel FEs of transmission gates and clocked inverters that make up the circuits are required.
In order to turn on and off the T and N channel FET pairs simultaneously, it is necessary to use two-phase clock signals that are inverted from each other.

Conventionally, two-phase clock signals inverted from each other have often been generated from a single-phase clock signal using a circuit as shown in FIG. In Figure 1, 1 is an input terminal, 2 is a power supply terminal, 3 and 4 are output terminals, and 5 to 14 MOSFETs
Odd-numbered ETs are P-channel FETs, and even-numbered ETs are N-channel FETs.

That is, P channel FET5. '7, 9, 11.13 and N-channel FETs 6, 8, 10, 12.14 are mutually inverted using a circuit configured in parallel with even number rows and odd number rows connected in series. A two-phase clock signal was obtained. However, this circuit has the following drawbacks. From input terminal 1 to Figure 2 (
If a clock having a voltage waveform as shown in FIG.
) is obtained. This figure 2 (b),
The mutually inverted clock signals in (C) are t3 and t6.
There is a time delay. These t3 and t6 are the input signals of FIG.
Figure 2 (C) generated by passing through the stage inverter.
Delay tl between the inverted output signal and the input signal in Figure 2 (a)
and from t4, the non-inverted output signal in FIG. 2(b) generated by the input signal in FIG. This is obtained by subtracting the delays t2 and t5 from the input signal. Assuming that the delays per stage of each inverter are equal, t2 and t5 are equal to delays of inno<-21 stages.

If there is a time delay between the two phase clocks that are inverted to each other, the P-channel FE that is a pair of the transmission gate and clocked inverter that make up the complementary MO3FET circuit.
There is a time difference between the on and off times of the T and N channel FETs, causing inconvenience in circuit operation. Naturally, the effect on circuit operation becomes more pronounced as the delay between the two phase clocks increases.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a clock pulse generation circuit that can easily reduce the delay time between mutually inverted two-phase locks in such a conventional complementary MO8FET circuit with a small number of elements. be.

Structure of the Invention To summarize, the present invention consists of a first inverter in which two stages of inverters are connected in series.
and a second column in which transmission gates and inverters are connected in series, the inputs of both columns are common, and the first stage inverter output signal of the first column is transmitted to the transmission of the second column. - The structure is such that the clock pulses are applied to both gate electrodes of the gate, thereby making it possible to generate two-phase clock pulses with little time delay from the subsequent inverters of each column.

Description of examples Embodiments of the present invention will be described based on the drawings.

In Fig. 3, the inverter 2 is composed of FETs 5 to 8.
The first row is a series connection of stages and P-channel FETs 9 and N
Inverter consisting of channel FET10, P channel MO8FET15, and N channel MO3FET1e
A second column is connected in series with a transmino/hun gate consisting of a FET15.1e with both gates connected to the FET.

Connect the output of the inverter composed of 6, and further connect the FE
Connect the gate of Tes,e and the source of FET15.16.

Now, if a signal having a voltage waveform as shown in FIG. 4 (-) is applied to the input terminal 1, in which a signal at the same level as the power supply is connected to H9 ground and a signal at the same level is L, the non-inverting output terminal 3 is shown in Figure 4 (
An output signal having a voltage waveform as shown in FIG. 4(a) is generated, and the delay with respect to the input signal shown in FIG. 4(a) is t8 and tll. Further, a signal having a voltage waveform as shown in FIG. 4(b) appears at the output terminal 17 of the transmission gate composed of FETs 15 and 16. If an L signal is applied to input terminal 1, F
The output of the inverter composed of ET5 and ET6 is H, p,
Since the gates of FETs 15 and 16 are at H and the sources are at L, only N-channel FET 16 is turned on and L appears at the output terminal 17 of the transmission gate. Next, when the input signal changes from L to H, the transmission FETs 15 and 1 are
There is a time when both the gate and source of 6 are at H,
Furthermore, with the addition of the substrate bias effects of FETs 15 and 16, a rising signal with an inflection point appears at the output terminal 17 of the transmission gate. Similarly, when the input signal rises from H to L, there is an inflection point. In addition, FET15.

When the gate and source of transmission gate 16 are high, only the P-channel transistor 15 is turned on, and high appears at the output terminal 17 of the transmission gate.

When the output signal of the transmission gate as shown in FIG. 4(b) is input to the gate of the inverter composed of FETs 9 and 10, the inverting output terminal 4 receives a signal having a voltage waveform as shown in FIG. 4(d). occurs. The waveform of the inverted output terminal 4 is hardly affected by the inflection point of the output signal of the transmission gate, which is the input wave. The delays t7 and tlo between the inverted output signal in Fig. 4(d) and the input signal in Fig. 4 are compared to the delays t7 and t4 between the input signal and inverted output signal in Fig. is decreasing. This appears at the output terminal 17 of the transmission gate in a transient state in which the gates and sources of FETs 15 and 16 are both at L or both at H.
The inverter consisting of 0 is inverted! This is because, even if it is not, it will be in a state of preparation for starting the reversal. Due to these factors, the fourth figure, which is the delay between the non-inverted output and the inverted output, and t
12 is decreasing.

Effects of the Invention As described above, the present invention has the advantage that a clock generation circuit that reduces the time delay between mutually inverted two-phase locks required in a complementary MO8FET circuit can be easily obtained with a small number of elements. Furthermore, by using the clock generation circuit according to the present invention, there is also the effect that the functional circuit can operate smoothly.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional clock generation circuit, and Figure 2 is a circuit diagram of a conventional clock generation circuit.
Figures (-) to (c) are diagrams showing signal voltage waveforms for explanation of the operation in Figure 1, Figure 3 is a circuit diagram of an example of a clock generation circuit according to the present invention, and Figures 4 (a) to (d). ) is a diagram showing signal voltage waveforms for explaining the operation of FIG. 3; 1--input terminal, 2... power supply terminal, 3... non-inverting output terminal, 4... inverting output terminal, 5, 7, 9゜11.
13.15...P channel MO8FET. 6.8, 10, 12, 14.16...N channel 08FET Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] The first row of two inverter stages and the transmino 7
a second column in which an input gate and an input gate are connected in series, the inputs of both columns are common, and the output signal of the first stage input gate of the first column is transmitted to the second column. of the transmission gate of the first column and the inverter of the second column of the second column.
- A clock pulse generation circuit that outputs two-phase clock pulses from the evening.