JPH05110387A - Latch circuit - Google Patents

Abstract

PURPOSE:To avoid a danger such as data destruction in a circuit including serial connection and parallel connection without increasing a delay time. CONSTITUTION:A delay signal generating circuit 2 receives an external control signal phi1 from an external control input terminal G to output control delay signals phi1-phi3 and switch control signals s1, s2. A control signal switch circuit 3 outputs switch output gate signals phiA, phiB from switch pairs SW1, SW2. Since the H level period of the switch output gate signal phiB includes periods before and after the H level period of the gate signal phiA, both gate signals phiA, phiB are not in L level simultaneously for a transition period from a latch period till a data-through period, either of transfer gates TGD, TGF is always cut off without fail and no data destruction due to occurrence in a level fluctuation for the transition period is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, and more particularly to a latch circuit in a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional latch circuit in a CMOS semiconductor integrated circuit is shown in FIG. The data inverter ID and the feedback inverter IF output and hold the data signal input from the external data input terminal D from the external data output terminal Q, and the data transfer gate TGD and the feedback transfer gate TGF are P-type MOS transistors and N-type MOS transistors. It is composed of CMOS transistors. The control signal generation circuit 5b receives the control signal φ1 from the external control signal input terminal G as shown in FIG.
As shown in (b), an inverter I for generating control delay signals .phi.2 and .phi.3 which are in opposite phase to each other.
1 and I2.

Although the control delay signals φ2 and φ3 are in the opposite phase relationship in terms of the circuit, they have the delay time Td of one stage of the inverter circuit, and therefore the signals φ2 and φ3 are within a certain period.
There is a state where 3 overlaps on the same level. That is, during the period T1 in which both the delay signals φ2 and φ3 are at “L” level, the P-type MOS transistors of both transfer gates TDG and TDF are used. The transistors operate to turn on the transfer gates TDG and TDG. Conventionally, in order to minimize such periods T1 and T2, the drive capability of the inverters I1 and I2 of the control signal generation circuit 5b is increased, and the parasitic wiring capacitance to the gates of both transfer gates TGD and TGF is suppressed as much as possible. Was devised.

FIG. 6A is a block diagram of an application circuit using the latch circuit of FIG. 5A. The signal line 10 connects the external data output terminal Q of the latch circuit 6 and the external data input terminal D of the subsequent latch circuits 7 and 8, and the control signal line 11 is a control signal S11 common to the latch circuits 7 and 8.
Enter.

Here, it is assumed that the latch circuit 6 outputs the "H" level in the latched state,
Consider a period TA during which the state in which 8 is in the latched state and outputs "H" level changes to the state of data through. Figure 6
This will be described using the waveforms of the signals S10 and S11 in (b).

The period TA is a period corresponding to the period T1 of FIG. 5B, and in the period TA, the two transfer gates TGD and TGF in the latch circuits 7 and 8 are operated by the P-type MOS transistor as described above. It is in a closed state. Therefore, in the period TA, the "H" level output of the latch circuit 6 and the "L" level inverter outputs in the latch circuits 7 and 8 collide with each other, and the signal S10 is output impedance of both and the on resistance of the transfer gate. The potential drops sharply to the potential point P determined by the partial pressure ratio. After that, data through is entered and switching of the switch circuit is completed, and the level returns to "H" level again.

[0007]

The conventional latch circuit described above uses a CMOS device having significantly improved speed characteristics due to recent improvements in microfabrication technology, and the following problems occur. It's coming. Figure 6 (b)
Since the inverter in the latch circuit 6 having improved speed characteristics, in other words, improved bandwidth and gain reacts to the instantaneous level fluctuation waveform in the period TA of the signal S10 shown in FIG. is there. Then, the signal S10 remains lowered as indicated by the dotted line in FIG. 6 (b) and cannot be restored to its original state, resulting in destruction of the latch data.

In order to suppress such a problem, the drive capability of the inverter for driving the transfer gate has been conventionally increased, but it is not possible to completely eliminate the period in which two transfer gates are simultaneously closed, and the speed characteristic is improved. The effect has not necessarily been improved for MOS transistor elements.

There is also a means of inserting a buffer circuit in the signal line 10 so that the level fluctuation during the period TA is not transmitted to the latch circuit 6, but in that case, there is a problem that the delay time is increased. ..

[0010]

The latch circuit of the present invention comprises:
An external control signal is input from an external control signal input terminal, a plurality of control delay signals having different phases sequentially through a plurality of inverters connected in cascade, and a pair of switch control signals via a delay circuit and an inverter. And a CMOS for inputting the control delay signal to two pairs of input terminals and the switch control signal to each of gate terminals in opposite directions.
A control signal switch circuit which has two switch pairs of a transfer gate of a transistor and outputs a pair of switch output gate signals from the two switch pairs;
The data input terminal is connected to the external data input terminal, the data output terminal is connected to the external data output terminal through the logic circuit, and the control delay signal in the reverse direction is applied to the positive direction gate terminal and the low level of the control delay signal. The switch output gate signal having a short pulse width corresponding to the inside of the period is input to the reverse direction gate end, the data transfer gate of the CMOS transistor to be input respectively, and the data input end to the external data output terminal via the feedback logic circuit. Connected, the data output terminal is connected to the data output terminal of the data transfer gate, the positive direction gate terminal inputs the switch output gate signal having a long pulse width before and after the low level period, and the reverse direction gate terminal Feedback transfer of CMOS transistor for inputting the control delay signal in the reverse direction It is configured to include a data switch circuit having a preparative.

Further, the latch circuit of the present invention receives the external control signal from the external control signal input terminal, and outputs a plurality of control delay signals having different phases sequentially through a plurality of inverters connected in cascade, and further delays the control delay signals. Four delay signal generation circuits for outputting a pair of switch control signals via a circuit and an inverter, and four transfer gates of a CMOS transistor for inputting the control delay signal to each of four pairs of input terminals and gate terminals in opposite directions. A control signal switch circuit having a switch pair and outputting an output gate signal from the four switch pairs;
A data transfer in which a data input terminal is connected to an external data input terminal, a data output terminal is connected to an external data output terminal through a logic circuit, and a switch gate signal having a short forward pulse is input to a reverse gate terminal. A gate and a data input terminal are connected to the external data output terminal via a feedback logic circuit, a data output terminal is connected to a data output terminal of the data transfer gate, and a positive direction pulse end has a long positive pulse width. And a data switch circuit having a feedback transfer gate of a CMOS transistor for inputting a switch output gate signal.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The latch circuit of this embodiment is the same as the conventional data switch circuit 4 shown in FIG. 5A, and a control signal generation circuit 5b for outputting each gate signal thereof has a delay signal generation circuit 2 and a control signal switch circuit. 3 is replaced with the control signal generating circuit 5 having the number 3.

The delay signal generating circuit 2 receives the external control signal φ1 from the external control signal input terminal G and outputs the control delay signals φ1 to φ3 having different phases sequentially through the inverters I1 and I2 connected in cascade. Further, a pair of switch control signals s1 and s2 are output via the delay circuit DL and the inverters I4 and I5.

The control signal switch circuit 3 has control delay signals φ1 and φ3 at two pairs of input terminals N1 and N2.
And the CM for inputting the switch control signals s1 and s2 to the P gate PG and the N gate NG in the opposite directions, respectively.
Transfer gates Tg1 and Tg2 of the OS transistor
And Tg3 and Tg4 have two switch pairs SW1 and SW2, and switch output gate signals φA and φB are output from these switch pairs SW1 and SW2.

In the data switch circuit 4, the data input terminal is connected to the external data input terminal D, the data output terminal NO is connected to the external data output terminal Q via the data inverter ID, and the P gate is shown in FIG. Control delay signal φ2 in the opposite direction to PG and “L” of that signal φ2
The data transfer gate TGD of the CMOS transistor for inputting the switch output gate signal φA having the shorter pulse width to the N gate NG corresponding to the inside of the level period T4, and the data input end outputs the external data via the period inverter IF. The switch output gate signal φB is connected to the terminal Q, the data output terminal is connected to the data output terminal NO, and the P gate PG has a long pulse width (T2 to T6).
And a feedback transfer gate TGF to which the N gate NG inputs the control delay signal φ2 in the reverse direction.

Next, the operation of the circuit will be described with reference to the timing chart of each signal in FIG. First, the control delay signal φ
1 and φ3 are at “L” level and the delay signal φ2 is at “H” level during the period T1, the switch control signals s1 and s
2 is "H" level and "L" level respectively,
The transfer gates Tg2, Tg4 of the control signal switch circuit 3 are turned on, and the transfer gates Tg1, Tg1,
Tg3 turns off.

Therefore, the signal φ1 is applied to the P gate PG of the feedback transfer gate TGF of the data switch circuit 4, and the delayed signal φ3 is applied to the N gate of the data transfer gate TGD5.
It is input to the gate NG. Therefore, since the switch output gate signals φA and φB are at “L” level and the delay signal φ2 is at “H” level, the transfer gate TGD is turned off, the transfer gate TGF is turned on, and the data signal from the external data input terminal D is latched. It

Next, the period T2 is the period T from the latched state.
Immediately after the time t1 when the control delay signal φ1 rises to transition to the data through state of No. 4, the signal φ2 is still at the “H” level due to the delay due to the inverter I1 during this period, and the delay signal φ3 Delay signal φ
Since 2 is at "H" level, it remains at "L" level.

On the other hand, since the input of the control delay signal φ3 to the N gate NG of the transfer gate TGD and the input of the signal φ1 to the P gate PG of the transfer gate TGF remain for the period T1, the output gate signal φB rises to the signal φ1. At the same time as the time point t1, it rises and the output gate signal .phi.A becomes "L" level. Here, since the control delay signal φ2 is at the “H” level, the feedback transfer gate TGF is cut off except for the N-type MOS transistor of the CMOS transistor.

Next, in the period T3, the rising time t of the signal φ1
Immediately after receiving the 1 and the signal φ2 falls at the time point t2 after the delay time Td of the inverter, the signal φ3 is still at the “L” level during the period T2 due to the delay due to the inverter I2. On the other hand, since the inputs of the signals φ3 and φ1 to the data switch circuit 4 are not changed, the switch output gate signal φB is “H” level and the gate signal φA is “L”.
It becomes a level. Since the control delay signal φ2 is at "L" level here, the transfer gates TGD, TG
The F-type CMOS transistors other than the P-type MOS transistors are cut off.

Then, during the period T4 in which the delay signal φ3 rises at the time t3 in response to the fall of the signal φ2, the signal φ
1 is at "H" level, and the signal φ2 is at "L" level. On the other hand, since the levels of the signals φ3 and φ1 input to the data switch circuit 4 do not change, the gate signal φB and the gate signal φA rising at the time point t3 are both at the “H” level, and the signal φ2 is at the “L” level. The transfer gate TGD turns on and the feedback transfer gate T
The GF is turned off, and the data through state is set in this period T4.

During this period T4, the delay circuit DL receives the rising time t3 of the control delay signal φ3.
And the fall of the switch control signal s1 at time t5 delayed by the delay amount Tdi of the inverter I4, and the time t6 delayed by the delay amount of the inverter I5 in response to the fall of the signal s1.
The transfer gates Tg1 and Tg3 are turned on by the rise of the switch control signal s2 of
g2 and Tg4 are turned off. At this time, the switch control signal s
Periods t5 to t6 when both 1 and s2 are at "L" level
All of the transfer gates Tg1 to Tg4 are turned on in the meantime, but since the output gate signals φA and φB have the same potential,
There is no effect on the transfer gates TGD and TGF.

Next, the period T5 is immediately after the time t7 when the delay signal φ1 falls to transition from the data through state to the latch state, which is the trailing edge of the gate signal φA, so that the output gate signal φA is " L "level, gate signal φB is at" H "level, and control delay signal φ2
Is at "L" level, transfer gates TGD, T
Of the CMOS transistors of GF, all but the P-type MOS transistor of the data transfer gate TGD are cut off.

Next, in the period T6, immediately after the falling time t7 of the delay signal φ1 and the delay signal φ2 rising at the time t8, the gate signal φA is at the "L" level and the gate signal φB is at the "H" level. At the level and since the signal φ2 is at the "H" level, all the CMOS transistors of the transfer gates TGD and TGF are cut off except the N-type MOS transistor of the feedback transfer gate TGF.

Finally, during the period T7, the latch state is set, and the switch output gate signal φB also falls in synchronization with the falling time t9 of the control delay signal φ3. Therefore, since the gate signals φA and φB are at “L” level and the delay signal φ2 is at “H” level, the data transfer gate TGD is off and the feedback transfer gate TGF is on.

At these timings, as shown in FIG. 2, the "H" level period (T2 to T6) of the switch output gate signal φB is "H" level period T of the gate signal φA.
4 before and after 4, the transition periods T2, T3 and T from the latch period T1 to the data through period T4 are included.
At 5 and T6, both gate signals φA and φB do not simultaneously overlap with the “L” level.

Therefore, the transfer gates TGD and TGF of the data switch circuit 4 are changed from the latched state to the data through state by the operation from the period T1 to the period T7.
Alternatively, at the time of transition from the data through state to the latch state, one of them must be a P-type MOS transistor of a CMOS transistor.
Since both the transistor and the N-type MOS transistor are cut off, there is no problem that the above-mentioned conventional latch circuit causes a level change in the period TA during which the data is changed to the data through to cause data destruction. Moreover, since the control signal φ1 and the delay signal φ3 from the control input terminal G pass through only the control signal switch circuit 3 and are connected to the gates PG and NG of both transfer gates TGD and TGF, the increase of the delay time is due to the parasitic capacitance. The setup time and hold time are almost the same as the conventional circuit.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. The delay signal generation circuit 2a of the latch circuit of this embodiment is
An external control signal φ1 is input from an external control signal input terminal G, and control delay signals φ1 to φ sequentially differ in phase via inverters I1 to I3 connected in a cascade.
4 and the delay circuit DL and the inverters I4 and I5 to output a pair of switch control signals s1 and s2.

The control signal switch circuit 3a includes four pairs of input terminals N1 to N4 and P gates PN and N gates N.
Transfer gates Tg1, Tg2 to Tg7 of CMOS transistors, which input the control delay signals φ1 to φ4 and the switch control signals s1 and s2 to G, respectively.
It has four switch pairs SW1 to SW4 of Tg8, and outputs the output gate signals φA to φD from these switch pairs. The data switch circuit 4 has the same structure as the circuit of the first embodiment shown in FIG.

The switch output gate signals φC and φA shown in FIG. 4 are supplied to the P gate PG and N gate NG of the data transfer gate TGD of the data switch circuit 4, respectively.
The switch output gate signals φB and φD are applied to the P gate PG and the gate NG of the feedback transfer gate TGF. Here, the switch output gate signal φA is switched by SW1 to SW2 driven by the switch control signals s1 and s2 which are sufficiently delayed as in the operation of the first embodiment.
There is a rising time point t3 of the control delay signal φ3 and a falling time point φ7 of the control delay signal φ1, and the pulse width (T4) is at a phase where the “H” level is slightly ahead of the period T5.
+ T5) is a short waveform.

Since the rising and falling edges of the switch output gate signal φB are synchronized with the delay signals φ1 and φ3, respectively, the pulse width (T2 + T3) before (T2 + T3) and (T6 + T7) after the period (T4 + T5) is added. It becomes a long waveform of T7).

Similarly, the switch output gate signals φC and φD in the opposite directions to the signals φA and φB are delayed signals φ3 and φ.
4 has a short pulse width (T5 + T6) and a long pulse width (T3 to T8), the same effect as that of the first embodiment can be obtained.

[0033]

As described above, the latch circuit of the present invention eliminates the risk of data destruction in a circuit including serial connection and parallel connection, and has various characteristics such as delay time, setup time, and hold time of the latch circuit. It is equivalent to a conventional latch circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a timing diagram of signals for explaining the operation of the circuit of FIG.

5A and 5B are a circuit diagram of an example of a conventional latch circuit and a timing diagram of respective signals for explaining the operation thereof.

6A and 6B are a block diagram of an example of a circuit using the latch circuit of FIG. 5 and a waveform diagram of each signal for explaining the operation thereof.

[Explanation of symbols]

 1, 1a Latch circuit 2, 2a Delay signal generation circuit 3, 3a Control signal switch circuit 4 Data switch circuit 5, 5a Control signal generation circuit D External data input terminal DL Delay circuit G External control signal input terminal ID Data inverter IF Feedback inverter I1 to I5 Inverter NG N gate Q External data output terminal PG P gate TGD Data transfer gate TGF Feedback transfer gate Tg1 to Tg8 Transfer gate φA to φD Switch output gate signal φ1 to φ4 Control delay signal s1, s2 Switch control signal

Claims (2)

[Claims] 1. A plurality of control delay signals having different phases sequentially input from an external control signal input terminal through a plurality of inverters connected in cascade by inputting an external control signal, and further via a delay circuit and an inverter. A delay signal generating circuit that outputs a pair of switch control signals and a transfer gate of a CMOS transistor that inputs the control delay signal to two pairs of input terminals and the switch control signal to each of gate terminals in opposite directions. A control signal switch circuit that has two switch pairs and outputs a pair of switch output gate signals from the two switch pairs; a data input terminal is connected to an external data input terminal; and a data output terminal is externally connected via a logic circuit. It is connected to the data output terminal and the control delay signal of the reverse direction is connected to the positive direction gate end. The switch output gate signal having a short pulse width corresponding to the inside of the low level period of the control delay signal is input to the reverse direction gate end of the data transfer gate of the CMOS transistor and the data input end of the feedback logic circuit. Via the external data output terminal, the data output terminal is connected to the data output terminal of the data transfer gate, and the positive direction gate terminal receives the switch output gate signal having a long pulse width before and after the low level period. And a reverse direction gate terminal having a feedback transfer gate of a CMOS transistor for inputting the reverse direction control delay signal, and a latch circuit. 2. A plurality of control delay signals having different phases sequentially input from an external control signal input terminal through a plurality of inverters connected in cascade by inputting an external control signal, and further via a delay circuit and an inverter. A delay signal generating circuit that outputs a pair of switch control signals; and four switch pairs of transfer gates of a CMOS transistor that inputs the control delay signal to each of four pairs of input terminals and gate terminals in opposite directions, A control signal switch circuit that outputs an output gate signal from the four switch pairs, a data input terminal connected to an external data input terminal, a data output terminal connected to an external data output terminal through a logic circuit, and a reverse gate Data transfer for inputting the switch output gate signal with a short positive direction pulse to the end The gate and the data input terminal are connected to the external data output terminal through a feedback logic circuit, the data output terminal is connected to the data output terminal of the data transfer gate, and the switch having a long positive pulse width is connected to the positive direction gate terminal. A data switch circuit having a feedback transfer gate of a CMOS transistor for inputting an output gate signal, and a latch circuit.