JP2894040B2 - Latch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a latch circuit, and more particularly to a latch circuit in a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional latch circuit in a CMOS semiconductor integrated circuit is shown in FIG. The data inverter ID and the feedback inverter IF output and hold the data signal input from the external data input terminal D from the external data output terminal Q, and the data transfer gate TGD and the feedback transfer gate TGF are formed of a P-type MOS transistor and an N-type MOS transistor. It is composed of CMOS transistors. The control signal generating circuit 5b receives the control signal φ1 from the external control signal input terminal G to
As shown in (b), an inverter I for generating control delay signals φ2 and φ3 having an opposite phase relationship to each other.
1, I2.

The control delay signals .phi.2 and .phi.3 have an opposite phase in circuit, but have a delay time Td corresponding to one stage of the inverter circuit, so that the signals .phi.2 and .phi.
There is a state where 3 overlaps on the same level. That is, the P-type MOS transistors of both transfer gates TDG and TDF are used during the period T1 when both the delay signals φ2 and φ3 are at the “L” level, and the N-type MOS transistor is used during the period T2 when both the signals φ2 and φ3 are at the “H” level. The transistors operate to turn on the transfer gates TDG and TDG. Conventionally, in order to minimize the periods T1 and T2, the drive capability of the inverters I1 and I2 of the control signal generation circuit 5b is increased, and the parasitic wiring capacitance to the gates of the transfer gates TGD and TGF is minimized. Had been devised.

FIG. 6A is a block diagram of an application circuit using the latch circuit of FIG. The signal line 10 connects the external data output terminal Q of the latch circuit 6 to the external data input terminal D of the subsequent latch circuits 7 and 8, and the control signal line 11 connects the control signal S11 common to the latch circuits 7 and 8.
Enter

Here, it is assumed that the latch circuit 6 outputs an "H" level in the latch state, and the latch circuits 7 and
Consider a period TA in which the latch state changes from the state of outputting the "H" level to the data through state. FIG.
This will be described using the waveforms of the signals S10 and S11 in FIG.

The period TA is a period corresponding to the period T1 in FIG. 5B. In the period TA, as described above, the two transfer gates TGD and TGF in the latch circuits 7 and 8 are operated by P-type MOS transistors. In a closed state. Therefore, during the period TA, the output of the "H" level of the latch circuit 6 and the output of the "L" level of the inverters in the latch circuits 7 and 8 collide with each other, and the signal S10 has the output impedance of both of them and the on-resistance of the transfer gate. , The voltage drops sharply to the potential point P determined by the partial pressure ratio. After that, it enters data through and completes the switching of the switch circuit, and returns to the “H” level again.

[0007]

The above-mentioned conventional latch circuit uses a CMOS device whose speed characteristic has been greatly improved due to the recent improvement in fine processing technology, and the following problems occur. It has become. FIG. 6 (b)
The inverter in the latch circuit 6 with improved speed characteristics, in other words, the bandwidth and the gain, reacts to the instantaneous level fluctuation waveform during the period TA of the signal S10 shown in FIG. is there. Then, the signal S10 remains down as shown by the dotted line in FIG. 6B, and does not return to the original state, and the latch data is destroyed.

Conventionally, in order to suppress such a problem, the drive capability of an inverter for driving a transfer gate has been increased. However, a period in which two transfer gates are completely closed at the same time cannot be eliminated, and speed characteristics have been improved. The effect has not always been improved for MOS transistor elements.

There is also a means for inserting a buffer circuit into the signal line 10 to prevent the level fluctuation during the period TA from being transmitted to the latch circuit 6, but in this case, there is a problem that the delay time is increased. .

[0010]

According to the present invention, there is provided a latch circuit comprising:
An external control signal is input from an external control signal input terminal, a plurality of control delay signals having different phases sequentially through a plurality of cascaded inverters, and a pair of switch control signals via a delay circuit and an inverter. And a CMOS for inputting the control delay signal to two pairs of input terminals and the switch control signal to each of gate terminals in opposite directions.
A control signal switch circuit having two switch pairs of transfer gates of transistors, and outputting a pair of switch output gate signals from the two switch pairs;
The data input terminal is connected to the external data input terminal, the data output terminal is connected to the external data output terminal via a logic circuit, and a forward control gate terminal is supplied with a reverse control delay signal and a low level of the control delay signal. A switch output gate signal having a short pulse width corresponding to the inside of the period is input to the reverse gate terminal, a data transfer gate of a CMOS transistor for inputting the signal, and a data input terminal is connected to the external data output terminal via a feedback logic circuit. Connected, a data output terminal is connected to the data output terminal of the data transfer gate, a forward gate terminal receives the switch output gate signal having a long pulse width before and after the low level period, and a reverse gate terminal. CMOS transistor feedback transfer circuit for receiving the reverse control delay signal It is configured to include a data switch circuit having a preparative.

The latch circuit according to the present invention further comprises a plurality of control delay signals having different phases sequentially through a plurality of cascaded inverters which receive an external control signal from an external control signal input terminal, A delay signal generation circuit that outputs a pair of switch control signals via a circuit and an inverter; and four transfer gates of CMOS transistors that input the control delay signal to four pairs of input terminals and gate terminals in opposite directions to each other. A control signal switch circuit having a switch pair and outputting an output gate signal from the four switch pairs;
A data transfer terminal having a data input terminal connected to an external data input terminal, a data output terminal connected to an external data output terminal via a logic circuit, and a switch output gate signal having a short forward pulse input to a reverse gate terminal. A gate, a data input terminal connected to the external data output terminal via a feedback logic circuit, a data output terminal connected to the data output terminal of the data transfer gate, and a positive gate having a long positive pulse width at the positive gate terminal. A data switch circuit having a CMOS transistor feedback transfer gate for inputting a switch output gate signal.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The latch circuit of the present embodiment is the same as the conventional data switch circuit 4 shown in FIG. 5A, and the control signal generation circuit 5b for outputting each gate signal is composed of the delay signal generation circuit 2 and the control signal switch circuit. 3 is replaced with a control signal generating circuit 5 having a control signal generating circuit 3.

The delay signal generating circuit 2 receives an external control signal .phi.1 from an external control signal input terminal G and receives control delay signals .phi.1 to .phi.3 having different phases sequentially through inverters I1 and I2 connected in cascade. Further, it outputs a pair of switch control signals s1 and s2 via delay circuit DL and inverters I4 and I5.

The control signal switch circuit 3 applies control delay signals φ1 and φ3 to two pairs of input terminals N1 and N2.
, And the CMs that input the switch control signals s1 and s2 to the P gate PG and the N gate NG in the opposite directions, respectively.
OS transistor transfer gates Tg1, Tg2
, And Tg3 and Tg4. The switch pairs SW1 and SW2 output switch output gate signals φA and φB from the switch pairs SW1 and SW2.

The data switch circuit 4 has a data input terminal connected to an external data input terminal D, a data output terminal NO connected to an external data output terminal Q via a data inverter ID, and a P gate as shown in FIG. PG is supplied with a control delay signal φ2 in the opposite direction, and “L”
A data transfer gate TGD of a CMOS transistor for inputting a switch output gate signal φA having a shorter pulse width to an N gate NG corresponding to the inside of the level period T4, and an external data output terminal via a period inverter IF The data output terminal is connected to the data output terminal NO, and the P gate PG is connected to the switch output gate signal φB during a long pulse width period (T2 to T6).
And an N gate NG has a feedback transfer gate TGF for inputting a control delay signal φ2 in the reverse direction.

Next, the operation of the circuit will be described with reference to the timing chart of each signal in FIG. First, the control delay signal φ
1 and φ3 are at the “L” level and the delay signal φ2 is at the “H” level during the period T1, the switch control signals s1 and s
2 are “H” level and “L” level, respectively.
The transfer gates Tg2 and Tg4 of the control signal switch circuit 3 are turned on, and the transfer gates Tg1 and Tg1 are turned on.
Tg3 turns off.

Therefore, the signal φ1 is supplied to the P gate PG of the feedback transfer gate TGF of the data switch circuit 4, and the delay signal φ3 is supplied to the N gate of the data transfer gate TGD5.
Input to the gate NG. Therefore, since switch output gate signals φA and φB are at “L” level and delay signal φ2 is at “H” level, transfer gate TGD is turned off, transfer gate TGF is turned on, and the data signal from external data input terminal D is latched. You.

Next, in the period T2, the latch state is changed to the period T2.
4 is immediately after the time point t1 at which the control delay signal φ1 rises to transition to the data through state. During this period, the signal φ2 is still at the “H” level due to the delay by the inverter I1, and the delay signal φ3 Also delay signal φ
2 is at the "H" level, it remains at the "L" level.

On the other hand, the input of the control delay signal φ3 to the N gate NG of the transfer gate TGD and the input of the signal φ1 to the P gate PG of the transfer gate TGF remain in the period T1, so that the output gate signal φB rises the signal φ1. The output gate signal φA rises at the same time as the point in time t1, and goes low. Here, since the control delay signal φ2 is at the “H” level, the components other than the N-type MOS transistor of the CMOS transistor of the feedback transfer gate TGF are cut off.

Next, a period T3 is a time point t at which the signal φ1 rises.
1 immediately after the signal φ2 falls at the time t2 after the delay time Td of the inverter, and during this period T2, the signal φ3 is still at the “L” level due to the delay by the inverter I2. On the other hand, since the inputs of signals φ3 and φ1 to data switch circuit 4 do not change, switch output gate signal φB is at “H” level, and gate signal φA is at “L”.
Level. Since the control delay signal φ2 is at "L" level, the transfer gates TGD, TG
F CMOS transistors other than the P-type MOS transistor are cut off.

During the period T4 in which the delayed signal φ3 rises at the time t3 in response to the fall of the signal φ2, the signal φ
1 is at "H" level, and signal .phi.2 is at "L" level. On the other hand, since the levels of signals φ3 and φ1 input to data switch circuit 4 do not change, gate signal φB and gate signal φA rising at time t3 are both at the “H” level, and signal φ2 is at the “L” level, so that data is low. The transfer gate TGD turns on and the feedback transfer gate T
The GF is turned off, and the period T4 is in the data through state.

During the period T4, the delay circuit DL receives the rising time t3 of the control delay signal φ3.
At the time t5 delayed by the delay amount Tdi of the inverter I4 and at the time t6 delayed by the delay amount of the inverter I5 in response to the fall of the signal s1.
, The transfer gates Tg1 and Tg3 turn on and the transfer gate Tg
g2 and Tg4 are turned off. At this time, the switch control signal s
1 and s2 are both at the “L” level.
All the transfer gates Tg1 to Tg4 turn on, but the output gate signals φA and φB have the same potential.
There is no effect on transfer gate TGD, TGF.

Next, the period T5 is immediately after the time point t7 when the delay signal φ1 falls to make a transition from the data through state to the latch state, and this is the falling of the gate signal φA. L level, gate signal φB is at “H” level, and control delay signal φ2
Are low level, the transfer gates TGD, TGD
Of the CMOS transistors of the GF, those other than the P-type MOS transistor of the data transfer gate TGD are cut off.

Next, the period T6 is immediately after the delay signal φ2 rises at the time t8 in response to the falling time t7 of the delay signal φ1, so that the gate signal φA is at “L” level and the gate signal φB is “H”. Level and the signal φ2 is at the “H” level, so that the CMOS transistors of the transfer gates TGD and TGF are cut off except for the N-type MOS transistor of the feedback transfer gate TGF.

Finally, the period T7 is in the latch state, and the switch output gate signal φB falls in synchronization with the falling time t9 of the control delay signal φ3. Accordingly, since the gate signals φA and φB are at “L” level and the delay signal φ2 is at “H” level, the data transfer gate TGD is off and the feedback transfer gate TGF is on.

By these timings, as shown in FIG. 2, the "H" level period (T2 to T6) of the switch output gate signal φB is the "H" level period T of the gate signal φA.
4, the transition periods T2, T3 and T3 between the latch period T1 and the data through period T4.
5, the gate signals φA and φB do not overlap the “L” level at the same time.

Therefore, the transfer gates TGD and TGF of the data switch circuit 4 are switched from the latch state to the data through state by the operation from the period T1 to the period T7.
Alternatively, at the time of transition from the data through state to the latch state, one of them must be a P-type MOS transistor of a CMOS transistor.
Since both the transistor and the N-type MOS transistor are cut off, the above-described problem does not occur in that the level change occurs during the period TA during which the conventional latch circuit changes to data through, thereby causing data destruction. In addition, the control signal φ1 and the delay signal φ3 from the control input terminal G are connected to the gates PG and NG of the transfer gates TGD and TGF only through the control signal switch circuit 3, so that the delay time increases due to the parasitic capacitance. And the setup time and the hold time are almost the same as those of the conventional circuit.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The delay signal generation circuit 2a of the latch circuit of the present embodiment
An external control signal φ1 is input from an external control signal input terminal G, and control delay signals φ1 to φ having different phases sequentially through inverters I1 to I3 connected in cascade.
4 and a pair of switch control signals s1 and s2 via a delay circuit DL and inverters I4 and I5.

The control signal switch circuit 3a includes four pairs of input terminals N1 to N4, a P gate PN, and an N gate N
The transfer gates Tg1, Tg2, Tg7, and Tg7 of the CMOS transistors which input the control delay signals φ1 to φ4 and the switch control signals s1 and s2 to G, respectively.
It has four switch pairs SW1 to SW4 of Tg8 and outputs output gate signals φA to φD from those switch pairs. The data switch circuit 4 has the same configuration as the circuit of the first embodiment shown in FIG.

Switch output gate signals φC and φA shown in FIG. 4 are applied to the P gate PG and the N gate NG of the data transfer gate TGD of the data switch circuit 4, respectively.
Switch output gate signals φB and φD are applied to the P gate PG and the gate NG of the feedback transfer gate TGF. Here, the switch output gate signal φA is switched by SW1 to SW2 driven by the switch control signals s1 and s2 which are sufficiently delayed as in the operation of the first embodiment.
It has a rising point in time t3 of the control delay signal φ3 and a falling point in time φ7 of the control delay signal φ1, and has a pulse width (T4) whose “H” level is slightly earlier than the period T5.
+ T5).

Since the rise and fall of the switch output gate signal φB are synchronized with the delay signals φ1 and φ3, respectively, the pulse width (T2 + T3) is added before the period (T4 + T5) and (T6 + T7) after the period (T2 + T7). The waveform becomes long at T7).

Similarly, switch output gate signals φC and φD in the opposite directions to signals φA and φB are delayed signals φ3 and φ
4, since each has a short pulse width (T5 + T6) and a long pulse width (T3 to T8), the same effects as in the first embodiment can be obtained.

[0033]

As described above, the latch circuit of the present invention eliminates the danger of data destruction in circuits including serial connection and parallel connection, and also has various characteristics such as delay time, setup time, and hold time of the latch circuit. This is equivalent to a conventional latch circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a timing chart of each signal for explaining the operation of the circuit of FIG. 3;

FIGS. 5A and 5B are a circuit diagram of an example of a conventional latch circuit and a timing chart of signals for explaining the operation thereof, respectively.

6 (a) and 6 (b) are a block diagram of an example of a circuit using the latch circuit of FIG. 5 and waveform diagrams of respective signals for explaining the operation thereof.

[Explanation of symbols]

 1, 1a Latch circuit 2, 2a Delay signal generation circuit 3, 3a Control signal switch circuit 4 Data switch circuit 5, 5a Control signal generation circuit D External data input terminal DL Delay circuit G External control signal input terminal ID Data inverter IF Feedback inverter I1 to I5 Inverter NG N gate Q External data output terminal PGP gate TGD Data transfer gate TGF Feedback transfer gate Tg1 to Tg8 Transfer gate φA to φD Switch output gate signal φ1 to φ4 Control delay signal s1, s2 Switch control signal

Claims (2)

(57) [Claims] An external control signal is input from an external control signal input terminal, a plurality of control delay signals having different phases sequentially through a plurality of cascaded inverters, and further via a delay circuit and an inverter. A delay signal generating circuit for outputting a pair of switch control signals; and a transfer gate of a CMOS transistor for inputting the control delay signal to two pairs of input terminals and the switch control signals to respective gate terminals in opposite directions. A control signal switch circuit having two switch pairs and outputting a pair of switch output gate signals from the two switch pairs; a data input terminal connected to an external data input terminal; and a data output terminal connected to an external device via a logic circuit. Connected to the data output terminal, a reverse control delay signal The switch output gate signal having a short pulse width corresponding to the inside of the low level period of the control delay signal is supplied to a reverse gate terminal, a data transfer gate of a CMOS transistor for inputting the switch output gate signal, and a data input terminal constitutes a feedback logic circuit. The data output terminal is connected to the data output terminal of the data transfer gate, and the forward gate terminal receives the switch output gate signal having a long pulse width before and after the low level period. A data switch circuit having a reverse gate terminal and a feedback transfer gate of a CMOS transistor to which the reverse control delay signal is input. 2. An external control signal is input from an external control signal input terminal, a plurality of control delay signals having different phases sequentially through a plurality of inverters connected in cascade, and further through a delay circuit and an inverter. A delay signal generating circuit that outputs a pair of switch control signals; and four switch pairs of a CMOS transistor transfer gate that inputs the control delay signal to each of four pairs of input terminals and gate terminals in opposite directions, A control signal switch circuit for outputting an output gate signal from the four switch pairs; a data input terminal connected to the external data input terminal; a data output terminal connected to the external data output terminal via the logic circuit; A data transfer for inputting the switch output gate signal having a short positive-going pulse at its end; A gate connected to the external data output terminal via a data input terminal feedback logic circuit, a data output terminal connected to a data output terminal of the data transfer gate, and a switch having a long forward pulse width at a forward gate terminal. A data switch circuit having a CMOS transistor feedback transfer gate for inputting an output gate signal; and a latch circuit.