JPH10150350A - Phase synchronization circuit and storage device using the phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish synchronization of an internal clock with an optional duty ratio in a short time by synthesizing an external clock signal with a signal resulting from delaying the external clock signal through the use of a synchronous mirror delay circuit. SOLUTION: An external clock signal CLKext is given to an input terminal 1. The received signal CLKext is given to an input buffer circuit 2, where the signal is amplified and shaped and the result is transferred to a drive circuit 7 via synchronous mirror delay circuits SMD 1, 2. When the clock signal is delivered through the synchronous mirror delay circuits SMD 1, 2, an internal clock signal CLKint is produced by synthesizing the external clock signal CLKext and a signal resulting from delaying the external clock signal CLKext by 0.5T. Thus, the internal clock signal CLKint whose duty ratio is 50% is generated. Then the output of the SMD 1, 2 is shaped to be a desired waveform by a driver circuit 7 and its output is the shaped internal clock signal CLKint.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit for matching the phase of an internal clock signal of an integrated circuit with the phase of a reference external clock signal.

[0002]

2. Description of the Related Art In recent years, the operation speed of a semiconductor integrated circuit has been dramatically increased. However, as the operation speed has increased, the circuit has been shifted due to a slight phase shift between an internal clock signal for driving an internal circuit and an external clock signal. Causes a malfunction.

[0003] Such a problem is solved by providing a phase synchronization circuit inside the integrated circuit. In a high-speed integrated circuit, the internal operation can be speeded up by using both the rising edge and the falling edge of the clock signal.

In such an integrated circuit, it is important that the rising edge and the falling edge of the internal clock signal are equally spaced (duty ratio 50%). This is because if the rising edge and the falling edge of the internal clock signal are not equally spaced, it may hinder the timing operation of the integrated circuit.

In a semiconductor integrated circuit, in order to reduce power consumption, it is desirable that the phase-locked loop is not operated when it is not necessary. For that purpose, it is important that synchronization can be performed in an extremely short time. It is.

FIG. 1 shows a synchronous mirror delay circuit (ISSCC Digest O) capable of synchronizing in an extremely short time.
f Technical Papres, p374-375, Feb., 1996). FIG. 2 is a waveform chart showing the operation.

The external clock signal CLKext is input to an input buffer circuit 102, where the waveform is shaped and amplified. At this time, the external clock signal is delayed by t1 by the input buffer circuit 102 as shown in FIG. The output of the input buffer circuit 102 is input to the delay circuit 103.
The delay circuit 103 is designed to generate a delay of td = t1 + t2. Here, t1 is the input buffer circuit 2
, T2 is the delay of the clock driver circuit.

The output signal of the delay circuit 103 is further delayed by td from the output of the input buffer circuit 102 as shown in FIG. The delay line 104 is, for example, a delay element composed of an inverter circuit and a NAND circuit connected in series as shown in FIG. 1, and the delay time of the entire delay line is equal to or longer than the period of the external clock. These are connected in multiple stages.

The output of each delay element forming the delay line 104 is input to the next-stage delay element and the transfer circuit 1
05 is input. On the other hand, the output of the input buffer circuit 102 is input to the delay circuit 103 and simultaneously the transfer circuit 1
05 is also input. The transfer circuit 105 includes a delay line 104
And each delay element of the delay line 106 is connected via a NAND circuit, and a clock signal output from the input buffer circuit 102 is input to one input of the NAND circuit.
Therefore, when the clock signal output from the input buffer circuit 102 is input to the transfer circuit 105, the voltage state of the delay line 104 is transferred to the delay line 106. At the time of the first clock signal, since no clock is input to the delay line 104, the output of the transfer circuit 105 does not change. However, in the second and subsequent clock signals, the clock input to the delay line 104 in the previous cycle is transferred to the delay line 106. Therefore, as shown in FIG.
The output timing of 05 is delayed by T−td from the output timing of the delay circuit 103. Here, T is a clock cycle.

The delay line 106 is composed of the same delay element as the delay line 104, and the delay amount per delay element stage is equal to the delay amount per delay element stage of the delay line 104. The delay line 106 has a structure in which the delay line 104 is folded.

Therefore, as shown in FIG. 1E, the clock signal input from the transfer circuit 105 to the delay line 106 receives the delay T-td of the same amount as the delay amount in the delay line 104, and After passing through 106, it is supplied to the driver circuit 107.

The driver circuit 107 is an amplifier circuit for supplying a clock signal to each circuit in the integrated circuit. By this driver circuit, the clock signal is delayed by t2 and output to the output terminal 108 as shown in FIG. As described above, the external clock is 2T in total.
The internal clock signal CLKint output is synchronized with the external clock signal CLKext as shown in FIG. 1 (f). In this case, the time required for synchronization is as short as 2T.

[0013]

In the above-mentioned synchronous mirror delay circuit, in order to operate properly, the clock signal input to the delay circuit 103 requires a high clock time tH, a low time tL, and a delay circuit. 103
It is necessary that the following relationship be established during the delay time td. tH <td <tL (Equation 1) If the above relationship is not established, the transfer circuit 105 is turned on by the next clock signal while the clock signal is propagating through the delay circuit 103. At this time, the delay line 104,
106 stops functioning and malfunctions. For the above reasons, the external clock signal must have a duty ratio of at least 50%.
It needs to be formatted below. In this case, the obtained internal clock signal also has a duty ratio of 50% or less. Therefore, the rising edge of the internal clock is only synchronized with the rising edge of the external clock, but not with respect to the falling edge. That is, in order for the synchronous mirror delay circuit to operate normally, the external clock signal CLKext must be 50% or less. Therefore, the internal clock signal CLKint
Also inevitably becomes 50%. As a result,
The operation timing of the integrated circuit is set at regular intervals (duty ratio 5
0%) is a problem for storage devices that are desirable. The present invention has been made in view of such a problem, and the present invention does not depend on the waveform of an external clock signal, and has an arbitrary duty ratio (in particular, 5
(0%) internal clock can be obtained.

[0014]

In order to achieve the above object, the present invention provides a synchronous mirror delay type synchronous circuit for generating a clock signal synchronized with a rising edge of an external clock, and an external clock. A synchronous mirror / delay-type synchronous circuit that generates a clock signal that is just half a cycle shifted from the rising edge, and an internal clock with a duty ratio of 50% is created by combining these two output clock signals. It is characterized by. According to the present invention, a synchronous mirror delay type synchronous circuit for creating a clock signal synchronized with a rising edge of an external clock, and a half cycle (T / 2) with respect to a rising edge of the external clock
Synchronous mirror that creates a shifted clock signal
By synthesizing the clock signal output from the delay type synchronous circuit to create an internal clock with a duty ratio of 50%, it is possible to always obtain an internal clock with a duty ratio of 50% regardless of the duty ratio of the external clock. . Further, since the present invention is based on a synchronous mirror delay type synchronous circuit, it is possible to synchronize the external clock signal and the internal clock signal in a very short time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows an overall configuration diagram of a storage device according to the present invention. The storage device includes a memory cell array, a row decoder, a column decoder, a sense amplifier, a column selection circuit, a row address buffer, a column address buffer, an output buffer, a control circuit, and a phase synchronization circuit.

FIG. 4 is a conceptual block diagram of the phase locked loop circuit shown in FIG. As shown in FIG. 4, the phase synchronization circuit includes an input terminal 1, an output terminal 8, first and second SMD1s.
And a synchronous mirror delay circuit SMD2, an input buffer 2, and a driver circuit 7. FIG.
Is the synchronous mirror delay circuit S shown in FIG.
FIG. 3 is a diagram including detailed circuits of MD1 and MD2. As shown in FIG. 5, the synchronous mirror delay circuit SM
D1 includes a delay circuit 21, delay lines 22 and 24, and a transfer circuit 23. Similarly, the synchronous mirror delay circuit SMD2 includes a delay circuit 31, delay lines 32 and 34, and a transfer circuit 33. FIG. 6 is a detailed circuit diagram of the delay lines 22 and 24 and the transfer circuit 23 shown in FIG. As shown in FIG. 6, delay lines 22 and 2
4 is basically configured by alternately connecting NAND gates and inverters. Further, as shown in FIG. 6, the transfer circuit 23 is constituted by a NAND gate. FIG. 7 shows a detailed circuit diagram of the driver circuit 7 shown in FIG. As shown in FIG. 7, the driver circuit 7 includes transistors Tr1 and Tr2 and inverters I1 to I6. The phase locked loop circuit according to the first embodiment of the present invention is configured as described above.

Next, the operation of the phase locked loop circuit according to the present invention will be described. The operation will be described with reference to FIG. 5 for convenience of description. FIG. 8 shows operation waveforms of each part of the phase locked loop circuit. Here, on the left side of the waveform shown in FIG.
FIG. 5 shows wirings and the like. An external clock signal CLKext having a period T is input to the input terminal 1 in FIG. External clock signal CLKext input
Are amplified and shaped in the input buffer circuit 2 and output from the synchronous mirror delay circuits SMD1 and SMD2.
Is transferred to the driver circuit 7. The clock signal is a synchronous mirror delay circuit SMD
When the signal propagates through 1 and 2, the clock signal is delayed by a desired amount in the synchronous mirror delay circuits SMD1 and SMD2 (details will be described later). Next, the clock signal propagated through the synchronous mirror delay circuits SMD1 and SMD2 is shaped into a desired waveform in the driver circuit 7. The shaped clock signal is
The internal clock signal CLKint is transmitted to a circuit in the storage device. The above operation will be described in more detail.
First, an external clock signal having a period T is input to the input terminal 1 in FIG. 5 to the phase locked loop circuit (see (1) in FIG. 8). Next, the external clock signal CLKext input to the input terminal 1 is transferred to the delay circuits 21 and 31 and the transfer circuits 23 and 33 via the input buffer circuit 2. Further, when the external clock signal passes through the input buffer 2, it receives a delay of t1. Accordingly, the waveform of the contact 100 is as shown in FIG. Next, when passing through the delay circuit 21, the clock signal
Suffer delay. Accordingly, the waveform of the wiring 110 is as shown in (3) of FIG. Here, the delay amount td is set so that the following relationship is satisfied. td = t1 + t2 (Equation 2) That is, the delay amount td of the delay circuit 21 is set to be equal to the sum of the delay amount t1 of the input buffer 2 described above and the delay amount t2 of the driver circuit 7 described later. Furthermore, in order to guarantee the operation of the phase locked loop circuit, the following relationship must be established between the delay amount td in the delay circuit 21 and the time tH when the clock signal is high and the time tL when the clock signal is low, as described above. No. tH <td <tL (Equation 3) Next, the signal on the wiring 110 undergoes a delay of T-td when passing through the delay line 22. Therefore, the signal propagating through the wiring 120 is as shown in (4) of FIG. Further, the signal on the wiring 120 is delayed by T-td when passing through the delay line 24. Therefore, the signal propagating through the wiring 130 is as shown in (5) of FIG. At this stage, the signal transmitted through the wiring 130 is the external clock signal C
It is delayed by (2T−t2) from LKext.
On the other hand, the delay circuit 21 is designed so that the signal is delayed by 2td when passing through the delay circuit 21. Therefore, a signal transmitted through the contact 100 is delayed by 2td when passing through the delay circuit 21. Accordingly, the waveform of the signal transmitted through the wiring 140 is as shown in (6) of FIG.
Next, the waveform passing through the wiring 140 is delayed by T−2td when passing through the delay line 32. Therefore, the wiring 15
The waveform at 0 is as shown in FIG. Next, the waveform passing through the wiring 150 is delayed by 0.5 × (T−2 × td) when passing through the delay line 34. Therefore,
The waveform of the wiring 160 is as shown in FIG. At this stage, the signal transmitted through the wiring 160 is delayed by (1.5 × T−t2) from the external clock signal CLKext. Finally, the wiring 130 and the wiring 160
When passing through the driver circuit 7, the signal
And the waveform is shaped. As a result, an internal clock signal CLKint is formed. The waveform of the clock signal CLKint is shown in FIG. next,
How the waveform of the internal clock signal CLKint is formed will be described in more detail. The driver circuit 7 has already been shown in FIG. In FIG. 7, it is assumed that the potential of the contact 300 is H. Now, consider the case where the signal on the wiring 160 changes from L to H (time T10 in FIG. 8). In this case, the transistor Tr2 turns on, but the signal on the wiring 130 does not change, so that the transistor Tr1 remains off. Accordingly, the potential of the contact 300 becomes L (GND), and the potential of the internal clock signal CLKint changes from H to L. Since the driver circuit 7 has the delay amount t2 as described above, the internal clock signal CLKint
8 is delayed by t2 from the signal waveform of 0 (time 1 in FIG. 8).
1). It should be noted here that the internal clock signal CLKint is the external clock signal CLKext
Thus, the delay is 1.5T in total. It should also be noted that the falling time T11 of the waveform of the internal clock signal CLKint depends on the rising time T9 of the waveform of the external clock signal CLKext. When the signal on the wiring 130 changes from L to H (time T12 in FIG. 8), the transistor Tr1 turns ON, so that the potential of the contact 300 becomes H, and the potential of the internal clock signal CLKint changes from L to H. . Also,
As described above, since the driver circuit 7 has the delay amount t2, the internal clock signal CLKint is delayed by t2 from the signal waveform of the wiring 130 (time 13 in FIG. 8). Here, it should be noted that the internal clock signal CLKint is delayed by a total of 2T from the external clock signal CLKext. Further, the internal clock signal CLKi
It should also be noted that the rising time T13 of the waveform of nt depends on the rising time T9 of the waveform of the external clock signal CLKext. The driver circuit 7 shown in FIG. 7 is not limited to this circuit configuration as long as it generates a clock signal that repeats rising and falling with signals having different phase differences. The embodiment is configured as described above. As can be seen from FIG. 8 (9), the internal clock signal CLKint uses a signal shifted by 0.5T from the rising edge of the external clock signal CLKext (for example, a signal having a delay of 1.5T and 2T). Synthesized. Therefore, an internal clock signal CLKint having a duty ratio of 50% can be formed. As can be seen from FIG. 8, the internal clock signal CLKint is
Since it is synchronized with the rise of the external clock signal CLKext, the duty ratio of the external clock signal need not be 50%. That is, the internal clock signal C having a duty ratio of 50% which does not depend on the duty ratio of the external clock signal.
LKint can be formed. Also, since the present invention is based on a synchronous mirror delay circuit, synchronization can be established in a very short time (2T). Also, a duty ratio of 50% that does not depend on the duty ratio of the external clock signal
Since the internal clock signal CLKint can be formed, the phase synchronization circuit according to the present invention can be easily applied to a storage device. Next, a second embodiment will be described in detail with reference to the drawings. FIG. 9 shows a conceptual circuit diagram of the phase locked loop of the second embodiment. Here, the configuration of the synchronous mirror delay circuits SMD4 and SMD5 is basically the same as the circuit configuration shown in FIG. 5, but their delay amounts are different. Next, a synchronous mirror delay circuit SMD
The operation waveform of No. 4 is shown in FIG. As shown in FIG. 10 (5), the synchronous mirror delay circuit SM
The signal of the output wiring 130 of D4 is the external clock signal CL.
It is delayed by (1 + 1 / n) × T−t2 from Kext. Further, as shown in FIG. 10 (6), the output wiring 16 of the synchronous mirror delay circuit SMD5
The signal of 0 is (1) from the external clock signal CLKext.
+ / M) × T−t2. However, m and n are different. Further, the delay amount td is set such that the following relationship is satisfied, as described above. td = t1 + t2 (Equation 4) Further, FIG. 10 (7) shows the waveform of the internal clock signal CLKint obtained by synthesizing these signals by the driver circuit 7. The embodiment is configured as described above. As can be seen from (7) of FIG. 10, the internal clock signal CLKint
From the rising edge of the external clock signal CLKext
The signals are synthesized using signals shifted by (1 / n-1 / m) × T. Therefore, an internal clock signal having an arbitrary duty ratio can be formed. As can be seen from FIG. 10, the internal clock signal CLKint is
Since it is synchronized with the rise of ext, the duty ratio of the external clock signal need not be 50%. That is, the internal clock signal CLKint independent of the duty ratio of the external clock signal can be formed. Also, since the present invention is based on a synchronous mirror delay circuit, synchronization can be established in a very short time. Also, a duty ratio of 50% that does not depend on the duty ratio of the external clock signal
Since the internal clock signal CLKint can be formed, the phase synchronization circuit according to the present invention can be easily applied to a storage device. FIG. 11 shows a conceptual diagram of an arrangement place of the phase locked loop. As shown in FIG. 11, it is desirable that the location of the phase synchronization circuit be located at the center in the chip.
Since the phase-locked loop is located at the center of the chip, variations in the distance from the phase-locked loop to each circuit in the chip are reduced, so that the occurrence of a phase difference in the chip can be minimized.

[0018]

Since the present invention is configured as described above, an internal clock having an arbitrary duty ratio (particularly, 50%) can be obtained without depending on the waveform of the external clock signal.
In addition, it is possible to provide a phase synchronization circuit that can establish synchronization in a very short time.

[Brief description of the drawings]

FIG. 1 shows a circuit diagram of a conventional phase locked loop circuit.

FIG. 2 shows operation waveforms of the phase locked loop circuit shown in FIG.

FIG. 3 is a diagram illustrating a diagram in which a phase locked loop is applied to a storage device.

FIG. 4 is a diagram showing a conceptual diagram of a first phase locked loop circuit according to the present invention.

FIG. 5 is a diagram showing the phase locked loop circuit of FIG. 4 in more detail;

FIG. 6 is a detailed circuit diagram of a synchronous mirror delay circuit.

FIG. 7 is a diagram showing a detailed circuit diagram of a driver circuit.

8 is a diagram showing operation waveforms of the phase locked loop shown in FIG.

FIG. 9 is a conceptual diagram of a second phase locked loop circuit according to the present invention.

FIG. 10 is a diagram showing operation waveforms of the phase locked loop shown in FIG.

FIG. 11 is a diagram showing an example of an arrangement place of a phase locked loop circuit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Input buffer circuit 7 Driver circuit 8 Output terminal 21 Delay circuit 22 24, 33, 34 Delay line 23, 33 Transfer circuit 100 Contact 110, 120, 130, 140, 150, 160
wiring

Claims (7)

[Claims] A first delay signal generating circuit for receiving a first clock signal and generating a first signal having a predetermined delay time from the first clock signal; Receiving a clock signal, a second delay signal generation circuit for generating a second signal having a predetermined delay time from the first clock signal, and the first signal and the second signal. And a waveform shaping circuit for generating a second clock signal having a predetermined duty ratio and being synchronized with the first clock. 2. A phase synchronizing circuit for synchronizing phases, comprising: receiving a first clock signal and generating a first signal having a predetermined delay time from the first clock signal. A second delay signal generating circuit for receiving the first clock signal and generating a second signal having a predetermined delay time from the first clock signal; and A waveform shaping circuit for generating a second clock signal having a predetermined duty ratio and synchronized with the first clock from the first signal and the second signal; A phase synchronization circuit characterized by the following. 3. The phase synchronization circuit according to claim 1, wherein the predetermined duty ratio of the second clock signal generated from the waveform shaping circuit is approximately 50%. 4. A first delay signal generation circuit for receiving an external clock signal generated from an external clock generation circuit and generating a first signal having a predetermined delay time from the external clock signal; Upon receiving the external clock signal, a second delay signal generating circuit for generating a second signal having a predetermined delay time from the external clock signal, and from the first signal and the second signal Having a predetermined duty ratio, and a waveform shaping circuit for generating an internal clock signal synchronized with the external clock; and operating based on the internal clock signal generated from the waveform shaping circuit; A storage device, comprising: a storage unit having a memory cell. 5. The storage device according to claim 3, wherein the predetermined duty ratio of the second clock signal generated from the waveform shaping circuit is approximately 50%. 6. A first delay signal generating circuit for receiving a first clock signal and generating a first signal having a predetermined delay time from the first clock signal; In response to the clock signal, a second delay signal generation circuit for generating a second signal having a predetermined delay time from the first clock signal, the rising timing based on the first signal, A clock signal generating circuit for generating a second clock signal whose fall timing is independently controlled based on the second signal. 7. A first delay signal generation circuit for receiving an external clock signal generated from an external clock generation circuit and generating a first signal having a predetermined delay time from the external clock signal, A second delay signal generation circuit for receiving the external clock signal and generating a second signal having a predetermined delay time from the external clock signal, having a predetermined duty ratio, The rising and falling timings are independently controlled based on a second signal, and an internal clock signal generating circuit for generating a second clock signal synchronized with the external clock, and a waveform shaping circuit. Operates based on the generated internal clock signal,
A storage device, comprising: a storage unit having a plurality of memory cells.