JPH06197006A - Synchronous logic circuit - Google Patents

Abstract

PURPOSE:To facilitate the adjustment of timing in a large scale integrated circuit by synchronizing an output signal of a flip-flop of a final stage with an external system clock even when an internal clock used to drive an internal flip-flop and a combined logic circuit is delayed from the external system clock. CONSTITUTION:The synchronous logic circuit 10 is made up of an input buffer 12, flip-flop circuits 14, 18, a combined logic circuit 16 connected in cascade between them, an output buffer 20 connecting to the flip-flop 18, an external system clock input section 22, a buffer 24 connecting to the input section 22, and a delay circuit 26 interposed between the flip-flop circuits 14, 18. When the external system clock to drive the circuit 10 is inputted to the input section 22, the delayed internal clock is inputted to the flip-flop 14 at a one-preceding stage from the final stage and an output signal therefrom is latched by the flip-flop 18 and the latched signal is outputted from the buffer 20 as an output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous logic circuit, and more particularly to a synchronous logic circuit having a pipeline structure having a combinational circuit between a plurality of stages of flip-flops.

[0002]

2. Description of the Related Art A large number of synchronous logic circuits are used in semiconductor integrated circuits such as ICs, LSIs, PLDs, ASICs, etc., and are now the mainstream. When an LSI including a synchronous logic circuit is mounted on a board (printed circuit board), the phase of the internal clock that drives internal circuits such as the synchronous logic circuit inside the LSI is delayed with respect to the external system clock on the board. ing.

FIG. 5 shows a block diagram of a conventional synchronous logic circuit 50. The synchronous logic circuit 50 shown in the figure includes a flip-flop 54 having a data input section 52 and an output section connected in cascade, a combinational logic circuit (combinational circuit) 56,
A flip-flop 58 and an output buffer 60, an input unit 62 for the external system clock SCLK and a clock driver (buffer) 64 are shown. In the illustrated example, the buffer 64 is read from the external system clock SCLK.
The internal clock CLK obtained via a clock tree including a large number of buffers and inverters
1 drives the flip-flop 54 at the immediately preceding stage and the flip-flop 58 at the final stage.

[0004]

In the conventional synchronous logic circuit 50, the internal clock CLK1 is the external system clock SCLK as shown in FIG. 4 (b).
The signal is a little delayed with respect to. Therefore, the output signals of the flip-flops 54 and 58 are both output in synchronization with the internal clock CLK1,
There was a problem of being delayed with respect to the external system clock.

Particularly, when an LSI becomes a large-scale LSI, an external system clock is given to an internal circuit through a clock tree composed of a larger number of clock drivers such as inverters and buffers, drives the internal circuit, and controls its operation. Therefore, the signal (internal clock) that passes through the clock tree that includes more inverters and buffers, which is a delay element, has a larger signal delay than the external system clock, and the signal from the internal circuit such as the synchronous logic circuit is delayed. There is a problem that the delay in the output signal becomes very large.

When the output signal thus delayed in phase is output to the outside of the LSI and input to the next LSI, the internal circuit (logic circuit) inside this LSI malfunctions. .

The object of the present invention was made in view of the above problems of the prior art. In the synchronous logic circuit, the final stage 1 is used as the clock input of the final stage flip-flop.
Provide a synchronous logic circuit that can improve output delay by using a signal with the same timing edge as the opposite phase or synchronization with the external system clock obtained by delaying the clock input (internal clock) at the immediately preceding stage To do.

[0008]

In order to achieve the above object, the present invention provides a plurality of stages of flip-flops for outputting input data in synchronization with a clock, and a combination connected between these flip-flops. In order to align the timing edge of the internal clock input to the clock terminal of the final-stage flip-flop with the timing edge of the external system clock, the flip-flop immediately preceding the final-stage flip-flop is provided. The present invention provides a synchronous logic circuit including a delay circuit that delays a falling edge of an internal clock input to a clock terminal of a clock.

Here, it is preferable that the final stage flip-flop performs a falling timing edge operation, and that the input internal clock of the final stage flip-flop has a phase opposite to that of the external system clock. Further, it is preferable that the delay circuit has a variable delay time.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronous logic circuit according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the synchronous logic circuit of the present invention. The synchronous logic circuit according to the present invention includes a plurality of flip-flops and a plurality of logic I.
Although the combinational logic circuit such as C has a pipeline structure in which the combinational logic circuits are alternately connected in cascade, FIG. 1 shows only the input end and the output end side portions characteristic of the present invention.

As shown in FIG. 1, a synchronous logic circuit 10 of the present invention comprises an input buffer 12, flip-flops 14 and 18, a combinational logic circuit (hereinafter referred to as combinational circuit) 16 cascaded between them, and a flip-flop. 1
8 has an output buffer 20, an external system clock input unit 22, a buffer 24, and a delay circuit 26 interposed between the clock terminal of the flip-flop 14 and the clock terminal of the flip-flop 18.

In the synchronous logic circuit 10 of the present invention, the input buffer 12 is connected to the input terminal D of the flip-flop 14 via a pipeline structure composed of a plurality of combinational circuits and a plurality of flip-flops. The input terminal of the combinational circuit 16 is the output terminal Q of the flip-flop 14.
The output terminal is connected to the input terminal D of the flip-flop 18 at the final stage. This final flip-flop 18
The output terminal Q of is connected to the output buffer 20. Here, the flip-flop 18 at the final stage has an inverting input at the clock terminal CK2 so that a falling edge operation is possible, and latches and outputs data at the falling edge of the input clock.

An external system clock SCLK output from an external system clock generation source (not shown) is input to the external system clock input unit 22 and a clock terminal CK1 of the flip-flop 14 is passed through a clock driver typified by a buffer 24. Internal clock CLK
1 is input. The buffer 24, which is a clock driver, typically represents a large number of buffers and inverters (not shown) that will be clock drivers.
In a large-scale circuit such as an ASIC or the like, a clock tree is created with many other clock drivers. Therefore, the internal clock CLK1 is a clock delayed from the external system clock SCLK because it passes through a plurality of buffers, inverters, and wirings. On the other hand, the internal clock CLK1 is also input to the delay circuit 26 which is one of the characteristic parts of the present invention. The delayed clock CLK2 output from the delay circuit 26 is input to the clock terminal CK2 of the final stage flip-flop 18.

The delay circuit 26 delays the internal clock CLK1 input to the CK1 terminal of the flip-flop 14 immediately before the final stage to output the external system clock SCLK.
It is for generating the delay clock CLK2 having the opposite phase (the phase shift is 180 °) or the same phase (the phase shift is 360 °), and any clock can be used as long as the required delay time can be set. For example, one or more delay elements such as a buffer and an inverter may be connected in series and used, or an RC delay circuit may be used by taking them out to the outside. When the external system clock SCLK for driving the synchronous logic circuit 10 of the present invention does not change, the delay circuit 26 may generate a fixed delay value (time) required for the input clock. However, when the external system clock SCLK may change, it is preferable to use, as the delay circuit 26, a delay circuit (described later) that can vary the delay value (time).

FIG. 2 shows a circuit diagram of an embodiment of the delay amount variable delay circuit used in the present invention. In the figure, a delay circuit 30 includes inverters 32 and 33 that can obtain a required delay value (time), pass transistors 34 and 35 that are alternately connected in series with the inverters 32 and 33, and inverters 32 and 33. Pull-up transistors 36, 37
And a delay control input TCI 38 for controlling the voltage applied to the gates of the pass transistors 34, 35.

In the delay circuit 30, the input terminal IN is connected to one electrode of the pass transistor 34, the other electrode of the pass transistor 34 is connected to the input of the inverter 32, and the output of the inverter 32 is the output of the pass transistor 35.
The other electrode of the pass transistor 35 is connected to the input of the inverter 33, and the output of the inverter 33 is connected to the output terminal OUT. Each gate of the pass transistors 34 and 35 has a delay control input TCI38.
Is connected to a signal line 39 extending from. The drains of the pull-up transistors 36 and 37 are connected to the inputs of the inverters 32 and 33, the sources are connected to the power supply (V _dd ), and the gates are connected to the inverters 32 and 3.
3 outputs, respectively.

In the delay circuit 30, the inverter 32,
Each of 33 produces a predetermined delay value (time), and the delay value (time) per inverter stage is determined by the drive capacity, wiring resistance and input capacitance of the inverter. Therefore, in the delay circuit 30 shown in FIG. 2, the gate potentials of the pass transistors 34 and 35 connected in series to the input sides of the inverters 32 and 33 are controlled by the voltage applied to the delay control input TCI 38, respectively. By controlling the resistance values of the transistors 34 and 35, that is, the on-resistance, the pass transistor 3
The signal delay at 4, 35 can be controlled. Since N-channel MOS transistors are used for the pass transistors 34 and 35, a predetermined analog voltage (V) higher than the threshold value is externally applied to the TCI input 38 to keep the pass transistors 34 and 35 always on. In this way, the delay circuit 30 can generate a predetermined delay value for the input clock.

When the voltage applied to the TCI input 38 is increased, the resistance values of the pass transistors 34 and 35 are decreased, the time constant is decreased, and the delay value obtained is decreased. Conversely, if the applied voltage is lowered, the pass transistor 34,
The resistance value of 35 increases and the delay value increases. By controlling the voltage applied to the TCI input 38 in this manner, the delay value can be controlled and it is possible to respond to the clock frequency within the predetermined range of the external system clock SCLK.

The pull-up transistors 36 and 38 are
Is a P-channel MOS transistor, and since the pass transistors 34 and 35 are NMOS, the source potential of the pass transistor 34 and 35 is lowered to approach the gate potential and the pass transistor 34 or 35 is turned off. It is for pulling up. Here, the delay circuit 30 in the illustrated example is composed of two units with the inverter 32, the pass transistor 34, and the pull-up transistor 36 as one unit, but the present invention is not limited to this, and any number of units may be used. It may be connected. Further, although the above-mentioned delay circuit 30 uses the inverter as the delay element, it may be a buffer.

With the above configuration, the delay circuit 30 in the illustrated example controls the signal delay in the pass transistors 34 and 35 by the potential applied to the delay control input (TCI), and the clock terminals of the flip-flops 14 and 18. Internal clock CL input to CK1 and CK2
The delay of K1 and the delay clock CLK2 can be optimized.

The synchronous logic circuit of the present invention is basically constructed as described above, and its operation will be described below with reference to the time chart shown in FIG.

In order to drive the synchronous logic circuit 10 of the present invention shown in FIG. 1, the external system clock SCLK shown in FIG. Then, the internal clock C obtained by delaying this clock SCLK via a number of clock drivers such as the buffer 24.
LK1 is the flip-flop 1 one stage before the last stage
4 is input to the clock terminal CK1 and the flip-flop 14 is driven by this internal clock CLK1. As a result, the flip-flop 14 has the internal clock CL.
The data input from the input terminal D is latched at the rising edge of K1 and output from the output terminal Q1 of the flip-flop 14.
The output signal is output from.

On the other hand, the internal clock CLK1 is input to the delay circuit 26, delayed by a predetermined delay time, and output from the delay circuit 26 as a delay clock CLK having a phase opposite to that of the external system clock SCLK. The delay clock CLK is input to the inverted clock terminal CK2 of the final stage flip-flop 18 to drive the flip-flop 18. Therefore, the flip-flop 18 is
It operates at the falling edge of the delay clock CLK, latches the output signal of the flip-flop 14 input to the input terminal D, and outputs the output signal from the output terminal Q2 to the output buffer 20.

As shown in FIG. 4A, the internal clock C
Since LK1 is delayed with respect to the external system clock SCLK, the output signal is output after being delayed with respect to the rising edge of the external system clock SCLK. On the other hand, the delay clock CLK2 has a phase delay of 180 ° or less with respect to the internal clock CLK1, and 180 ° with respect to the external system clock SCLK.
Although the clocks are out of phase (opposite phase), the flip-flop 18 performs a falling edge operation, so that the external system clock SCLK rises from the final stage flip-flop 18 of the synchronous logic circuit 10 of the present invention. An output signal synchronized with the edge is output. As a result, this output data can be input to a synchronous logic circuit at the next stage (not shown) to operate correctly.

On the other hand, in the conventional synchronous logic circuit 50 shown in FIG. 5, the flip-flop 58 at the final stage has the same structure as the immediately preceding flip-flop 54, as shown in FIG. 4 (b). The internal clock CLK1 is input. Therefore, the output signal from the final stage flip-flop 58 is the internal clock CLK1 and the flip-flop 5.
Although it is synchronized with the output signal of No. 4, it is output at a timing deviated from the rising edge of the external system clock SCLK. Therefore, a state occurs in which the synchronous logic circuit at the next stage (not shown) cannot operate.

In the synchronous logic circuit 10 of the present invention, the time between the output timing of the final stage flip-flop 18 and the output timing of the final stage flip-flop 14 is shorter than one clock cycle. . Therefore, depending on the scale of the combinational logic circuit 16 interposed therebetween, the logical operation time may be insufficient, the operation may not be completed, and the output may not be performed at the output timing of the flip-flop 18. In this case,
A combinational circuit 1 such as the synchronous logic circuit 50 shown in FIG.
6 is used in the subsequent stage (output side) of the two-stage pipeline structure flip-flops 42 and 44.
2 has an internal clock CL similar to the flip-flop 54.
K1 may be input, and the delay clock CLK2 delayed by the delay circuit 26 may be input to the final stage flip-flop 44.

In the above-mentioned example, the final stage flip-flops 18 and 44 have their clock terminals as inverted clock input terminals, so that the input clock (delayed clock CL
However, the present invention is not limited to this, and an inverter is provided on the input side or the output side of the delay circuits 26 and 30 to invert the delay clock CLK2,
The flip-flops 18 and 44 at the final stage may be made to have a rising edge operation in the same phase as the external system clock SCLK.

Further, instead of providing an inverter on the input side or output side of the delay circuit 30, the number of inverters (32, 33) in the delay circuit 30, that is, the number of units is set to an odd number, and the delayed clock itself is used as an external system clock. SC
It may be in phase with LK. Furthermore, the delay circuits 26 and 30
The internal clock CLK1 may be generated to be in phase with the external system clock SCLK by shifting the phase of the internal clock CLK1 by 180 ° or more.

The synchronous logic circuit of the present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the gist of the present invention.

[0031]

As is apparent from the above description, according to the synchronous logic circuit of the present invention, when the internal clock driving the internal flip-flop or the combinational logic circuit is delayed with respect to the external system clock. However, since the output signal of the final stage flip-flop is synchronized with the external system clock, there is no delay of the output signal with respect to the external system clock. It is not necessary to individually synchronize with other circuits when mounting on a board). Therefore,
According to the synchronous logic circuit of the present invention, it is possible to easily adjust the timing in a large-scale LSI.

According to the synchronous logic circuit of the present invention,
By varying the delay value of the delay circuit, the delay value can be optimized according to the frequency of the external system clock.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of a synchronous logic circuit according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of a variable delay circuit used in the present invention.

FIG. 3 is a configuration block diagram of another embodiment of the synchronous logic circuit according to the present invention.

4A and 4B are time charts showing a clock signal of each part and an output signal of each part of the synchronous logic circuit of the present invention and the related art, respectively.

FIG. 5 is a block diagram of a conventional synchronous logic circuit.

[Explanation of symbols]

 10, 40 Synchronous logic circuit 12 Input buffer 14, 18, 42, 44 Flip-flop 16 Combinational logic circuit (combinational circuit) 20 Output buffer 22 External system clock input 24 Buffer (clock driver) 26, 30 Delay circuit 32, 33 Inverter 34,35 Pass transistor (NMOS) 36,37 Pull-up transistor (PMOS) 38 Delay control input SCLK External system clock CLK1 Internal clock CLK2 Delay clock

Claims (3)

[Claims] 1. A synchronous logic circuit comprising a plurality of stages of flip-flops for outputting input data in synchronization with a clock, and a combinational circuit connected between these flip-flops. In order to align the timing edge of the internal clock input to the clock terminal with the timing edge of the external system clock, the falling edge of the internal clock input to the clock terminal of the flip-flop immediately before the final flip-flop is delayed. A synchronous logic circuit having a delay circuit for controlling the synchronous logic circuit. 2. The synchronous logic circuit according to claim 1, wherein the final stage flip-flop has a falling timing edge operation, and the input internal clock of the final stage flip-flop has a phase opposite to that of the external system clock. . 3. The synchronous logic circuit according to claim 1, wherein the delay circuit has a variable delay time.