JP2012014321A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the design and verification period for a system that uses a plurality of user-programmable integrated circuits.SOLUTION: A field-programmable gate array 1 that is an integrated circuit comprises: a processing block 2 that is an externally user-programmable logic circuit; FIFO registers 3-1 and 3-2 for retiming external input data I1a and I1b using an internal clock CK; a selector 4-1 for selecting either output data of the processing block 2 or output data of the FIFO register 3-2, and outputting it to the outside; and a selector 4-2 for selecting either output data of the processing block 2 or output data of the FIFO register 3-2, and inputting it into the processing block 2 as input data.

Description

  The present invention relates to an integrated circuit used in a system that performs communication frame processing and the like, and more particularly to an integrated circuit such as a field programmable gate array that is a logic circuit that can be programmed by a user from the outside.

  Reconfigurable hardware such as Field Programmable Gate Array (hereinafter referred to as “FPGA”) can be built in a short period of time after the design is completed. Since the hardware can be changed, it is applied to systems in various fields. In addition, the system scale to be applied has been increasing year by year, and the FPGA itself has been increased in scale, but there are many cases where a system is realized by combining a plurality of FPGAs.

  In the field of communications, the specification has been a major application field of FPGA because it can be confirmed by hardware in a short period of time. However, due to the dramatic improvement in communication speed and advanced processing such as security enhancement in recent years, multiple There are many examples of constructing a system using the above FPGA.

  For this reason, techniques for realizing a communication system using a plurality of FPGAs have been developed so far (see Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). FIG. 12 is a block diagram showing a configuration example of a conventional communication system using a plurality of FPGAs. In this communication system, each FPGA 1000 is connected to each other via buses 1001 and 1002, and the FPGA 1000 is centrally controlled by a controller 1003. In FIG. 12, CK is a clock, IN1 and IN2 are input data, and OUT1 and OUT2 are output data.

FIG. 13 is a diagram showing a design / verification period of a conventional communication system when a plurality of FPGAs are developed in parallel. 2000 is the design and verification period of the first FPGA, 2001 is the design and verification period of the second FPGA, 2002 is the design and verification period of the third FPGA, 2003 is the design and verification period of the controller, and 2004 is between the FPGAs It is a connection verification period. As described above, in the design / verification of the communication system shown in FIG. 12, the design / verification period of the controller and the connection verification period between the FPGAs are in the third FPGA design / verification period, which took the most time for development. And are added.
As a technique for shortening the development period of a communication system, a method of creating a netlist of FPGA and ASIC (Application Specific Integrated Circuit) has been proposed (see Patent Document 5).

JP 2000-353950 A JP 2001-186010 A JP 2002-314579 A JP 2005-011344 A JP 2007-102813 A

  In a system configured by combining a plurality of FPGAs via a bus as in the prior art, processing can be efficiently performed in the case of processing closed in one FPGA, but a block of an FPGA like communication frame processing In the case of pipeline processing in which the output of the signal becomes the input of the next FPGA block, there is a first problem that bus control becomes complicated and bus control becomes difficult. Further, there is a second problem that it is necessary to unify bus clocks, and it is necessary to operate a plurality of FPGAs in synchronization.

In order to solve these two problems and implement systemization, in addition to the complexity of development, the design of the systemization must be done after the design of the block to be put in each FPGA is completed, so total development There was a third problem that it took a long time.
Note that the above problems are not limited to FPGAs, but occur similarly in a system using an integrated circuit that can be programmed by a user after manufacturing.

  The present invention has been made to solve the above-described problem, and an object thereof is to shorten the design / verification period of a system using a plurality of integrated circuits that can be programmed by a user.

The integrated circuit of the present invention is a logic circuit that can be programmed from the outside. The processing block processes the input data and outputs the output data to the outside. The external input data is retimed by the internal clock of the integrated circuit. And a FIFO register for inputting to the processing block.
Further, according to one configuration example of the integrated circuit of the present invention, either one of the output data of the processing block and the output data of the FIFO register is selected according to a first select signal and output to the outside. And a second selector that selects one of the output data of the processing block and the output data of the FIFO register in accordance with a second select signal and inputs the selected data to the processing block as input data. It is characterized by comprising.

Further, in one configuration example of the integrated circuit of the present invention, the processing block includes a high-speed processing block and a low-speed processing block, and the FIFO register uses the internal clock to restore high-speed input data. It consists of a high-speed FIFO register for timing and a low-speed FIFO register for retiming low-speed input data with the internal clock, and the output data of the high-speed FIFO register or low-speed FIFO register is high-speed A processing unit that determines whether the data is for low speed or low speed, and distributes the determined data as input data to the processing block for high speed and the processing block for low speed, and the processing block for high speed Output data and output data of the processing block for low speed are either for high speed or low speed. It is characterized in further comprising a merging processing means for outputting to an external output terminal.
Further, in one configuration example of the integrated circuit of the present invention, the distribution processing means determines whether the output data is high-speed data based on an identifier included in the output data of the high-speed FIFO register or the low-speed FIFO register. It is determined whether the data is for low speed, and if it is high speed data, it is input to the high speed processing block, and if it is low speed data, it is input to the low speed processing block.

  According to the present invention, by providing a FIFO register for retiming input data from the outside with an internal clock of the integrated circuit and inputting it to the processing block, a plurality of integrated circuits are connected in a system in which a plurality of integrated circuits are mounted. A bus, a controller for controlling the bus, and a clock common to the system are not required. In the present invention, timing adjustment can be achieved only between connected integrated circuits, so that system design can be simplified. Further, in the present invention, since timing adjustment in the entire system is not required, connection verification between integrated circuits and verification of completed design blocks can be performed before the design of all design blocks is completed. The verification period can be greatly shortened.

  Further, according to the present invention, a first selector that selects one of the output data of the processing block and the output data of the FIFO register according to the first select signal and outputs the selected data to the outside, the output data of the processing block, At the time of designing a system equipped with a plurality of integrated circuits by providing a second selector that selects one of the output data of the FIFO register in accordance with the second select signal and inputs it to the processing block as input data However, even if only a part of the design of the interface to the outside of the system is completed, the design is completed by switching the first and second selectors and returning the data to the input direction. You can proceed with verification of the part. As a result, in the present invention, the connection between the integrated circuits is not performed at the same time as the design / verification of the processing block, instead of performing the verification of the connection between the upper blocks after completing the design / verification of the processing block as in the prior art. Verification can be performed, and the system design and verification period can be greatly shortened.

  In the present invention, it is determined whether the output data of the high-speed FIFO register or the low-speed FIFO register is high-speed data or low-speed data, and the high-speed processing block and low-speed data are input using the determined data as input data. Distribution processing means that distributes and inputs to processing blocks, and merge processing that outputs the output data of the high-speed processing block and the output data of the low-speed processing block to either the high-speed or low-speed external output terminal When designing a system equipped with a plurality of integrated circuits, for example, even when only a part of the low-speed interface design is completed, the low-speed data input from the high-speed interface is entered. The processing circuit for low speed is allocated inside the integrated circuit on the side, and the high speed side in the integrated circuit on the exit side. It is possible to return to the interface, it is possible to proceed with the verification of the part design is complete. As a result, in the present invention, the connection between the integrated circuits is not performed at the same time as the design / verification of the processing block, instead of performing the verification of the connection between the upper blocks after completing the design / verification of the processing block as in the prior art. Verification can be performed, and the system design and verification period can be greatly shortened.

1 is a block diagram illustrating an internal circuit configuration example of an FPGA that is an integrated circuit according to a first embodiment of the present invention. 3 is a timing chart for explaining the operation of the FIFO register according to the first embodiment of the present invention. It is a block diagram which shows the internal circuit structure of FPGA at the time of programming so that a logic circuit may become an input-output terminal direct connection circuit. It is a block diagram which shows the example of the communication system which combined FPGA which concerns on the 1st Embodiment of this invention. It is a figure which shows the example which wraps up data inside FPGA in the 1st Embodiment of this invention. It is a figure which shows another example which wraps around data inside FPGA in the 1st Embodiment of this invention. It is a figure which shows the design and verification period of the communication system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows another example of the communication system which combined FPGA which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the example of the communication system which combined FPGA which concerns on the 2nd Embodiment of this invention. It is a figure which shows the example which distributes the low speed data input from the high speed IF side to the low speed side in the 2nd Embodiment of this invention. It is a block diagram which shows the internal circuit structural example of FPGA which is the integrated circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the conventional communication system by several FPGA. It is a figure which shows the design and verification period of the conventional communication system at the time of developing several FPGA simultaneously in parallel.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an internal circuit configuration example of an FPGA which is an integrated circuit according to the first embodiment of the present invention.
The FPGA 1 is a logic circuit that can be programmed by the user from the outside. The FPGA 1 processes the input data and outputs the output data to the outside, and the external input data I 1 a and I 1 b are rewritten by the internal clock CK of the FPGA 1. First-in first-out (FIFO) registers 3-1, 3-2, selectors for selecting one of the output data of the processing block 2 and the output data of the FIFO register 3-2 and outputting them to the outside 4-1, and a selector 4-2 that selects one of the output data of the processing block 2 and the output data of the FIFO register 3-2 and inputs the selected data to the processing block 2 as input data.

  In FIG. 1, O1a and O1b are output data, ICK1a and ICK1b are input clocks, OCK1a and OCK1b are output clocks, and SEL1 and SEL2 are select signals for controlling the selectors 4-1, 4-2.

  In general, there is a phase difference between the clock external to the FPGA and the internal clock CK of the FPGA. Therefore, the FIFO register 3-1 of the present embodiment retimes the input data I1a at a predetermined timing of the internal clock CK (for example, the rising edge of the internal clock CK) and outputs the internal data D1 as shown in FIG. To do. Similarly, the FIFO register 3-2 also retimes the input data I1b at a predetermined timing of the internal clock CK and outputs the internal data.

  In this manner, in this embodiment, the input data I1a and I1b are retimed by the FIFO registers 3-1 and 3-2, thereby preventing data loss due to the phase difference between the external clocks ICK1a and ICK1b and the internal clock CK. The processing block 2 in the FPGA 1 can process data according to a single clock CK.

  According to the present embodiment, when a plurality of FPGAs are combined, the phase adjustment between the two FPGAs of the output side FPGA and the input side FPGA may be performed. It is possible to easily realize connection between the FPGAs as compared with the case of supplying. In this embodiment, a bus for connecting the FPGA and a controller for controlling the bus are also unnecessary.

  Further, in the present embodiment, selectors 4-1 and 4-2 are provided in the FPGA 1, and the selection operation of the selectors 4-1 and 4-2 is switched by select signals SEL1 and SEL2 input from the outside. Can be realized.

  The selector 4-1 selects one of the output data of the processing block 2 and the output data of the FIFO register 3-2 according to the select signal SEL 1 input from the outside, and outputs it as output data O 1 a. In this way, the selector 4-1 can send the data output from the processing block 2 as output data O1a to a subsequent FPGA (not shown), or is input from the subsequent FPGA and retimed by the FIFO register 3-2. The input data I1b can be turned back to the subsequent FPGA as output data O1a.

  The selector 4-2 selects one of the output data of the processing block 2 and the output data of the FIFO register 3-2 according to the select signal SEL2 input from the outside and outputs the selected data to the processing block 2. In this manner, the selector 4-2 can output the input data I1b input from the subsequent-stage FPGA and retimed by the FIFO register 3-2 to the processing block 2, or the data output from the processing block 2 can be output to the processing block. It can also be folded back to the input of 2.

  In the present embodiment, the selectors 4-1 and 4-2 are not essential components. Further, the example shown in FIG. 1 is an example in which the data can be folded back bidirectionally by the selectors 4-1 and 4-2 provided in the subsequent stage of the processing block 2 (right side in FIG. 1). It is also possible to provide a selector in the previous stage of processing block 2 (left side in FIG. 1).

The processing block 2 processes the output data of the FIFO register 3-1 and the output data of the selector 4-2 with logic programmed by the user. Output data in the right direction of the processing block 2 is output to the selectors 4-1, 4-2. Output data to the left of the processing block 2 is output to the outside as output data O1b.
The internal clock CK of the FPGA 1 is output to the outside as output clocks OCK1a and OCK1b.

  FIG. 3 is a block diagram showing an internal circuit configuration of the FPGA 1 when the logic circuit constituted by the processing block 2 is programmed so as to be an input / output terminal direct connection circuit (hereinafter referred to as a through circuit). In this case, the data input from the FIFO register 3-1 is output as it is to the selectors 4-1, 4-2. The data input from the selector 4-2 is output to the outside as output data O1b as it is.

  In this way, even before the design of the processing block 2 is completed at the initial stage of design, a communication path can be formed by directly connecting the input / output terminals inside the processing block 2. Therefore, connection verification between a plurality of FPGAs becomes possible from the initial stage of design.

FIG. 4 is a block diagram showing an example of a communication system in which the FPGA 1 of the present embodiment is combined. The internal configurations of the first FPGA 1-1, the second FPGA 1-2, and the third FPGA 1-3 are as described with reference to FIGS.
The first FPGA 1-1 receives input data I1a and input clock ICK1a from outside the system, processes the input data I1a, and outputs output data O1a and output clock OCK1a. The output data O1a and the output clock OCK1a are input to the second FPGA 1-2 as input data I2a and input clock ICK2a, respectively.

  The second FPGA 1-2 processes the input data I2a and outputs the output data O2a and the output clock OCK2a. The output data O2a and the output clock OCK2a are input to the third FPGA 1-3 as the input data I3a and the input clock ICK3a, respectively. The third FPGA 1-3 processes the input data I3a and outputs the output data O3a and the output clock OCK3a to the outside of the system.

  The third FPGA 1-3 receives the input data I3b and the input clock ICK3b from outside the system, processes the input data I3b, and outputs the output data O3b and the output clock OCK3b. The output data O3b and the output clock OCK3b are input to the second FPGA 1-2 as input data I2b and input clock ICK2b, respectively.

The second FPGA 1-2 processes the input data I2b and outputs the output data O2b and the output clock OCK2b. The output data O2b and the output clock OCK2b are input to the first FPGA 1-1 as the input data I1b and the input clock ICK1b, respectively. The first FPGA 1-1 processes the input data I1b and outputs the output data O1b and the output clock OCK1b to the outside of the system.
As described above, the data processing is repeated in the plurality of FPGAs 1-1 to 1-3, and the output data of the final FPGA is output outside the system.

  In the initial stage of design, the system interface unit (hereinafter referred to as IF unit) may not be completed. Even in such a case, if the FPGA 1 of the present embodiment is used, the data signal is turned back by the selector inside the FPGA, so that the verification of the part where the design is completed can be advanced.

  In the example of FIG. 5, the design of the input / output IF unit on the right side of the third FPGA 1-3 is not completed. For this reason, the unfinished input / output IF unit is shown by a dotted line. Even in such a case, by using the selector inside the first FPGA 1-1, by performing data continuity that wraps the result of processing the input data I1a by the processing block of the first FPGA 1-1 as the output data O1b, Verification of the first FPGA 1-1 whose design has been completed and the input / output IF unit on the left side thereof can proceed.

  In the example of FIG. 6, by switching the selector in the third FPGA 1-3, the processing block of the third FPGA 1-3 processes the input data I3a as the output data O3b. As described above, the connection confirmation between the FPGAs can be verified by data conduction using the turn-back function of the selector sequentially from the FPGA 1 close to the input / output IF unit whose design has been completed.

  In addition, verification of a block whose design has been completed can be performed even if it is not in the order from the input / output IF unit. In this case, the processing block of the FPGA 1 that is not subject to verification may be a through circuit, and data conduction may be performed so that the processing block of the FPGA 1 that is subject to verification returns data. Thus, any FPGA 1 can be verified after the connection between the FPGAs is verified. The folding signal of the selector can be generated by a physical switch or a folding register mounted on the FPGA 1.

  FIG. 7 is a diagram showing a design / verification period of the communication system according to the present embodiment. Reference numeral 100 denotes a design / verification period of the first FPGA 1-1, 101 denotes a design / verification period of the second FPGA 1-2, 102 denotes a design / verification period of the third FPGA 1-3, and 103 denotes a connection verification period between the FPGAs. It is. As described above, in the present embodiment, as is clear from FIG. 13, not only the controller design / verification period is eliminated, but also the connection verification between FPGAs is performed prior to the design of each FPGA. Since verification is possible by using functions, the design and verification period of the entire system can be greatly shortened.

In the example of FIGS. 1 to 6, the example of the FPGA having one data path in two data transmission directions of left → right direction and right → left direction has been described. It is also possible to configure the system using an FPGA having the following data path.
The internal configurations of the second FPGA 1-5 and the fourth FPGA 1-7 are as described with reference to FIGS. The first FPGA 1-4 and the third FPGA 1-6 each have a plurality of data paths in two data transmission directions.

  The first FPGA 1-4 receives input data I1a and input clock ICK1a from outside the system, processes the input data I1a, and outputs output data O1a and O1c and output clocks OCK1a and OCK1c. The output data O1a and the output clock OCK1a are input to the second FPGA 1-5 as the input data I2a and the input clock ICK2a, respectively. The output data O1c and the output clock OCK1c are the fourth as the input data I4a and the input clock ICK4a, respectively. To the FPGA 1-7.

  The second FPGA 1-5 processes the input data I2a and outputs the output data O2a and the output clock OCK2a. The output data O2a and the output clock OCK2a are input to the third FPGA 1-6 as input data I3a and input clock ICK3a, respectively. The fourth FPGA 1-7 processes the input data I4a and outputs the output data O4a and the output clock OCK4a. The output data O4a and the output clock OCK4a are input to the third FPGA 1-6 as input data I3c and input clock ICK3c, respectively. The third FPGA 1-6 processes the input data I3a and I3c and outputs the output data O3a and the output clock OCK3a to the outside of the system.

  The third FPGA 1-6 receives input data I3b and input clock ICK3b from outside the system, processes the input data I3b, and outputs output data O3b and O3c and output clocks OCK3b and OCK3c. The output data O3b and the output clock OCK3b are input to the second FPGA 1-5 as the input data I2b and the input clock ICK2b, respectively. The output data O3c and the output clock OCK3c are the fourth as the input data I4b and the input clock ICK4b, respectively. To the FPGA 1-7.

  The second FPGA 1-5 processes the input data I2b and outputs the output data O2b and the output clock OCK2b. The fourth FPGA 1-7 processes the input data I4b and outputs the output data O4b and the output clock OCK4b. The output data O2b and the output clock OCK2b are input to the first FPGA 1-4 as the input data I1b and the input clock ICK1b, respectively. The output data O4b and the output clock OCK4b are the first as the input data I1c and the input clock ICK1c, respectively. To the FPGA1-4. The first FPGA 1-4 processes the input data I1b and I1c and outputs the output data O1b and the output clock OCK1b to the outside of the system.

  An FPGA having a plurality of data paths, such as the first FPGA 1-4 and the third FPGA 1-6, can be realized by using a selector as described above or by providing a switching function unit inside the processing block. Can do.

[Second Embodiment]
In the transition period from low-speed communication to high-speed communication, a communication system having a low-speed IF and a high-speed IF as shown in FIG. 9 may be necessary.
First, the data path on the high-speed IF side will be described. The first FPGA 1-8 receives the input data I1a and the input clock ICK1a from outside the system, processes the input data I1a, and outputs the output data O1a and the output clock OCK1a. The output data O1a and the output clock OCK1a are input to the second FPGA 1-9 as input data I2a and input clock ICK2a, respectively.

  The second FPGA 1-9 processes the input data I2a and outputs the output data O2a and the output clock OCK2a. The output data O2a and the output clock OCK2a are input to the third FPGA 1-10 as input data I3a and input clock ICK3a, respectively. The third FPGA 1-10 processes the input data I3a and outputs the output data O3a and the output clock OCK3a to the outside of the system.

  The third FPGA 1-10 receives input data I3b and input clock ICK3b from outside the system, processes the input data I3b, and outputs output data O3b and output clock OCK3b. The output data O3b and the output clock OCK3b are input to the second FPGA 1-9 as input data I2b and input clock ICK2b, respectively.

  The second FPGA 1-9 processes the input data I2b and outputs the output data O2b and the output clock OCK2b. The output data O2b and the output clock OCK2b are input to the first FPGA 1-8 as input data I1b and input clock ICK1b, respectively. The first FPGA 1-8 processes the input data I1b and outputs the output data O1b and the output clock OCK1b to the outside of the system. The above is the data flow on the high-speed IF side.

  Next, the data path on the low-speed IF side will be described. The first FPGA 1-8 receives input data I1c and input clock ICK1c from outside the system, processes the input data I1c, and outputs output data O1c and output clock OCK1c. The output data O1c and the output clock OCK1c are input to the second FPGA 1-9 as input data I2c and input clock ICK2c, respectively.

  The second FPGA 1-9 processes the input data I2c and outputs the output data O2c and the output clock OCK2c. The output data O2c and the output clock OCK2c are input to the third FPGA 1-10 as input data I3c and input clock ICK3c, respectively. The third FPGA 1-10 processes the input data I3c and outputs the output data O3c and the output clock OCK3c to the outside of the system.

  The third FPGA 1-10 receives the input data I3d and the input clock ICK3d from outside the system, processes the input data I3d, and outputs the output data O3d and the output clock OCK3d. The output data O3d and the output clock OCK3d are input to the second FPGA 1-9 as input data I2d and input clock ICK2d, respectively.

  The second FPGA 1-9 processes the input data I2d and outputs the output data O2d and the output clock OCK2d. The output data O2d and the output clock OCK2d are input to the first FPGA 1-8 as input data I1d and input clock ICK1d, respectively. The first FPGA 1-8 processes the input data I1d and outputs the output data O1d and the output clock OCK1d to the outside of the system. The above is the data flow on the low-speed IF side.

  Even in such a system, the design of a low-speed or high-speed input / output IF unit may be delayed. In the example of FIG. 10, the design of the low-speed input / output IF unit is not completed. For this reason, the unfinished input / output IF unit is shown by a dotted line. Therefore, as shown in FIG. 10, the low-speed data input from the high-speed IF side is distributed to the low-speed side inside the first FPGA 1-8, and the first FPGA 1-8, the second FPGA 1-9, and the third FPGA 1 By returning the data processed in −10 to the high-speed IF side in the third FPGA 1-10, it is possible to verify the connection on the low speed side between the plurality of FPGAs and the block on the low speed side.

  FIG. 11 shows an internal circuit configuration of the first FPGA 1-8 of the present embodiment. The FPGA 1-8 uses a high-speed processing block 2a, a low-speed processing block 2b, which is a logic circuit that can be programmed by the user from the outside, and input data I1a, I1b, I1c, I1d using the internal clock CK of the FPGA 1-8. Select one of the FIFO registers 3-1, 3-2, 3-3, 3-4 to be retimed, the output data of the processing block 2a and the output data of the FIFO register 3-2 and output the selected data to the outside. The selector 4-1, the selector 4-2 that selects one of the output data of the processing block 2a and the output data of the FIFO register 3-2 and inputs the selected data to the processing block 2a, and the output of the processing block 2b Selector 4 for selecting one of the data and the output data of the FIFO register 3-4 and outputting it to the outside The selector 4-4 that selects one of the output data of the processing block 2b and the output data of the FIFO register 3-4 and inputs the input data to the processing block 2b, and the output data of the FIFO register 3-1. It is determined whether it is high-speed data or low-speed data, and the distribution data is input to the processing blocks 2a and 2b as input data, and the output data of the processing block 2a and the output data of the processing block 2b And a merging processing unit 6 for outputting to a high-speed external output terminal.

  As in the first embodiment, the FIFO registers 3-1, 3-2, 3-3, 3-4 receive the input data I1a, I1b at a predetermined timing of the internal clock CK (for example, the rising edge of the internal clock CK). , I1c, I1d are retimed to output internal data.

  The selector 4-1 selects one of the output data of the processing block 2 a and the output data of the FIFO register 3-2 according to the select signal SEL 1 input from the outside, and outputs it as output data O 1 a. The selector 4-2 selects either the output data of the processing block 2a or the output data of the FIFO register 3-2 according to the select signal SEL2 input from the outside, and outputs it to the processing block 2a.

  The selector 4-3 selects one of the output data of the processing block 2b and the output data of the FIFO register 3-4 according to the select signal SEL3 input from the outside, and outputs it as output data O1c. The selector 4-4 selects one of the output data of the processing block 2b and the output data of the FIFO register 3-4 according to the select signal SEL4 input from the outside, and outputs it to the processing block 2b.

  The distribution processing unit 5 determines whether the output data of the FIFO register 3-1 is high-speed data or low-speed data based on an identifier such as a destination address included in the output data of the FIFO register 3-1. If it is data, it is output to the processing block 2a, and if it is low speed data, it is output to the processing block 2b.

  The distribution processing unit 5 is a circuit that can be programmed by a user from the outside. The user can arbitrarily set whether to execute the distribution process as described above or to directly output the output data of the FIFO register 3-1 to the processing block 2a without executing the distribution process.

  The merge processing unit 6 outputs the output data of the high-speed processing block 2a as the high-speed output data O1b, and also outputs the output data of the low-speed processing block 2b as the output data O1b. In this way, the merge processing unit 6 can output the data processed in the processing block 2b to the high-speed IF side.

  The merge processing unit 6 is a circuit that can be programmed by the user from the outside. Whether or not to perform the merging process as described above can be arbitrarily set by the user.

  The processing block 2a processes the output data of the distribution processing unit 5 and the output data of the selector 4-2 with logic programmed by the user. Output data to the right of the processing block 2a is output to the selectors 4-1, 4-2. Output data in the left direction of the processing block 2a is output to the outside as output data O1b via the merge processing unit 6.

The processing block 2b processes the output data of the FIFO register 3-3 or the output data of the distribution processing unit 5 and the output data of the selector 4-4 with logic programmed by the user. Output data in the right direction of the processing block 2b is output to the selectors 4-3 and 4-4. Output data to the left of the processing block 2b is output to the outside as output data O1d, or output to the outside as output data O1b via the merge processing unit 6.
The internal clock CK of the FPGA 1-8 is output to the outside as output clocks OCK1a, OCK1b, OCK1c, OCK1d.

With the configuration of the first FPGA 1-8 as described above, the data distribution and merging shown in FIG. 10 can be realized.
The second FPGA 1-9 and the third FPGA 1-10 have the same configuration as that of the first FPGA 1-8.

  In the present embodiment, the selectors 4-1 to 4-4 are not essential constituent requirements. Further, the example shown in FIG. 11 is an example in which data can be folded bidirectionally by selectors 4-1 to 4-4 provided at the subsequent stage of processing blocks 2 a and 2 b (right side in FIG. 11). However, it is also possible to provide a selector in the previous stage (left side in FIG. 11) of the processing blocks 2a and 2b.

  In this embodiment, the distribution processing unit 5 and the merging processing unit 6 are provided in the high-speed input / output IF unit, but these may be provided in the low-speed input / output IF unit. That is, the distribution processing unit determines whether the output data of the FIFO register 3-3 is high-speed data or low-speed data, and distributes the determined data to the processing blocks 2a and 2b as input data. Alternatively, the merging processing unit may output the output data of the processing block 2a and the output data of the processing block 2b to the low-speed external output terminal.

  The present invention can be applied to an integrated circuit such as a field programmable gate array.

  DESCRIPTION OF SYMBOLS 1,1-1 to 1-10 ... FPGA, 2, 2a, 2b ... Processing block, 3-1 to 3-4 ... FIFO register, 4-1 to 4-4 ... Selector, 5 ... Distribution processing part, 6 ... Merge processing section.

Claims (4)

A logic circuit that can be programmed from outside, a processing block that processes input data and outputs output data to the outside,
An integrated circuit comprising: a FIFO register for retiming input data from the outside with an internal clock of the integrated circuit and inputting the data to the processing block. The integrated circuit of claim 1, wherein
A first selector for selecting one of the output data of the processing block and the output data of the FIFO register according to a first select signal and outputting the selected data to the outside;
And a second selector that selects one of the output data of the processing block and the output data of the FIFO register according to a second select signal and inputs the selected data to the processing block as input data. Integrated circuit. The integrated circuit according to claim 1 or 2,
The processing block consists of a processing block for high speed and a processing block for low speed,
The FIFO register includes a high-speed FIFO register for retiming high-speed input data with the internal clock and a low-speed FIFO register for retiming low-speed input data with the internal clock,
Further, it is determined whether the output data of the high-speed FIFO register or the low-speed FIFO register is high-speed data or low-speed data, and using the determined data as input data, the high-speed processing block and the low-speed processing Sorting processing means for sorting and inputting into blocks,
An integrated circuit comprising: merging processing means for outputting the output data of the processing block for high speed and the output data of the processing block for low speed to either the high speed or low speed external output terminal . The integrated circuit of claim 3, wherein
The distribution processing means determines whether the output data is high-speed data or low-speed data based on an identifier included in the output data of the high-speed FIFO register or the low-speed FIFO register. Input to the processing block for high speed, and input to the processing block for low speed if the data is low speed.

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