JPH1173440A - Emulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of terminals, to reduce the number of logic devices by effectively using the gates of programmable logic devices, and to prevent the operating frequency from decreasing by minimizing the number of divisions by multiplexing signals to input/output terminals of divided logic blocks on a time-division basis. SOLUTION: Time-division registers 41 to 44 and clock generating circuits 45 and 46 which control them are inserted into logic blocks 21 and 22 at an output source and an input destination. Then preCLK inputted from outside is determined according to multiplicity. To multiplex two signals 21a and 21b outputted by registers 31 and 32 of the logic block 21, clock generating circuits 45 and 46 generate four control clocks CLK1 to CLK4 of higher frequency than a system clock from preCLK inputted to the logic blocks 21 and 22 and input them to time-division registers 41 to 44. Then signals between the divided logic devices are multiplexed to decrease the number of input/output terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation method for simulating a logic circuit at a high speed by using a plurality of programmable logic devices in a method of evaluating the validity of the logic when designing the logic circuit. It concerns the device.

[0002]

2. Description of the Related Art The prior art will be described with reference to the description in Japanese Patent Application Laid-Open No. 8-30653. Advances in semiconductor technology have increased the degree of integration of logic LSIs year by year, making it possible to integrate large-scale systems on a single chip.
It is becoming possible to build a system such as an electronic device using a chip or a plurality of LSIs. However, when evaluating the validity of the logic when designing the logic circuit, when verifying the function of a large-scale logic, for example, an LSI including 100,000 gates or more or an entire system including the LSI,
Unlike the conventional case of verifying functional blocks and glue logic (logic for connecting functional blocks such as control logic), improvement in design quality cannot be expected unless functions are verified at the application level. However, EW
S (Engineering Work Status)
In the simulation by software using n) or the like, the number of steps becomes extremely large when executing an image or communication-related application, and is practically impossible in terms of processing time. Therefore, in order to obtain an execution performance close to the actual operation, emulation by hardware (simulation operation of a logic circuit) is indispensable.

[0003] In software simulation, although the processing performance is improved year by year by improving the performance of a simulator, a workstation for executing the simulator and a personal computer, 100 to 1000 clocks / cycle is required.
With a processing performance of seconds, emulation by hardware can be executed at an operating frequency of 1 MHz to 10 MHz, and since it is 10 ⁶ to 10 ⁷ clocks / second, a speedup of 1000 times or more can be expected.

As the emulation device, there are a dedicated emulation device unique to a target logic circuit and a general-purpose device capable of emulating various logics. As a dedicated logic emulation device, a TTL (Transistor Transistor) logic part is used.
er Logic), a gate array, or a programmable logic device, and mounted on a printed circuit board. In this case, it is necessary to manufacture a printed circuit board or the like for each development of one type, and thus there is a problem that a manufacturing period and cost are required. In addition, it is difficult to repair a logic defect found during verification, which is inefficient. On the other hand, as one of the general-purpose emulation devices, there is a configuration method disclosed in Japanese Patent Application Laid-Open No. 4-138568. This is because a plurality of programmable logic devices (eg, FPGA (Field Programmable)
Gateway)) and a plurality of programmable wiring modules (for example, wiring elements having a crossbar switch configuration). Therefore, since the logic and the wiring can be freely changed, it is possible not only to cope with various logics but also to flexibly cope with the logic modification. When using a general-purpose emulation device to emulate the target logic or system, first specify the specifications of the programmable logic device to be used based on the netlist or logic drawing that is the connection information of the logic elements as the logic information. The logic is divided into a plurality of logic modules according to the number of gates that can be integrated and the number of external input / output terminals. Then, the divided logical module information is programmed into each programmable logical device. Further, by embedding the connection information between the logic modules into a programmable wiring device, an emulation apparatus can be configured and emulation can be performed. In the configuration of the conventional general-purpose logic emulator, when a logical division is performed based on the number of usable gates of a programmable logical device that uses logical information, the divided logic is as shown in FIGS. 9A and 9B. The number of wires between modules increases. This is because an internal signal is extracted to the outside. As a result, the number of wires generally exceeds the number of external input / output terminals of the logic device. For this reason, most of the logic modules have a problem that the gate in the logic device cannot be used effectively due to the limitation of the number of external input / output terminals. The inability to effectively use the gates of a logic device not only increases the number of logic devices used but also increases the size of the printed circuit board on which the logic device is mounted. In addition, as the number of used logical devices increases, the programming time for the logical devices also increases, which is inefficient. Furthermore, the possibility that a certain signal path itself also goes through a plurality of logic devices increases, so that the possibility of lowering the operating frequency increases.

[0005] As a conventional example which solves this problem, there is a "logic simulation apparatus and its control method" disclosed in Japanese Patent Application Laid-Open No. 8-30653. FIG.
1 is a configuration diagram of a logic module disclosed in Japanese Patent No. According to JP-A-8-30653, the logic module 918-1 shown in FIG.
And S / P conversion circuits 921-i (921-1 to 92-1) for converting input data from serial data to parallel data.
1-3) and a P / S conversion circuit 922-i (922-1 to 922-922) which converts a parallel signal into serial and outputs the signal.
3). This input and output serial /
By the parallel conversion, the number of signal lines required for the logic module before the conventional example can be greatly reduced. Also, the S / P conversion circuit of each logic module and the P / S
The conversion circuit operates with the serial interface clock for the serial interface operation, and the logic module operates with the system clock. FIG. 7 also shows an operation timing chart in the same publication, and also describes that the serial-parallel clock is input by the number of signal lines of the parallel signal to be serial-parallel-converted.

[0006]

According to the above prior art,
The number of signal lines required for the logic module can be significantly reduced. However, since all of the input / output pins of the logic block are converted to serial, there is a disadvantage that the operating frequency is reduced. The present invention has been made in order to solve the above-described problems. By selectively reducing the number of wires between logic modules, the gates of the logic device can be used effectively, and the number of logic devices used can be reduced. An object of the present invention is to realize an emulation device that reduces the number of emulation devices. It is an object of the present invention to improve the efficiency of emulation by reducing the number of logic devices used, and to realize an emulation device that suppresses a reduction in operating frequency.

[0007]

The logical information is logically divided by using a plurality of logical devices having input / output terminals for inputting / outputting signals and interconnectable via the input / output terminals. In an emulation device for emulating information, the emulation device includes an input / output terminal for time-division multiplexing of input / output signals, and an input / output terminal for not time-division multiplexing input / output signals, and Between devices, time-division multiplexed signals and non-time-division multiplexed signals are input and output in a mixed manner.

The logic information is logic information defining a plurality of logic modules having a predetermined number of input / output terminals. The emulation device is logically divided so that the logic modules correspond to the logic devices. Select the signals to be time-division multiplexed so that the number of input / output terminals of the module does not exceed the number of input / output terminals of the corresponding logic device, and time-division multiplex the selected signals to the input / output terminals of the logic device. It is characterized by doing.

[0009] The input / output terminal of the logic device is characterized in that a signal is time-division multiplexed for each destination of another connected logic device.

The emulation apparatus is characterized in that logical division is performed based on logical device information defining a logical device to be used, an operating frequency of the logical device, and timing information of input / output signals.

The emulation apparatus is characterized in that signals are multiplexed from signals having loose timing conditions based on timing information of input / output signals.

The emulation device is characterized in that a control signal required for multiplexing is selected from a prepared logic circuit and inserted.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. The present invention relates to an emulation device that performs logical division based on a logic device whose logic can be programmed, and in which the number of external input / output terminals of the logic module exceeds the number of input / output terminals of the used logic device, becomes a pin module. Are provided with serial / parallel conversion circuits and parallel / serial conversion circuits, respectively, and serial signal lines are multiplexed in a time division manner to reduce the number of external input / output terminals. When multiplexing, set all terminals to 1
Rather than serially multiplexing pairs, multiplex each connected programmable logic device, and prioritize input and output signals based on delay information and timing, and use signals with loose timing. The multiplexing process is performed from the beginning, and the signals are multiplexed until the pin neck can be eliminated. For control signals required for time-division multiplexing, a clock generation circuit is prepared in advance, and a clock several times the actual system clock is input to each logical device. A time-division clock is generated accordingly.

Hereinafter, a specific description will be given with reference to the drawings. FIG. 1 is a flowchart showing a configuration procedure of the emulation device of the present invention. In the figure, reference numeral 11 denotes logic information representing logic to be subjected to logic emulation, 13 denotes programmable logic device information to be used (hereinafter referred to as logic device information), and 15 denotes timing and operation of external and internal signals of the target logic. A timing information definition file 17 for defining timing information indicating a frequency and the like is information about a clock generation circuit that controls the multiplexed signal. FIG. 2 is a block diagram showing an example of an emulation apparatus according to the present invention, and is a block diagram showing a case where a large-scale logic is realized in a plurality of programmable logic devices. 2 includes programmable logic devices (hereinafter, also referred to as logic blocks) 21 to 23, programmable wiring devices 24 to 26, and a clock output circuit 27. The logic is integrated into the programmable logic devices 21 to 23,
All the signals connecting between 23 are connected via programmable wiring devices 24-26. The system clock signal 28 is output from the clock output circuit 27 and is input to all the logic devices 21 to 23.

The operation will be described below with reference to FIGS. In the reading step 12 of the logical information, the logical information 11 of the logic to be subjected to the logical emulation is read.
FIG. 3 shows verilog-HD as an example of the logical information 11.
L (Hardware Description Lan
g.). In the figure, 100 is a module definition, 101 is a module name, 102 and 103 are input / output terminal names, 105 is an input terminal definition, 107 is an input terminal name, 110 is an output terminal definition, 112 is an output terminal name, 11
5 is a logical description, and 117 is the end of the module definition.
The number of gates of the entire emulation device is estimated from logic information defining such a logic module. Next, in the logical division step 14, the programmable logical device information 13 to be used is read, and the logical division is performed into, for example, logical blocks 21 to 23 based on the read logical device information. From the logical device information 13, the number of gates and the number of external input / output terminals, which are the specifications of the logical device, can be obtained. Also, a logical device name such as a maker name or a series name can be obtained. The number of gates of one logical device is set based on the read logical device information. An example of logical division will be described. The total number of gates is estimated from the read logical information. The information of the logical device to be used is read, and the number of gates of one logical device is set. The division is performed in order from the upper module defined in the logic information within a range within the set number of gates. If the number of gates exceeds the number of gates at the time of division at the first level, the division is performed again at the second level.

A specific description will be given with reference to FIG. For example,
When the logic size of the logic device to be used is 30 KG and the gate size of the logic device to be used is 10 KG, the number of gates exceeds one stone (one logic device).
Therefore, attention is paid to a module one level lower. This layer is composed of three modules A, B, and C. A
Is 10 KG, so that it matches the gate size of the logic device, and the division of A is completed here. B is 10 at 15KG
To go beyond KG, go down one layer. In this hierarchy, there are two modules B_1 and B_2, and B_1 is 1
Since it is 0KG, the division is completed. Since B_2 is 5KG, it becomes a target to be merged with another module. Since the remaining C is 5KG, it is merged with B_2. When the number of input / output terminals of the logical blocks 21 to 23 exceeds the number of input / output terminals of the specified logical device information 13, the signal time-division multiplexing processing 16 for reducing the number of pins is performed.

Hereinafter, the multiplexing process 16 will be further described. If the number of input / output terminals of the logical blocks 21 to 23 exceeds the number of input / output terminals of the logical device in the determination of 162 in FIG. A first grouping process is performed for each block (164). By grouping the input / output terminals in 164, in the classified signal group, the timing information is input from the timing information definition file 15, and the priority is determined based on the operating frequency, the delay time, and the like.
A second grouping is performed for each priority (166). The timing information is timing information of logic external and internal signals, and may input an absolute value such as a frequency or a delay time, or may input a relative value for each signal. FIG. 5 is a diagram illustrating an example of the case of a relative value. 131, 13
5, 139 are signal names, and 133, 137, 141 are relative values. Here, the numerical value indicating the relative value is 0 to 10
It is assumed that 100 is the highest at 0. Unfilled signals have a relative value of 0 by default. From the group of signals grouped as described above, the signal multiplexing process is performed in order from the signal group with the highest priority, which is the signal with the looser timing condition (168). For example, assume that the number of input / output terminals of a logical block before time division multiplexing is 120, and the number of input / output terminals of a logical device is 100. Grouping by connection destination 16
4. Multiplexing processing 1 based on priority grouping 166
68, the number of input / output terminals of the logical block becomes 11
It is assumed that the number has decreased to zero. Even so, since the number of input / output terminals of the logical device is still over, the multiplexing process is further repeated. As a result, the number of input / output terminals of the logical block is 1
Suppose that it becomes 00. Here, since the number of input / output terminals of the logical block has fallen within the number of input / output terminals of the logical device, the multiplexing process 16 ends. At this time, it is a feature of the present invention that the time division multiplexing process is terminated when the number of input / output terminals of the logical block falls within the number of input / output terminals of the designated logical device. As a result, not all signals but only necessary minimum signals are multiplexed. The multiplexing processing 16 is not performed for a logical block in which the number of input / output terminals is not exceeded. After the multiplexing process is completed, in a circuit inserting step 18, an appropriate clock generating circuit is selected from the clock generating circuit group 17 prepared in advance according to the degree of multiplexing and inserted into each logical block. In addition, terminals to be multiplexed are minimized, and time division is performed by a clock signal having a frequency higher than the frequency of the output timing signal.

Hereinafter, an example of logical processing related to multiplexing will be described. FIG. 6 shows a part of a logical block diagram before multiplexing. In the figure, a divided logical block 2
The 1 output signals 21 a and 21 b are input to the logic block 22. The output signals 21a and 21b are output from the registers 31 and 32 controlled by the system clock CLK, and have the same output timing. These signals 21
a and 21b are input to the logic block 22, and are taken into the registers 33 and 34 by the system clock CLK, respectively.

FIGS. 7 and 8 show an example of an emulation device after time division multiplexing. FIG. 7 is a partial schematic diagram of a logical block, and FIG. 8 is a timing chart showing the operation thereof. In the figure, a logical block 21 as an output source includes:
A group of clock generation circuits prepared in advance (1 in FIG. 1)
From 7), a circuit selected according to the degree of multiplexing is inserted,
Time division registers 41 and 42, and a clock generation circuit 45 and a selector 47 for controlling the registers are provided. The registers 29 and 30 are registers that are not time-division multiplexed,
The signals 29a and 30a are output from the register 2 by the system clock.
9 and 30, respectively. Similarly, time-division registers 43 and 44 and a clock generation circuit 46 for controlling the registers are inserted into the logic block 22 that is the input destination. The signals 29a and 30a are taken into the registers 35 and 36 of the logic block 22, respectively, by the system clock.

The preCLK input from the outside is determined according to the degree of multiplexing. In this embodiment, a clock that is twice the system clock CLK is input. In the present embodiment, an example of time-division multiplexing of two signals is taken, so the number is doubled for easy understanding, but may be any number. In clock generation circuits 45 and 46, preCLK
Outputs the system clock CLK from the registers 31 to
32, 33-34. Two signals 21a, 2a output from the registers 31, 32 of the logic block 21
When multiplexing 1b, the clock generation circuits 45 and 46 perform pre-input to the logic blocks 21 and 22, respectively.
CLK, four control clocks CLK1 to CLK4 having a higher frequency than the system clock are generated. CLK1
To CLK4 are input to the time division registers 41 to 44, respectively. In the logic block 21 that is the output source, the output signals 21a and 21b are output at the rising edges of CLK1 and CLK2, and are time-division multiplexed by the selector 47 into the signal 21x. In the logic block 22, which is the input destination, the input signal 21x is fetched at the rising edges of CLK3 and CLK4 by the registers 43 and 44, and is converted from serial / parallel to the signals p22a and p22b. 22b. Clock generation circuits 45 and 46, time-division registers 41 to 44
Are prepared in advance according to the number of multiplexes (see FIG. 1).
The clock generation circuit group 17) shown in FIG.

Further, pre input from the outside
CLK may be arbitrarily determined by a designer (user). Also, assuming that the preCLK input from the outside is the same as the system clock, the PLL (Ph
It is also possible to realize a frequency multiplying circuit such as "ase locked loop" and generate multiplexed clocks CLK1 to CLK4 having a higher frequency than the system clock according to the degree of multiplexing.

As described above, according to this embodiment,
By multiplexing the signals between the divided logical devices in a time-division manner, it is possible to reduce the number of input / output terminals of the logical device, and to effectively use the gates in the logical device, The number of devices can be minimized. At this time, not all input / output signals are multiplexed, but only the necessary minimum signal within a range where the number of gates can be used effectively, so that a reduction in the operating frequency can be suppressed. Signals with more severe timing conditions are further multiplexed from signals with loose timing by setting priorities based on timing information, because delays further increase and operation performance decreases by passing through multiplexing circuits. It is possible to avoid multiplexing of critical paths if possible. The multiplexed signal group is multiplexed for each other connected programmable logic device, thereby reducing the overhead of the control circuit for multiplexing and making it easier to observe when monitoring during logic verification. be able to. The control signals required for these multiplexes are provided in advance with a clock generation circuit, and can be selected according to the degree of multiplexing, so that the designer can perform division without intention. That is,
The designer (user) does not need to consider how many signals are multiplexed in one input / output terminal, and can easily perform division.

[0023]

As described above, according to the emulation apparatus of the present invention, the number of terminals can be reduced by time-divisionally multiplexing signals to the input / output terminals of the divided logical block, so that the programmable logic device can be used. Can be used effectively, and the number of logical devices can be reduced.

In addition, it is possible to minimize the number of terminals to be multiplexed, to perform time division by a clock signal having a frequency higher than the frequency of the output timing signal, and to minimize the number of divisions. it can.

Also, since not all signals are multiplexed but only the number of signals necessary for logical division are time-division multiplexed, a decrease in operating frequency can be suppressed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure for configuring an emulation device according to the present invention.

FIG. 2 is a configuration diagram of an example of an emulation device of the present invention.

FIG. 3 is a diagram illustrating a module definition example of logical information according to the embodiment of this invention;

FIG. 4 is a diagram illustrating an example of logical division according to the embodiment of this invention;

FIG. 5 is a diagram showing an example of a timing information definition according to the embodiment of the present invention.

FIG. 6 is a partial schematic diagram before performing time division multiplexing processing in the embodiment of the present invention.

FIG. 7 is a partial schematic diagram after time-division multiplexing processing is performed in the embodiment of the present invention.

8 is a diagram showing a timing chart of the operation of FIG.

FIG. 9 is a diagram illustrating an increase in the number of wires between logic modules in the related art.

FIG. 10 is a configuration diagram of a conventional logic module.

[Explanation of symbols]

11 logical information, 12 logical information read, 13 programmable logical device information, 14 logical division, 15
Timing information definition file, 16 multiplex processing, 1
7 clock generation circuit group, 18 clock generation circuit insertion, 21, 22 logic blocks, 29, 30 registers not time-division multiplexed, 31 to 34 registers, 35, 3
6 registers not time-division multiplexed, 41-44 time-division registers, 45, 46 clock generation circuits.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kazuo Chiba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (6)

[Claims] An emulation of the logic information by using a plurality of logic devices having input / output terminals for inputting / outputting signals and being interconnected via the input / output terminals. In the emulation device, the emulation device includes an input / output terminal for time-division multiplexing of input / output signals, and an input / output terminal for not time-division multiplexing of input / output signals. An emulation apparatus characterized in that time-division multiplexed signals and signals that are not time-division multiplexed are input and output in a mixed manner. 2. The logic information is logic information defining a plurality of logic modules having a predetermined number of input / output terminals. The emulation device is logically divided in correspondence with the logic module and the logic device, respectively. Select a signal to be time-division multiplexed so that the number of input / output terminals of the logic module does not exceed the number of input / output terminals of the corresponding logic device, and time-divide the selected signal to the input / output terminals of the logic device. The emulation device according to claim 1, wherein the emulation device performs multiplexing. 3. The emulation apparatus according to claim 1, wherein the input / output terminal of the logic device performs time division multiplexing of a signal for each destination of another connected logic device. 4. The emulation device is logically divided based on logical device information defining a logical device to be used, an operating frequency of the logical device, and timing information of input / output signals. 1 to
3. The emulation device according to any one of 3. 5. The emulation device according to claim 4, wherein the emulation device multiplexes signals having loose timing conditions based on timing information of input / output signals. 6. The emulation apparatus according to claim 1, wherein the emulation apparatus selects and inserts a control signal required for multiplexing from a prepared logic circuit.