JPH0344109A - Output buffer - Google Patents

Abstract

PURPOSE:To decrease a through-current and to reduce the power consumption of a semiconductor integrated circuit by adding a delay circuit so as to prevent complementary MOS transistors(TRs) from being simultaneously turned on. CONSTITUTION:When a data signal D changes from a low level to a high level, while an output of a NOR gate 3 changes immediately to a low level, an output of a NAND gate 2 changes to a low level with a delay by a time of a delay of the data signal D at a delay circuit 21. Thus, a time of a P-channel MOSTR 18 to start turning on is slower than a time of an N-channel MOSTR 19 to start turning off. Then the throughcurrent is decreased and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer, and particularly to a CMO3 output buffer formed within a semiconductor integrated circuit.

[Conventional technology]

FIG. 4 shows a circuit diagram of a conventional tri-state CMOS buffer.

Conventional 0MO8 output buffers of this type are connected to high potential power supplies (
(hereinafter referred to as VDD) and low potential type R (hereinafter referred to as GND)
A P-channel MO3 transistor 18 and an N-channel MO8 transistor 19 are connected in series between the P-channel MO3 transistor 18 and the gate electrode of the P-channel MO3 transistor 18, which receives a data signal and an output enable signal E. The output of the NAND gate 16 is connected to the gate electrode of the N-channel MO8 transistor 19.
A NOR whose inputs are a signal obtained by inverting the output enable signal E by an inverter 15 and the data signal R.
The output of the gate 17 is connected to the P-channel MO3 transistor 18 and the N-channel MO8 transistor 19,
An output signal O was taken out to an output terminal 20 from the connection point of each drain electrode.

Next, the operation of the conventional output buffer mentioned above will be explained. When the output enable signal E is low level, NAN
Since the output of the D-game) 16 is at a high level and the output of the NOR gate 17 is at a low level, both the P-channel MO8 transistor 18 and the N-channel MO3 transistor 19 are in the OFF' state, and the output signal O is in a high impedance state.

Conversely, when the output enable signal E is high level,
If the data signal is low level, P channel MO8
The transistor 18 is in the OFF' state, the N-channel MO8 transistor 19 is in the ON state, the output signal O changes to low level, and if the data signal is high level, P
The channel MOS transistor 18 is in the ON state, the N channel MOS transistor 19 is in the OFF state, and the output signal O changes to a high level.

[Problems to be Solved by the Invention] In the conventional 0MO8 output buffer described above, when the output enable signal E of the output buffer is at a high level, the output signal O is inverted in response to the level change of the data signal, and the P Channel MO8 transistor 18 and N channel MO
There is a period in which all the eight transistors 19 are in the ON state, albeit for a short time. During this period, a through current flows from vDD to GND, which causes a temporary increase in power consumption, especially in semiconductor integrated circuits that use many 0MO8 output buffers with large current drive capabilities. Ta. Additionally, when many output signals change simultaneously, such as on a data bus, large load capacitances on the output signals will generate large power supply noise.
This caused circuit malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer that solves the above-mentioned drawbacks, does not cause a temporary increase in power consumption, and does not generate power supply noise.

[Means to solve the problem]

In the configuration of the present invention, an output signal of a durable NAND gate whose input is a data signal is connected to a gate electrode, and the other electrode of a MOS transistor connected to one electrode of a -potential power source is connected to the data signal. In the output buffer, the output signal of a multi-input NOR gate serving as one input is connected to the gate electrode, and the other potential power source is connected to the other electrode of the MOS transistor connected to one electrode to obtain the output signal. A delay circuit is provided which takes a data signal as an input and obtains an output obtained by delaying the data signal by a desired time according to a delay control signal, and outputs the output signal of the delay circuit to one of the multi-input NAND gate and the multi-input NOR gate. It is characterized by having two inputs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an output buffer according to an embodiment of the present invention.

In FIG. 1, the output buffer of this embodiment includes a delay circuit 21, unlike the conventional one. This delay (DL)
The circuit 21 is a circuit that delays the data signal by a desired time, and this delay time can be controlled by an external control signal C. For example, it is possible to switch between a delay of one clock cycle and a delay of two clock cycles. The gate electrode input of the P-channel MO8I-transistor 18 whose source electrode is connected to VDD is
A three-man powered NAND gate 2 whose output inputs are the pull signal E, the data signal, and the output signal of the delay circuit 21.
is the output signal of N, whose source electrode is connected to GND.
The gate electrode input of the channel MO8 transistor 19 is
The signal obtained by inverting the output enable signal E by the inverter 1, the data signal, and the output signal of the delay circuit 21 are the output signals of the three-man power NOR gate 3,
The P channel MO8 transistor 18 and the N channel M
By connecting the drain electrodes of the O8 transistor 19,
An output signal O is obtained at the output terminal 20.

Next, the operation of the circuit shown in FIG. 1 will be explained.

FIG. 2 is a time diagram of the output buffer circuit shown in FIG. 1. In FIG. 2, when the output enable signal E is at a low level, the output of the NAND gate 2 is at a high level;
Since the output of the NOR gate 3 is at a low level, both the P-channel MO8 transistor 18 and the N-channel MO8 transistor 19 are in the OFF state, and the output signal O is in a high impedance state.

The following is an explanation when the output enable signal E is at a high level. When the data signal changes from a low level to a high level, the output of the NOR gate 3 immediately changes to a low level, whereas the output of the NAND gate 2 is the time that the data signal is delayed by the delay circuit 21. It changes to low level with a delay of 1 minute. Therefore, N-channel MO
Since the time when the P-channel MO3 transistor 18 starts turning ON is later than the time when the MO3 transistor 19 starts going OFF, the through current can be reduced.

Furthermore, when the data signal changes from high level to low level, the output of NAND gate 2 immediately changes to high level, whereas the output of NOR gate 3 is delayed due to the delay of the data signal in delay circuit 21. Changes to high level with a delay of a certain amount of time. Therefore, the time when N-channel MO8 transistor 19 starts to turn ON is later than the time when P-channel MO8 transistor 18 starts to turn OFF, so that the through current can be similarly reduced.

Furthermore, the delay time in the delay circuit 21 can be changed by the control signal C, so if there are eight output signals in an output buffer, for example, four will be delayed by one clock cycle, and the remaining four will be delayed by one clock cycle. By setting the output signal to be delayed by two clock cycles, it is possible to prevent all eight output signals from changing simultaneously, and it is possible to suppress the generation of large GND (VDD) noise. Furthermore, when the speed of the output signal O is particularly required, by setting the delay time of the delay circuit 21 to Ons, it is possible to realize the same operation as a conventional output buffer. However, in this case, there are three conditions for setting the delay time, so the control signal C requires multiple lines.

Unlike the conventional example, this embodiment includes a delay circuit 2 that can delay a data signal by a desired time using a control signal C.

FIG. 3 is a circuit diagram showing an output buffer according to another embodiment of the present invention.

In FIG. 3, the output buffer of this embodiment includes a large number of buffer circuits 30, 31, 32 . . . . and a flip-flop circuit 40. The buffer circuit 30 includes a P-channel MO8 transistor 18 and an N-channel MO8 transistor 18.
It includes an OS transistor 19, a delay circuit 21, an inverter 4, a NAND gate 5, and a NOR gate 6. That is, an output buffer similar to that of the previous embodiment is configured. Other buffer circuits 31, 32 .・・・・・・
are delay circuits 22, 23 . It has exactly the same configuration as the buffer circuit 30 except for the contents of . Also,
P-channel MO3 transistor 8 and N-channel MO8 transistor 9. 1st two-man power NO.
R gate 41 is configured with P channel MOS transistors 11.12 and N channel MO8 transistors 13.
14 constitutes a second two-man powered NOR gate 42, one input of the two-man powered NOR gate 41 is an output signal of the two-man powered NOR gate 42, and one input of the two-man powered NOR gate 42 The input is the output signal of the two-man power NOR gate 41, and the flip-flop circuit 40 includes both of them. Said two-man NOR gate 3
Another input of the input buffer is the output buffer group 30, 31.
, 32. The other input of the two-man power NOR gate 42 serves as the input of the reset signal R. The characteristic point here is that the VDD and GND of the flip-flop circuit 40 composed of the two-man powered NOR game) 41, 42 are connected to the output buffer group 30, 31, 32 .・・・
The VDD and GND used for ... are taken from a remote location, and the output buffer circuit 30.3
1,32. This means that it is less susceptible to the effects of power supply noise caused by changes in the output of... That is, after equivalently passing through the resistors 50, 51, the buffer circuits 30, 31, 32 .・・・・・・、VDD、G
It is connected to an ND power supply.

Next, the operation of the circuit shown in FIG. 3 will be explained.

Each output buffer 30, 31, 32 . . . . operations are the same as in the above embodiment. In this embodiment, the control signal C on the control line 50 (the above-mentioned 2
When the output signal of the human-powered NOR gate 42) is at a low level, the delay circuits 21, 22, 23 . The delay time due to . . . . The delay time is set to be different for each buffer circuit 30, 31, 32°, . . . . Immediately after reset, the control signal C is at a low level, and the output signals O0°0, . 0. ,......If the load capacitance on is small, the output signal Oo, 01.02...
Since the GND noise generated due to the level change is relatively small, the control signal C remains at the low level without inverting the state of the flip-flop circuit 40. Therefore, the delay circuits 21, 22゜23
, . . . are the same, and the buffer circuits 30, 31, 32 . The output level of...
change almost simultaneously. Conversely, the output signal 0. ．． 0. .

When the load capacitance on 02, . . . is large, the GND noise generated by the level change of the output signals Oo, Or, Ot, . . . becomes large,
When this noise level exceeds a certain value, the state of the flip-flop circuit 40 is reversed, so that the control signal C becomes high level and the delay circuits 22, 23.
The delay time due to... will differ by the amount set, and the buffer circuits 30, 31, 32,...
The timing at which the output level changes will be shifted. Since this state continues until the reset signal is input again, there is an advantage that once large GND noise occurs, the subsequent generation of GND noise can be suppressed to some extent.

〔Effect of the invention〕

As explained above, the present invention adds a delay circuit to a conventional output buffer and prevents complementary MOS transistors from turning on at the same time, thereby reducing the through current. This has the effect of reducing power consumption of integrated circuits. Further, the present invention has the effect of reducing power supply noise and improving circuit reliability, especially by shifting the timing at which the output signals of the plurality of output buffers change.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an output buffer according to an embodiment of the present invention, FIG. 2 is a time diagram of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of an output buffer according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional output buffer. E: Output enable signal, C: Delay control signal, D, Do, Dt+ D2...
...Data signal, o, o,,o,,ol...Output signal, 21,22゜23...Delay circuit, 1,4
．． 15... Inverter, 2.5, 16...
...NAND gate, 3, 6. 17゜41.42...
...NOR gate, 7, 8, 11゜12.18...
...P channel MOS transistor, 9.10,1
3,14.19...N-channel MOS transistor, 20...Output terminal, 30°31.32.
...Output buffer, 40...Flip-flop circuit, 50, 51...VDD -GND
Wiring resistance of wiring.

Claims (1)

[Claims] The output signal of a multi-input NAND gate, whose gate electrode is connected to the data signal as one input, and the other electrode of a MOS transistor whose gate electrode is connected to a single potential power source, and the multi-input NAND gate whose data signal is one input. In an output buffer, which obtains an output signal by connecting the output signal of the NOR gate to the gate electrode and the other electrode of a MOS transistor connected to one electrode of another potential power source, the data signal is input and delayed. A delay circuit is provided which obtains an output obtained by delaying the data signal by a desired time according to a control signal, and the output signal of the delay circuit is used as one input of the multi-input NAND gate and the multi-input NOR gate. output buffer.