JP3185870B2 - High-speed, high-drive signal transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a buffer circuit, and more particularly, to a high-speed and high-drive input / output signal transmission circuit.

[0002]

2. Description of the Related Art A buffer circuit using a MOS transistor is used as a digital input / output interface of a semiconductor integrated circuit, and a general-purpose integrated circuit is properly used depending on the operation speed. In particular, in recent years, with the increase in the degree of integration of semiconductor integrated circuits and the diversification of applications, there has been an increasing demand for faster signal transmission circuits for input / output interfaces.

Conventionally, to increase the speed of a buffer circuit, a high-speed and high-drive circuit is obtained by connecting in parallel a circuit whose speed has been reduced by reducing the size of the buffer and controlling the on / off timing thereof. Was realized.

[0004]

However, even in a buffer circuit having a small size, a transistor in the circuit must operate, so that it takes time for the circuit to operate, and a MOS transistor switch circuit in which the transistor does not need to operate is required. There is a problem that the delay time is considerably large in comparison.

On the other hand, the MOS transistor switch circuit has a problem that it is not suitable for a high-load circuit such as a buffer circuit because it is a high-speed circuit but has no driving ability.

An object of the present invention is to provide a high-speed and high-drive signal transmission circuit capable of high-speed operation and having a driving capability.

[0007]

A high-speed and high-drive signal transmission circuit according to the present invention is a high-speed and high-drive signal transmission circuit used as a digital input / output interface of a semiconductor integrated circuit. MO that outputs
An S transistor switch circuit, a buffer circuit connected in parallel to the MOS transistor switch circuit,
A control circuit for controlling the transistor switch circuit and the buffer circuit is provided. When the signal input from L
Only occasionally MOS transistor switch circuit changes to H by to output the signal as a signal output, signal
After the input changes from L to H, it is specified by the internal circuit.
The signal is switched to a buffer circuit after being delayed by a predetermined timing, and a signal output corresponding to the signal input is output only by the buffer circuit.

[0008] The control circuit of the input signal rise /
An edge detection circuit having a falling edge;
The detection circuit includes five logic circuits NOT, one buffer,
An external circuit switching signal is composed of three D flip-flops and a logic circuit ExOR. An external circuit switching signal is input to the C terminal of the first D flip-flop via the second logic circuit NOT, and an external signal An output is input to the C terminal of the second D flip-flop via the buffer, and an external signal output is input to the C terminal of the third D flip-flop via the sixth logic circuit NOT. The Q outputs of the first, second, and third D flip-flops are connected to a first logic circuit, respectively .
NOT, third logic circuit NOT, and fifth logic circuit N
The signal is input to the D terminal of the flip-flop via the OT, the Q bar output of the first to third D flip-flops is input to the logic circuit ExOR, and the output of the logic circuit ExOR is the MOS transistor switch circuit and the buffer circuit it is preferable that the output comprises an edge detection circuit that controls the respective.

The control circuit may have a logic circuit which receives an output of the edge detection circuit and an enable input from the outside and outputs a control signal to each of the MOS transistor switch circuit and the buffer circuit.

[0010] The control circuit may further include a delay circuit for adjusting the timing from the rising of the signal to the switching from the MOS transistor switch circuit to the buffer circuit to a predetermined value.

Preferably, the switching signal from outside the edge detection circuit is a clock signal.

The buffer circuit includes a logic circuit NAND, a logic circuit NOR, a logic circuit NOT, a PMOS, and an NMO.
The source of the PMOS is connected to VDD, the drain is connected to the drain of the NMOS, and is connected to the output circuit OUT. The source of the NMOS is connected to GND, and the drain is connected to the drain of the PMOS and the output. The logic circuit NAND receives a signal input and an output from the control circuit via the logic circuit NOT. The output is inverted and connected to the gate of the PMOS. it is preferable that the output from the control circuit output is input is connected to the gate of the N MOS.

In the present invention, the respective advantages are simultaneously realized by connecting the buffer circuit and the MOS transistor switch circuit in parallel.

With this configuration, when the signal state changes, the switch circuit transiently functions as a high-speed operation circuit, then the buffer circuit is enabled, and the switch circuit is turned off, thereby functioning as a buffer circuit.
Therefore, a circuit which can operate at the same high speed as the switch circuit and has a driving ability can be obtained.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a high-speed and high-drive signal transmission circuit according to a first embodiment of the present invention.

Referring to FIG. 1, a high-speed and high-speed driving circuit according to a first embodiment of the present invention includes a MOS transistor switch circuit 1, a buffer circuit 2, an edge detection circuit 3 for controlling them, and an external enable control circuit. Logic circuit A
It comprises a signal input terminal IN, a signal output terminal OUT, an enable input terminal EN, and a circuit switching signal input terminal SW.

The MOS transistor switch circuit 1 and the buffer circuit 2 are connected in parallel. The edge detection circuit 3 and the logic circuits AND4 and NAND5 for enable control detect the change (rising / falling) edge of the signal state and the circuit switching signal SW, and control the MOS transistor switch circuit 1 and the buffer circuit 2.

The drain of the MOS transistor switch circuit 1 is connected to the signal input terminal IN, and the source is connected to the signal output terminal OUT and the edge detection circuit 3. The output of AND4 is connected to the gate, and the enable input EN and the output of the edge detection circuit 3 are connected to AND4.
The buffer circuit 2 receives the signal input IN and the output of the NAND 5, and outputs the signal output terminal OUT and the edge detection circuit 3.
And connected to. The enable input EN and the inverted output of the edge detection circuit 3 are input to the NAND 5.

AND4 outputs "1" when the enable input EN is H and the output of the edge detection circuit 3 is "1", and "0" when the output of the edge detection circuit 3 is "0".
Is output. Therefore, MOS transistor switch circuit 1
Is ON when the output of the edge detection circuit 3 is “1”, and is OFF when the output of the edge detection circuit 3 is “0”.
It becomes F.

FIG. 2 is a detailed circuit diagram of the buffer circuit of FIG. The buffer circuit 2 includes a logic circuit NAND21, a logic circuit NOR22, a logic circuit NOT23, a PMOS 24, and an NMOS 25. The source of the PMOS 24 is connected to VDD, and the drain is connected to the drain of the NMOS 25 and to the output circuit OUT. You. The source of the NMOS 25 is connected to GND, and the drain is connected to the drain of the PMOS 24 and the output circuit OUT. The NAND 21 receives the signal input IN and the output of the NAND 5 via the NOT 23, and the output is inverted to P
Connected to the gate of MOS24. The NOR22 outputs an output signal input IN and a logic circuit NAND5 is input is connected to the gate of the N MOS 25.

When the enable input EN is H, the output from the edge detection circuit 3 is inverted by NAND5. Therefore, when the output of the edge detection circuit 3 is "1", the PMOS 2
4, the NMOS 25 is turned off, and the output OUT is disabled. When the output of the edge detection circuit 3 becomes "0" and IN becomes "H", the PMOS 24 is turned on and the NMO
S25 is turned off, and the output OUT becomes VDD. I
When N becomes “L”, the PMOS 24 is turned off and the NMOS 2
5 turns ON, and the output OUT becomes GND. Thus, the buffer circuit 2 performs a normal operation when the output of the edge detection circuit 3 becomes "0".

That is, when the output of the edge detection circuit 3 becomes "1", the MOS transistor switch circuit 1
When it becomes N, the signal input IN is output to the signal output circuit OUT, and the buffer circuit 2 is disabled. When the output of the edge detection circuit 3 becomes "0", the MOS
The transistor switch circuit 1 is turned off and does not output the signal input IN to the signal output circuit OUT.
Outputs VDD to the signal output circuit OUT when the signal input IN is “H”, and outputs G when the signal input IN is “L”.
ND is connected to the signal output circuit OUT.

When the enable input EN is L, AND
4 becomes “0”, and the MOS transistor switch 1
Since the FF becomes the FF and the output of the NAND 5 becomes “1”, the buffer circuit 2 is disabled.

FIG. 3 is a detailed circuit diagram of the edge detection circuit of FIG. The edge detection circuit 3 includes five logic circuits NOT3
1, 32, 33, 35, 36, one buffer 34, 3
D flip-flops (hereinafter abbreviated as DFF) 37, 3
8, 39, and a logic circuit ExOR40, and an external circuit switching signal SW, signal output OUT, NAN
D5 and AND4.

An external circuit switching signal SW is input to the C terminal of the first DFF via the second logic circuit NOT,
An external signal output OUT is input to the C terminal of the second DFF 38 via the buffer 34, and an external signal output OUT is input to the third DFF 38 via the sixth logic circuit NOT36.
Input to the C terminal of the FF, and the first, second and third DFFs 3
The Q outputs of 7, 38 and 39 are connected to the first logic circuit NOT31,
Third logic circuit NOT33, fifth logic circuit NOT35
Through the D terminal of each DFF,
From the third DFFs 37, 38, and 39 input the logic circuit ExOR40, and the output of the logic circuit ExOR40 is the logic circuit AN of the MOS transistor switch circuit 1.
When the output of the edge detection circuit 3 output to the logic circuit NAND5 of D4 and the buffer circuit 2 becomes "1" as described above, the MOS transistor switch circuit 1 is turned on to change the signal input IN to the signal output circuit. Output to ON. The buffer circuit is disabled.

When the circuit switching signal SW is "0" and the signal input I
When N is L and the input signal output ON is L, that is, “0”, the output of the DFF 37 is “0”, the output of the DFF 38 is “1”, the output of the DFF 39 is “1”, and the ExOR 40 Is "0", the MOS transistor circuit is turned off, and the output of the buffer circuit 2 is G
ND.

Next, even if the circuit switching signal SW rises from "0" to "1", the output of the DFF 37 is "0", the output of the DFF 38 is "1", and the DFF 39
Is "1", the output of the ExOR 40 is "0", the MOS transistor circuit is OFF, and the output of the buffer circuit 2 is GND.

Next, when the circuit switching signal SW falls from "1" to "0", the output of the DFF 37 becomes "1", the output of the DFF 38 is "1", and the output of the DFF 39 is "1". Therefore, the output of ExOR 40 is “1”
And the MOS transistor circuit is turned on, and the output of the buffer circuit 2 is disabled.

Here, when the input signal IN switches from L to H, the MOS transistor circuit is ON, so that a high voltage is applied to the signal output circuit OUT and the edge detection circuit 3.
When a high voltage is applied to the edge detection circuit 3, the DFF 38 switches from "1" to "0", the output of the ExOR 40 switches from "1" to "0", the MOS transistor circuit is turned off, and the output of the buffer circuit 2 is turned off. Is enabled. Accordingly, the enable control logic circuit AND4
And a signal output circuit OU while the MOS transistor circuit is turned off after being delayed by the operation time of the transistor.
When the voltage of the signal input IN is applied to T and the PMOS 24 of the buffer circuit 2 is turned on after a delay corresponding to the enable control logic circuit NAND5 and the operation time of the transistor, V
DD is applied to the signal output circuit OUT as an H voltage, and the output of the signal output circuit OUT switches from the MOS transistor circuit to the buffer circuit 2.

Next, when the circuit switching signal SW falls from "1" to "0", the output of the DFF 37 becomes "0", the output of the DFF 38 is "0", and the output of the DFF 39 is "1". Therefore, the output of ExOR 40 is “1”
Then, the MOS transistor circuit is turned on, the output of the buffer circuit 2 is disabled, and returns to the initial state.

As described above, when the MOS transistor switch circuit 1 is on and the buffer circuit 2 is disabled and the signal state changes, a signal is passed through the MOS transistor switch circuit 1 until the buffer circuit 2 operates. Can be transmitted.

Although the MOS transistor switch circuit 1 does not have a driving ability, it does not need to operate a transistor for transmitting a signal, so that high-speed signal transmission is possible. The change in signal state is detected by the edge detection circuit 3, and the operation is performed at high speed through the MOS transistor switch circuit 1 capable of high-speed transmission until the buffer circuit 2 operates. When the buffer circuit 2 is enabled, the MOS transistor switch circuit 1 is turned off, and the output from the buffer circuit having the driving capability is obtained, and the circuit has a high driving capability. By connecting the buffer circuit and the MOS transistor switch circuit in parallel, it is possible to realize a circuit which can operate at the same high speed as the switch circuit and has a driving ability.

When these operations are completed, the MOS transistor 1 is turned off, so that only the signal is connected via the buffer circuit. Unlike the case where the MOS transistor is always connected, the output side of the buffer circuit is not connected. The signal waveform containing noise does not affect the input side of the buffer circuit.

FIG. 4 shows an embodiment using the high-speed and high-drive signal transmission circuit of the present invention. Reference numeral 7 denotes a DFF which operates in synchronization with the reference signal clock CLK. The data signal DATA is input to the D terminal of the DFF, and the output of the Q terminal is input to the high-speed high-drive signal transmission circuit 6 as an input signal IN. Then, transmission is performed through the high-speed and high-drive signal transmission circuit 6 of the present invention. The reference signal CLK that has passed through the buffer 8 is input to the high-speed and high-drive signal transmission circuit 6 as a circuit switching signal SW and is input to the C terminal of the DFF 7.

FIG. 5 is a time chart of the high-speed and high-drive signal transmission circuit of FIG. 4 using a clock as the switch signal. When the clock CLK switches from H to L while DATA is L, the signal switching signal SW falls with a delay by the buffer 8. The MOS transistor switch circuit 1 changes from OFF to ON, and the buffer circuit 2 changes from enable to disable. The signal input IN is at L.

When the clock CLK rises in this state, the signal input IN changes from L to H. Since the MOS transistor switch circuit 1 is ON, the signal input IN is output to the signal output OUT. The changing edge is detected by the edge detection circuit 3, and the enable control logic circuit AN
The MOS transistor switch circuit 1 is turned off, the buffer circuit 2 is switched to enable, and the signal output OU is delayed by delaying the operation time of the transistor by D4 and NAND5.
T switches from the MOS transistor switch circuit 1 to the buffer circuit 2, and the voltage of VDD is output.

When the clock CLK falls, the circuit switching signal SW falls. Here, the MOS transistor switch circuit 1 is turned on, and the output of the buffer circuit 2 is switched to enable. At the next rising edge of the clock CLK, the signal input IN changes from H to L, the MOS transistor switch circuit 1 is turned off, the buffer circuit 2 is enabled, and returns to the initial state.

Next, a description will be given of a second embodiment of the high-speed and high-drive signal transmission circuit according to the present invention. FIG. 6 is a circuit diagram of a high-speed and high-drive signal transmission circuit according to a second embodiment of the present invention. In the second embodiment, the AND of the first embodiment is used.
4 and the MOS transistor switch circuit 1, and between the NAND 5 and the buffer circuit 2, a delay circuit 68,
And a delay circuit 69 are provided. In the drawing, the number is represented by 2 or 4, but it is sufficient to insert a required number individually in series according to a desired delay time.

Since the configuration and functions other than the delay circuit 68 and the delay circuit 69 are the same as those of the first embodiment, the description is omitted.

In order to change the timing of switching from the MOS transistor switch circuit 61 to the buffer circuit 62, a delay is provided between the AND 4 and the MOS transistor switch circuit 1 and between the NAND 5 and the buffer circuit 2 in the first embodiment. By providing the circuit 68 and the delay circuit 69, it is possible to create a control timing that is optimal for the actual signal transmission of the circuit.

[0041]

As described above, in the high-speed and high-drive signal transmission circuit of the present invention, the buffer circuit and the MOS transistor switch circuit are connected in parallel, and by controlling them, the high-speed operation equivalent to that of the switch circuit is achieved. Is possible,
In addition, there is an effect that a circuit having a driving ability can be realized.

When the rising operation is completed, the MO
Since the S transistor is turned off, only the signal is connected via the buffer circuit, and unlike the case where the MOS transistor is always connected, the signal waveform containing noise on the output side of the buffer circuit is changed to the input side of the buffer circuit. There is also an effect that it does not affect the image.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-speed and high-drive signal transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the buffer circuit of FIG.

FIG. 3 is a detailed circuit diagram of the edge detection circuit of FIG. 1;

FIG. 4 is an embodiment using the high-speed and high-drive signal transmission circuit of the present invention.

FIG. 5 using a clock as a switch switching signal;
4 is a time chart of the high-speed and high-drive signal transmission circuit of FIG.

FIG. 6 is a circuit diagram of a high-speed and high-drive signal transmission circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1, 61 MOS transistor switch circuit 2, 62 buffer circuit 3, 63 edge detection circuit 4, 64 logic circuit AND 5, 65 logic circuit NAND 6, 66 high-speed high-drive signal transmission circuit 7, 37, 38, 39 D flip-flop Buffers 8, 34 Buffer 21 Logic circuit NAND 22 Logic circuit NOR 23, 31, 32, 33, 35, 36 Logic circuit NO
T 24 PMOS 25 NMOS 40 Logic circuit ExOR 68, 69 Delay circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (6)

(57) [Claims] 1. A high-speed and high-drive signal transmission circuit used as a digital input / output interface of a semiconductor integrated circuit, comprising: a MOS transistor switch circuit for outputting a signal output from an input signal input; A buffer circuit connected to the
A control circuit for controlling the transistor switch circuit and the buffer circuit, said control circuit, said the signal input by only the MOS transistor switch to <br/> when the signal input changes from L to H Output as a signal output, the signal input
Is switched from L to H and then switched to the buffer circuit with a delay of a predetermined timing defined by an internal circuit , and the buffer circuit only switches the signal output at a voltage corresponding to the signal input. A high-speed, high-drive signal transmission circuit characterized by outputting. 2. The control circuit according to claim 1, wherein said control signal rises.
An edge detection circuit that changes in edge / fall;
The edge detection circuit includes five logic circuits NOT, one buffer, three D flip-flops, and a logic circuit Ex.
And an external circuit switching signal is input to the C terminal of the first D flip-flop via the second logic circuit NOT, and an external signal output is input to the second terminal via the buffer. The signal is input to the C terminal of the D flip-flop, and the signal output from the outside is supplied to the third terminal via the sixth logic circuit NOT.
, And the Q outputs of the first, second, and third D flip-flops are connected to the first logic, respectively .
Logical circuit NOT, third logical circuit NOT, and fifth logical circuit
The logic circuit ExOR is input to the D terminal of the flip-flop via a circuit NOT, and the Q bar output of the first to third D flip-flops is input to the logic circuit ExOR.
Claim that controls the respective OR output is output to the buffer circuit and the MOS transistor switch 1
2. A high-speed and high-drive signal transmission circuit according to claim 1. 3. The control circuit receives an output of the edge detection circuit and an enable input from the outside, and
3. The high-speed and high-drive signal transmission circuit according to claim 2, further comprising a logic circuit that outputs a control signal to each of the OS transistor switch circuit and the buffer circuit. 4. The control circuit according to claim 2, further comprising a delay circuit for adjusting a timing from a signal rise to switching from the MOS transistor switch circuit to the buffer circuit to a predetermined value. A high-speed and high-drive signal transmission circuit according to claim 3. 5. The high-speed and high-drive signal transmission circuit according to claim 2, wherein the switching signal from outside the edge detection circuit is a clock signal. 6. The logic circuit according to claim 6, wherein the buffer circuit is a logic circuit NAN.
D, a logic circuit NOR, a logic circuit NOT, a PMOS, and an NMOS, and the source of the PMOS is VD
D, the drain of which is connected to the drain of the NMOS and the output circuit OUT,
A source of the NMOS is connected to GND, a drain is connected to a drain of the PMOS and an output circuit OUT,
The logic circuit NAND has a signal input and the logic circuit NO.
The output from the control circuit via T is input, the output is inverted and connected to the gate of the PMOS, and the signal input and the output from the control circuit are input to the logic circuit NOR. high-speed and high-driven signal transmission circuit according to claim 1 connected to said N MOS gate.