JPS63122314A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the production of a large power noise by giving a signal being the result of a delay given to a data signal or its inverted signal by means of a delay means by a prescribed time as one input respectively to two multi-input logic circuits giving a gate input to a P-channel and an N-channel transistors (TRs) for output so as to suppress a through-current. CONSTITUTION:With a data signal D changed from a high level to a low level, an output point (a) of a NAND gate 11 goes to a high level as soon as a level of the data signal D is lower than its logic threshold value. On the other hand, a level of an output point (b) of a NOR gate 12 goes to a high level with a delay by a delay time after the input of a delay means DL goes to a low level till the output goes to a low level. Thus, the operation of the N-channel TR TN going from the off-state to the on-state so far is started slowly more than the operation of the P-channel TR TP from the on-state so far to the off-state and a through-current is decreased. Similarly, when the data signal D changes from a low level to a high level, the through-current is decreased by the reversing operation in comparison with that above.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an output circuit formed in a semiconductor integrated circuit, and particularly relates to a CMO8 (complementary insulated gate type) output circuit. Regarding buffer circuits.

(Prior Art) FIG. 8 shows a conventional tri-state output buffer circuit. That is, a P-channel transistor TP and an N-channel transistor are connected in series between the vDD power supply node and Vss' (a ground terminal), and the data signal is connected to the f- of the P-channel transistor TP. The output of the NAND gate 81 which inputs the output enable signal EN is input, and the EN signal obtained by inverting the EN signal by the I/Putter 82 and the data signal are input to the ff-) of the N-channel transistor TN. The output of the NOR gate 83 is input. Then, the drain interconnection point of both the transosters TP p'r becomes the output node N0, and the output signal OUT is taken out.

In the above output buffer circuit, the EN signal is at a low level (
'0' level), the output of the Nand gate 81 is at a high level ('1' level) and the output of the NOR gate 83 is at a low level, so both transformers 'rp j 'r are in the off state, and the output node No. becomes a high impedance state. On the other hand, when the EN signal is at a high level, the logic level corresponding to the data signal is at the output node N.
Appears in o. That is, if the data signal is at a high level,
The output of the Nand gate 81 and the output of the NOR gate 83 are each at a low level, and the P-channel transistor TP
is in the on state, the N-channel transistor TN is in the off state, and the output node No becomes high level. Contrary to the above, if the data signal is at a low level,
and the output of the NOR gate 83 are at a high level, the P-channel transistor T is turned off, the N-channel transistor T is turned on, and the output node No becomes a low level.

By the way, when the EN signal is at a high level, the two outputs Tp'r
In the process of inverting the gate potential of N, before one transistor turns from on to off, the other transistor turns from off to on. In other words, both transistors TP #'rN
There is a period when both are on. During this period, VDD
'A through current flows from the FIL source node to the V118 power supply node, which is undesirable, and in the circuit shown in FIG. 8, the above-mentioned period is shortened. That is, when the data signal changes from a high level to a low level, the Nant gate 81
Comparing the response time of the output point a of the output point a and the output point of the node y-ss to change from a low level to a high level, we get the following:
Nando p −) 81 output point a is Noah gate 83
The output point is faster than that. Therefore, the timing at which the P-channel transistor T starts to turn off is faster than the timing at which the N-channel transistor TN starts to turn on, and the period during which both transistors TPs'rN are both in the on state is short. It becomes like this. Similarly, when the data signal changes from a low level to a high level, the timing at which the N-channel transistor T starts to turn off is farther from the timing at which the P-channel transistor TP starts to turn on, and both transistors Tp p TN The period in which it is in the on state becomes shorter.

By the way, the CMO 8 output cover has a large current drive capacity.

In an LSI (large scale integrated circuit) having a large number of circuits, the through current component of the buffer has a large effect on the power consumption of the entire LSI chip, so it is necessary to reduce it. Therefore, in the conventional exit cover, Noah, shown in Figure 8,
In order to enhance the common current reduction effect, the Nant gate 81
The logic threshold of the node 83 is set lower than HVoo, and the logic threshold of the node 83 is set higher than WVpo, thereby increasing the difference in response time between output points a and b to the level inversion of the data signal. However, since the range in which such a logic threshold value can be adjusted is limited, it is not possible to sufficiently reduce the through current of the buffer. Also, as mentioned above, the logic threshold of the NAND gate 81 and the NOR gate 83 is set to 'A'.
If it is moved slightly away from voo, the noise margin of Son(Jn becomes small, the current driving ability of the N-channel transistor of the NAND gate 81 and the P-channel transistor of the Far gate 83 decreases significantly, and the operating speed of the buffer decreases significantly. In this way, when conventional output covers and NORs try to suppress through current, they result in a reduction in noise margin and a significant reduction in operating speed, so they are designed to balance these characteristics. The degree of freedom when doing so is small.

(Problems to be Solved by the Invention) The present invention solves the problem by adjusting the logic values of the logic circuit on the gate input side of the P-channel transistor and the logic circuit on the gate input side of the N-channel transistor as described above. It was designed to solve the various problems associated with trying to suppress current, and can suppress through current without reducing noise margin or significantly reducing operating speed. It is an object of the present invention to provide an output buffer circuit that can shift the operation timing of individual circuits when used simultaneously, has a small current in a source wire, and can prevent the generation of large power supply noise.

[Structure of the Invention] (Means for Solving the Problems) The output buffer circuit of the present invention includes a first multi-input logic circuit that provides a gate input of a P-channel transistor for output, and a gate of an N-channel transistor for output. For the second multi-input logic circuit that provides input, then:r'L('3
As one input, the data signal is characterized in that a signal obtained by delaying the inverted signal of the data signal by a predetermined period of time by a delay means is provided.

(Operation) By setting the delay time of the delay means to a desired value,
It is possible to adjust the start timing of the 2nd inversion operation of one of the P-channel transistor and N-channel transistor for output and the start timing of the off-on inversion operation of the other, and it is possible to reduce the through current of the P and F circuits. can.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a CMO 8 output cover 77 circuit with large current drive capability formed in an integrated circuit. Torra/Sosta TN are connected in series. The above P-channel transistor T
The output of the three-man powered NAND f-to 11 is input to the gate of p, and the output of the three-man powered NOR gate 12 is input to the gate of the N-channel trannostar TN. The three inputs of the NAND gate 11 are a data signal, an output (delayed data signal) of a delay means DL for delaying the data signal for a predetermined period of time, and an enable signal EN. Further, as the three inputs of the NOR gate 12, a data signal, a delayed data signal, and an output BN of an inverter 13 that inverts the output enable signal EN are input.

Next, the operation of the tristate W output buffer circuit will be explained with reference to the timing chart shown in FIG. i2. E
When the N signal is at a low level, the output point a of the NAND f-to 11 is at a high level, and the output point of the NAND r-to 12 is at a low level, so that both transistors TF p'r, , are in the off state. , the output node No becomes in a high impedance state. On the other hand, when the EN signal is at a high level, the nine logic levels are set to the output node No. according to the data signal.
appears in That is, if the data signal is at a high level f,
The output of the Nant gate 11 and the output of the F gate 12 are at a very low level, and the P-channel transistor TP
is in the on state, the N-channel transistor TN is in the off state, and the output node No becomes high level. Contrary to the above, if the data signal is at a low level, the NAND gate 11
and the output of node 12 are at a high level, indicating that the p-channel transistor TP is in the off state.
N-channel transistor TN is turned on, and output node No becomes low level.

In the above operation, the response time of the output points a and b when the level of the data signal is inverted is as described below due to the presence of the delay means DL. That is, when the data signal changes from high level to low level, the output point a of the Nant gate 11 becomes high level at the same time as the level of the data signal becomes lower than its logic threshold (usually 11I2Voo). , the output point of the NOR gate 12 becomes high level with a delay corresponding to the delay time from when the input of the delay means DL becomes low level until the output becomes low level. After a while,
The P-channel transistor TP changes from the on state to the off state for up to seven times, while the N-channel transistor TN
The operation from the off state to the on state until tL starts later, and the through current is reduced. Similarly, when the data signal changes from low level to high level, the output point of NOR gate 12 becomes low level at the same time as the level of the data signal becomes higher than its logic threshold (usually '4Vno). Therefore, the output point 1 of the Nant gate 11 becomes low level after a delay corresponding to the delay time from when the input of the delay means DL becomes high level until the output becomes high level. Therefore, the P-channel transistor T? The operation from the OFF state to the ON state starts later, and the through current is reduced.

According to the output buffer circuit described above, one through current can be easily reduced by setting the delay time of the delay means DL to a desired value. Moreover, when designing to optimize the delay time, it is only necessary to consider the trade-off between the magnitude of the through current and the reduction in operating speed of the buffer circuit due to the delay operation.

FIG. 3 shows a tri-state a output buffer circuit according to another embodiment.Compared to the circuit shown in FIG. 1, the data signal is inverted by an inverter 31, and the inverted data signal is input to the delay means DL. In place of the three-man powered NAND gate 11 shown in Fig. 1, a three-man gate 32 and an inverter 33 are connected in series, and the three-man powered E
The first point is that the N signal, image signal, and delay means output are input.
The difference is that a three-man powered NAND gate 34 and an inverter 35 are connected in series in place of the three-man powered Noah route 12 shown in the figure, and the EN signal, i signal, and delay means output are input as the three-man powered input, and the other points are the same. Therefore, the same reference numerals as in FIG. 1 are shown.

The operation of the circuit shown in FIG. 3 is performed in accordance with the operation of the circuit shown in FIG. 1 as described above.

FIG. 4 shows an output buffer circuit according to another embodiment, in which two output P-channel transistors are connected to the TPO gate.
The output of the human-powered NAND route 4 is input, and the gate of the N-channel transistor T for output is connected to the two-powered Noah gate 4.
2 is input, and a data signal is input as an input to each of the Nant gate 41 and the NOR gate 42. Then, the data signal passes through the variable delay delay VDL and becomes the above-mentioned output. The variable biting means VDL is complementary controlled by a control signal C and a signal C obtained by inverting this by an inverter 51, for example, as shown in FIG. A second CMOS switch (consisting of an LP channel transistor P and an N channel transistor Qs connected in parallel) 52 and 53 is used, and the data signal is delayed by a delay means DL to switch the data signal from the first CMOS switch to the first CMOS switch. The data signal is input to the switch 52, and the data signal is directly connected to the second C.
It serves as an input to the MOS switch 53, and the output terminals of the two CMOS switches 52 and 53 are commonly connected.

According to the circuit shown in FIG. 4, the second CMOS switch 53 is controlled to be turned on when high-speed operation is required, and the second CMOS switch 53 is turned on when it is desired to reduce through current to reduce consumption and mental effort. It becomes possible to select to control one CMOS switch 52 to turn on.

Note that the delay means used in each of the embodiments described above can be a Japanese type delay element, but for example, as shown in FIG. By using n, it is possible to obtain a delay time of one cycle of the black signal φ.

FIG. 7 shows a group of output buffer circuits in an LSI K according to an application example of the present invention.
7 are used in parallel. Here, for example, the output 2277 circuits 7Jo to 71γ are as shown in FIG. Same delay time 1
．． Each of the delay means in the four output buffer circuits 714 to 717 for the remaining data D4 to D is configured to have the same delay time tb (different from 1. above).

Therefore, when outputting the r-ta, the output cover and the f-circuit 71°~
Since the operation timings of the 71s group and the output buffer and 77 circuits 714 to 717 group are different, all output buffer circuits 71
Compared to the case where 0 to 717 operate at the same time, the current in the power supply line becomes smaller, the power supply noise becomes smaller, and the through current of each circuit is reduced, resulting in a reduction in current consumption.

[Effects of the Invention] As mentioned above, according to the output 2277 circuit of the present invention, the through current can be reduced by adjusting the inversion timing of the output P-channel transistor and N-channel transistor using a delay means. , can be done. However, problems such as a reduction in noise margin or a significant reduction in operating speed that occur when adjusting the logic threshold of a gate as in the conventional example do not occur. Maji, the above output 227
By using 7 circuits, the operation timing of several circuits can be shifted when multiple circuits are used at the same time, so the current in the power supply line becomes smaller, preventing large power supply noise from occurring, and improving the operation of the LSI. This can contribute to improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the output buffer circuit of the present invention, FIG. 2 is a timing diagram showing the circuit operation of I'i, 1i1, and FIGS. 3 and 4 are other embodiments. circuit diagram,
FIG. 5 is a circuit diagram showing an example of the variable delay means in FIG. 4;
FIG. 6 is a logic circuit diagram showing an example of delay means used in each embodiment, FIG. 7 is a logic circuit diagram showing an example of application of the present invention,
FIG. 8 is a circuit diagram showing a conventional CMO8 output buffer circuit. TP...P channel transistor TN...N channel transistor, 11. (32, 33), 41...first multi-input logic circuit, 12. (34, 35), 42...
-N2 multi-input logic circuit, 13.31...inverter, DL...delay means, vDL...variable delay means. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (5)

[Claims] (1) A P-channel transistor and an N-channel transistor connected in series between a high-potential side power supply node and a low-potential side power supply node, and a data signal D or its inverted signal @D@ serve as one input, and the output is A first multi-input logic circuit whose input is the gate input of the P-channel transistor, and a second multi-input logic circuit whose input is the data signal D or its inverted signal @D@ and whose output is the gate input of the N-channel transistor. A multi-input logic circuit, and a delay means into which the data signal D or its inverted signal @D@ is input, delays it by a predetermined time, and provides it as one input of each of the two multi-input logic circuits. Features an output buffer circuit. (2) The output buffer circuit according to claim 1, wherein the delay means is a variable delay means whose delay time is controlled by a control signal. (3) The first multi-input logic circuit is a NAND gate, and the second multi-input logic circuit is a NOR gate, each of which receives a data signal and a signal delayed by the delay means. An output buffer circuit according to claim 1. (4) The first multi-input logic circuit has a NOR gate and an inverter connected in series, and the second multi-input logic circuit has a NAND gate and an inverter connected in series, each of which is an inverted signal of the data signal D. 2. The output buffer circuit according to claim 1, wherein @D@ and a signal delayed by said delay means are input. (5) provided corresponding to each multi-bit data signal,
Claim 1 characterized in that the delay time of the delay means in the output buffer circuit corresponding to some of the data signals is different from the delay time of the delay means in the output buffer circuit corresponding to the remaining data signals. Output buffer circuit described in section.