JPH03198520A - Logic circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a logic circuit and to facilitate the layout by bringing a node to a prescribed level when any transmission gate is turned off in response to a signal on a control line. CONSTITUTION:Signals (a), (c) on a control line inputted to input terminals INA and INC are signals having a longer enable period than that of signals (b), (d) inputted to input terminals INB, IND. Since a series transistor(TR) 1 in a logic circuit operates with a margin for speed, it is not required to increase the operating speed through the increased size of the series TR 1. Thus, the entire layout area is reduced. Moreover, when plural similar logic circuits are manufactured, since it is possible to provide an inverter to invert the signal b, d in common, the number of TRs is reduced by the common share.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit constructed on a semiconductor integrated circuit, particularly to a MOS logic circuit.

[Conventional technology]

A conventional MOS logic circuit, such as an inverter, is shown in FIG. Figure 5 (81 is the logic circuit of the inverter, Figure 5 (b)
FIG. 1 is a circuit diagram showing a circuit in which the circuit of FIG. 5 fa) is expressed using a MOS transistor.

In FIG. 5, ■ is a P-channel type MOS transistor, 2 is an N-channel type MOS transistor, 3 is an inverter, IN is an input terminal, and OUT is an output terminal.

As shown in FIG. 5(b), all input signals are signals on the control lines of the MOS transistors, and the circuit is configured to output a power supply voltage level or a ground level depending on the input conditions.

Conventional multi-input logic circuits are also constructed using a similar method. The circuit shown in FIG. 6(a) is an example of a multi-input logic circuit. FIG. 6(b) is a circuit diagram representing the circuit of FIG. 6(a) using a MOS transistor. In Figure 6, 5 is 4-person power 7)'-off (A
ND-OR) circuit, INA-IND is the input terminal,
In FIG. 6, the same or equivalent parts as in FIG. 5 are given the same reference numerals.

Moreover, a-d are input signals.

As shown in FIG. 6(b), a conventional multi-input logic circuit has a large number of MOS transistors and has a complicated structure.

In addition, in order to realize a multi-input logic circuit, several MO
It is necessary to connect S transistors in series, which reduces the driving ability of the logic circuit.

For example, when two MO5I- transistors are connected in series, the on-resistance of the MO,S) transistor is doubled. Thus, as the number of MO3I-transistors in series increases, the drive capability decreases due to the increase in on-resistance.

In order to make two series MO5I transistors have the same on-resistance as a single MO3 transistor, the MOS transistor width must be doubled.

Therefore, in order to make the driving capability of the series MO3I transistor sufficient, the size of the series MO5 transistor must be increased.

However, since the load capacitance also increases due to the increase in the width of the MOS transistor, the operating speed is not completely the same as that of a single MO3f transistor.

As described above, conventional logic circuits are complex and difficult to layout, and multi-input logic circuits require a very large layout area in order to obtain sufficient operating speed.

[Problem to be solved by the invention]

Conventional logic circuits have had the problem of requiring a large number of MOS transistors to configure a multi-input logic circuit. Furthermore, since there are series transistors in the logic circuit, there is also the problem that the layout area must be increased in order to obtain sufficient operating speed.

The present invention has been made in view of these points, and its purpose is to obtain a multi-input logic circuit that is easy to layout with as few MO3) transistors as possible without causing a decrease in operating speed. It is in.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a plurality of transmission gates that conduct or non-conduct an input signal in response to a signal on a control line, and one node to which the output of each transmission gate is connected. , and a transistor that sets the node to a predetermined potential when any transmission gate is in an off state in response to a signal on a control line.

[Effect]

In the logic circuit according to the invention, when any of the transmission gates is on, the transmission gate immediately propagates the corresponding signal, and when any of the transmission gates is off, the transistor transmits the output of the transmission gate. to a potential of
As a result, the node connected to the output of the transmission gate is also brought to the same potential.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a multi-input logic circuit according to the present invention, and FIG. 2 is a time chart showing the operation timing of the circuit shown in FIG.

In FIG. 1, 1 is a P-channel type MO3) transistor, 2 is an N-channel type MO3) transistor, and 3 is an inverter.

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a multi-input logic circuit in FIG. 6 (al).
and INC are connected to the control line of the MOS transistor. Signal input to the control line, i.e. input terminal INA
The signals input to INC must be exclusively enabled. In other words, the signals a and c input to INA and INC do not become level "L" at the same time.

When either signal a or c becomes “1”, the input terminal [N
The signal sum (yod) input to B or IND is inverted by an inverter and output to the output terminal OUT.
When both and C become level “0”, P-channel type MO
3I--Transistor 1 is turned on and level "1" is output to the output terminal OUT.

In the configuration shown in Fig. 1, as shown in Fig. 2, signals a and c (Fig. 2 (b), (dl)) on the control lines connected to input terminals INA and INC are input to input terminals INB and IND. The signal S, d (signal with a longer enable period than that in Figure 2 (C1, (el)). By doing so, there is a margin in the speed at which the series transistor 1 in the logic circuit in Figure 1 operates. Therefore, there is no need to increase the operating speed by increasing the size of the series transistor 1. Note that FIG. 2(a) shows a clock, and FIG. 2(a) shows a signal at the output terminal OUT.

With such a circuit configuration, the number of transistors is the same as in the conventional case, but there is no need to increase the size of the series transistors. If there is no problem in operating speed, the P-channel MoS transistor 1, which is a series transistor, can be made as small as the device manufacturing limit. This reduces the overall layout area.

Also, when creating multiple similar logic circuits, the signal
Since it is also possible to share an inverter for inverting d, it is possible to reduce the number of transistors accordingly.

FIG. 3 is a circuit diagram showing another embodiment of the multi-input logic circuit according to the present invention. FIG. 3 shows another embodiment in which the present invention is applied to the logic circuit of FIG. 6 (al). In the circuit of FIG. 3, unlike the circuit shown in FIG. A control line (connected to the input terminal INE) must be prepared.The signal e input to the terminal INE is a signal whose level is "1" when the signals a and C are at the level "0".

In FIG. 3, the signal lines connected to the input terminals INA, INC, and INE serve as control lines for the MOS transistor 2. Only one signal on the control line must be enabled at any time.

In other words, multiple signals a, c, and e are at level r at the same time.
It will never become LJ. Either signal a or C is “
1, the signal S or d input to the terminal INB or IND is inverted by the inverter 3 and output to the output terminal OU.
Output to T. When the signal e becomes level "1", the N-channel MOS transistor 2 turns on and becomes level "1".
is output to the output terminal OUT.

With such a circuit configuration, the number of transistors can be reduced, and the overall layout area can also be reduced.

If the period during which the signal on the control line is enabled is lengthened as in the case of FIG. 1, it is not necessary to increase the size of the transistor to which the signal e is input. If there is no problem with operating speed, this MOS transistor can be made as small as the device manufacturing limit.

Further, as shown in FIG. 3, it is preferable to configure the device so that the signal is output via the inverter 3.

When the output is as shown in FIG. 1, the amount of load capacity attached to the output varies depending on the case. This makes it difficult to reduce the size of the transistor that brings the output to level rlJ when all transmission gates are off.

An application example of the logic circuit shown in FIGS. 1 and 3 will be explained using FIG. 4. FIG. 4(a) is a logic circuit diagram of the decoder. FIG. 4 (bl is a circuit diagram showing the case where the present invention is applied to the logic circuit of FIG. 4 (al). In the same figure, 1 is a P-channel type MOS transistor, 2 is an N-channel type MO3L transistor, 3 is an inverter, 4
indicates a 2-person NAND circuit, 5 indicates a 4-person ANDNOR circuit, and 6 indicates a 6-person ANDNOR circuit. Also, INI~IN3. INA and INB are input terminals, and 0UTI to 0UT7 are output terminals.

When Figure 4fa) is made into a circuit in the conventional manner as shown in Figure 6[bl], it features 90 MO3I-transistors, in particular the dotted line shown in Figure 4(a). Considering only the portion consisting of the enclosed AND-NOR circuit and NAND circuit, 48 MOS) transistors are required.

However, in the case of FIG. 4(b) where the present invention is applicable, 70
(MOS) transistors are required. Considering only the part surrounded by the dotted line in FIG. 4(a), only 28 MOS transistors are required.

Furthermore, in addition to reducing the number of transistors, the size of each MO3I transistor constituting the logic circuit can be reduced, so the layout area can be further reduced.

〔Effect of the invention〕

As explained above, the present invention simplifies the configuration of the logic circuit and improves the layout by setting the node to a predetermined potential when any transmission gate is off in response to a signal on the control line. It has the effect of making it easier.

Furthermore, by increasing the number of control lines by one, the number of transistors required for the configuration can be reduced, which has the effect of reducing the cost of the semiconductor integrated circuit.

Furthermore, by making the enable period of the signal on the control line longer than that of the Buddha signal, there is a margin in operating speed, and the size of the MOS transistor does not need to be made larger than necessary, which also has the effect of reducing power consumption. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the logic circuit according to the present invention, FIG. 2 is a time chart showing the operation timing of the circuit shown in FIG. 1, and FIG. 3 is another embodiment of the logic circuit according to the present invention. FIG. 4(a) is a logic circuit diagram of a decoder that shows an example, FIG. 4(b) is a logic circuit diagram when the present invention is applied to FIG. 4(al), and FIG. 5(al is Logic circuit diagram of the inverter, Figure 5 (bl is the circuit in Figure 5 (al) is MOS
) A logic circuit diagram expressed using transistors, Figure 6(a) is a circuit diagram showing an example of a multi-input logic circuit, and Figure 6(b) is a logic circuit diagram using MOS transistors. FIG. 2 is a logic circuit diagram drawn using ■...P channel type MO3I- transistor, 2...
N-channel MOS transistor, 3...inverter, INA~INE...input terminal, OUT...output terminal.

Claims (1)

[Claims] a plurality of transmission gates that make input signals conductive or non-conductive in response to signals on a control line; one node to which the output of each transmission gate is connected; and a transistor which sets the node to a predetermined potential when the gate is also in an off state.