JPH02235294A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of malfunction or the like due to the noise of an output buffer by providing an output buffer circuit with a multiplexing circuit using a node between the source of a PROM cell and a resistance as a switching input to switch the gate inputs of a p-channel MOSFET and an n-channel MOSFET. CONSTITUTION:The output buffer circuit is provided with the resistance 9 connected in series between the source of the PROM cell 10 and the earth potential and the multiplexing circuit 6 using the node between the source of the cell 10 and the resistance 9 as the switching input to switch the gate inputs of p-channel and n-channel MOSFETs 2, 4, 3, 5 constituting a part of the output buffer circuit. Thereby, the transistor (TR) size of an output buffer can be switched in accordance with the power supply voltage of an IC and the switching voltage of the TR size can be programmably controlled. Consequently, the generation of various malfunction due to the switching noise of the output buffer can be evaded without reducing the switching speed of an output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit (hereinafter referred to as an IC), and more particularly to an output buffer circuit of an IC composed of MOSFETs.

[Conventional technology]

Conventionally, in the output buffer circuit of this type of IC, it has not been possible to switch the transistor size of the MOSFET forming the circuit.

[Problem that the invention is trying to solve]

Currently, the main cause of noise generation inside an IC is switching of the output signal of the output buffer circuit (hereinafter referred to as switching).
It is. These noises affect other circuits within the IC via the IC's power supply and ground lines, causing malfunctions. Generally, the noise increases as the transistor size of the MOSFET that constitutes the output buffer increases, and the noise increases as the power supply voltage applied to the IC increases.
However, due to the relationship between load capacity and switching speed,
In recent years, with ICs that require high-speed operation, it is impossible to reduce the transistor size of the output buffer MOSFET to an extent that does not generate noise without sacrificing the switching speed of the output signal. As a result,
Particularly in areas with high power supply voltages, malfunctions caused by deterioration of the input level due to noise, counter malfunctions, and dynamic circuit retention failures occurred, which became a bottleneck in IC development. [Means for Solving the Problems] The output buffer variable circuit of the present invention has a PROM cell whose control gate and drain are short-circuited, a PROM write/read circuit, and an input to the PROM cell drain. The output of the readout circuit and
A multiplex circuit that switches to the internal power supply of the integrated circuit, a resistor connected in series between the source of the PROM cell and the ground potential, and a connection point between the source of the PROM cell and the resistor are used as switching inputs, and a part of the output buffer circuit is used as the switching input. It has a multiplex circuit that switches the gate inputs of the P-channel MOSF'ET and the N-channel MOSF'ET. [Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. 1 is the output terminal, 2 and 4 are P-channel MOSFETs, 3
．． 5 is an N-channel MOSFET, and 2-5 constitute an output buffer circuit. 6 is a multiplex circuit that switches the gate inputs of 4 and 5, 7 is an inverter element, 8 is an output signal, 9 is a resistor, 10 is a PROM cell, 11 is a PR
A multiplex circuit that switches the drain input of the OM cell, 12 a write/read circuit for the PROM cell,
13 is a PROM mode signal, and 14 is an inverter element.

The multiplex circuit 6 includes a P-channel MOSFET connected to a power supply 101, a complementary transfer gate composed of a P-channel MOSFET and an N-channel MOSFET 102 and 103, and a
N-channel MOSFE connected to ground potential of 04
It consists of a T and 105 inverter elements. The 11 multiplex circuit includes a complementary transfer gate composed of 111 and 113 P-channel MOSFETs and an N-channel MOSFET, and 1
It is composed of 12 inverter elements.

When the 130PROM mode signal becomes logic “1”, the 11
The write/read circuit of the 120 PROM cells and the IO PROM cell are connected through the multiplex circuit of the 120 PROM cells, the PROM mode is set, and when writing is performed to the 10 PROM cells, electrons are injected into the floating gate in the cell. The threshold voltage (hereinafter referred to as VTM) of the 100PROM cell shifts to a certain level. 1
In order to make the 00PROM cell conductive, this V TM
It is necessary to apply a voltage exceeding 10% to the control gates of the 10 PROM cells. The amount of shift of this VTM can be controlled by setting the write voltage or write time during writing. Also, whether or not the desired VTM has been set can be confirmed by reading out the 10 PROM cells. Now, as an example, the IO(7) PROM cell is written so that VTM=5V.

Next, when the 13 PROM mode signals become logic "0", the 10 PROM cells are connected to the power supply inside the IC.

When the power supply voltage of the IC is less than 5V, the PROM cell 10 is non-conductive and the inverter 14 outputs a logic "1" due to the resistor 9. At this time, in the multiplex circuit 6, the transfer gates 102 and 103 are conductive, and the 1
The P-channel MOSFET 01 is non-conductive, and the N-channel MOSFET 104 is also non-conductive due to the inverter 105. As a result, the output of the inverter 7 is 10.
716.4.5<7) MOSFETt! , 2 and 3 constitute an output buffer circuit with a large transistor size, and drive the output terminal of 1 at high speed.

When the IC power supply voltage is 5V or more, the 100PROM cell is conductive, and the resistance value of 9 is set high, so 14
The inverter outputs logic “1”. At this time, in the multiplex circuit 6, the transfer gates 102 and 103 are non-conductive, and the P-channel MOSFET 101
becomes conductive, and the N-channel MOSFET 104 also becomes conductive due to the inverter 105, and as a result, the P of 4 becomes conductive.
A power supply potential is applied to the gate of the channel MOSFET through 101, and a ground potential is applied to the gate of the N-channel MOSFET 5 through 104.
The SFET becomes non-conductive.

In this case, the output of 7 inverters is 2, 3 MOSF
Just a few MOSFETs can be used as gate input for ET.
This creates an output buffer circuit with a small transistor size to suppress noise generation.

As mentioned above, in areas where the IC's power supply voltage is low and the transistor's current supply capacity is low, the switching speed of the output buffer is more important than the effect of noise caused by output buffer switching on other circuits within the IC. Therefore, it is possible to increase the transistor size of the output buffer and drive the output terminal at high speed. Also, IC
In areas where the power supply voltage of the IC is high and the current supply capacity of the transistor is high, the noise caused by the switching of the output buffer is greater than the switching speed of the output buffer.
Since the effect on other circuits within the circuit is a problem, the transistor size of the output buffer can be reduced to suppress noise generation. Furthermore, since the switching voltage of this output buffer switching circuit can be freely set when writing to the 100PROM cell, it is possible to fine-tune the suppression of noise caused by output buffer switching and the high switching speed. is possible.

〔Effect of the invention〕

As explained above, the present invention provides a PROM cell whose control gate and drain are short-circuited, and a PROM write/write/program.
The input to the readout circuit and the drain of the PROM cell is
a multiplex circuit for switching between the output of the PROM write/read circuit and the internal power supply of the integrated circuit;
A resistor connected in series between the source of the ROM cell and the ground potential and a connection point between the source of the PROM cell and the resistor are used as switching inputs, and the gates of the P-channel and N-channel MOSF'ETs that form part of the output buffer circuit By having a multiplex circuit that switches inputs,
The transistor size of the output buffer can be switched according to the IC power supply voltage, and the switching voltage of the transistor size can be programmably controlled.
without sacrificing output signal switching speed.
Various malfunctions caused by switching noise of the output buffer can be avoided in a region where the power supply voltage is high.

5...N-channel MOSFET, 6...
・・Multi 7”L/x times LIO・・・・・・PRO
M cell, 11...multiplex circuit.

Claims (1)

[Claims] A PROM cell whose control gate and drain are short-circuited, a PROM write/read circuit, and a multiplex circuit that switches the input to the drain of the PROM cell with the output of the PROM write/read circuit and an internal power supply of an integrated circuit; A resistor connected in series between the source of the PROM cell and the ground potential and a connection point between the source of the PROM cell and the resistor are used as switching inputs, and P-channel and N-channel MOS form part of the output buffer circuit.
A variable output buffer size circuit that has a multiplex circuit that switches the gate input of the FET.