JPH0897701A - Smiconductor circuit - Google Patents

Abstract

PURPOSE: To suppress a throughhole current of the semiconductor output circuit by configuring the semiconductor output circuit such a way that conduction timings of transistors(TRs) are set differently from each other when the TRs are conductive. CONSTITUTION: An additional MOS TR P6 whose control electrode receives a signal complementary to a signal given to control electrodes of MOS TRs P1-P5 is provided between a power supply node 1 and a control electrode line comprising resistors R1-R4 each having a definite resistance and interconnecting the control electrodes of the MOS TRs P1-P5 which are connected in parallel between an output signal line 5 and the power supply node 1. When the MOS TRs P1-P5 are not conductive, the additional MOS TR P6 is conciuctive, internal nodes INA1-INA5 are driven to a power supply voltage level by an inverter A1 and the additional MOS TR and the MOS TRs P1-P5 are set in the nonconductive state in the same timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit,
In particular, the present invention relates to a semiconductor circuit which responds to an input signal and outputs a signal of a logic level corresponding to the logic level of the input signal. More specifically, the present invention relates to an output circuit included in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a structure of a conventional output circuit. In FIG. 11, a conventional output circuit is a p-channel MOS transistor connected in parallel between a power supply node 1 supplying a first power supply potential Vcc as a reference potential and an output signal line 5 connected to an output terminal 4. Transistor P1
P5, n-channel MOS transistors N1 to N5 connected in parallel with each other between the output signal line 5 and the ground node 2 supplying the ground potential GND as the second reference potential,
resistors R1 to R4 connected between gate electrodes as control electrodes of the p-channel MOS transistors P1 to P5,
It includes resistors R5 to R8 connected between respective gate electrodes of n channel MOS transistors N1 to N5. The resistors R1 to R4 are connected in series, one end of which is p
Connected to the gate electrode of the channel MOS transistor,
The other end is connected to the gate electrode of the p-channel MOS transistor in the next stage. Similarly, the resistors R5 to R8 are also connected in series, one end of each is connected to the gate electrode of the n-channel MOS transistor of the previous stage, and the other end of each is connected to the gate electrode of the n-channel MOS transistor of the next stage. .

The conventional output circuit further includes an input signal IN.
Receiving an input signal IN1 from the input node 3 via the node 3a and inverting the input signal IN1 to the resistors R1 to R4; and an input signal IN2 applied from the input node 3 to the input node 3b by inverting the resistor R5. ~ Inverter A2 applied to R8 is included. Input signals IN1 and IN
Although 2 is the same signal, it is indicated by a different reference numeral from each other in order to simplify the following description. Next, the operation of the output circuit shown in FIG. 11 will be described with reference to the operation waveform diagram of FIG.

When input signal IN is at L level, inverters A1 keep nodes INA1 to INA5 at H level, and p channel MOS transistors P1 to P5 are all off. On the other hand, due to the inverter A2, the nodes INB1 to INB5 are at the H level and the n channel MO
S transistors N1 to N5 are all in the ON state, and output signal line 5 and output node 4 are at the L level of the ground potential GND level.

When the input signals IN (IN1, IN2) rise to H level, the output signals of the inverters A1 and A2 fall to L level. At this time, the resistors R1 to R4 function as delay elements, and sequentially delay and transmit the output signal of the inverter A1. Similarly, the resistors R5 to R8 also function as delay elements, delaying and transmitting the output signal of the inverter A2. Therefore, first the nodes INA1 and I
The potential level of NB1 falls to L level, the p-channel MOS transistor P1 is turned on, and the n-channel MOS transistor is turned on.
The transistor N1 is turned off. At this time it is still p
The channel MOS transistors P2 to P4 are in the off state, and the n channel MOS transistors N2 to N4 are also in the on state. In this state, output signal line 5 is charged from power supply node 1 via p channel MOS transistor P1. When the predetermined time has passed, the node INA
2 and INB2 fall to L level, p-channel MOS transistor P2 is turned on, n-channel M
The OS transistor N2 is turned off. As a result, the output signal line 5 is connected to the p-channel MOS transistor P1.
The signal DOUT output from its output node A is charged by charging via P2 and P2. Similarly, the nodes INA3 and INB3 fall to the L level, then the nodes INA4 and INB4, and then the node I.
NA5 and node INB5 fall to the L level sequentially. The p-channel MOS transistors P3 to P5 are sequentially turned on, and the n-channel MOS transistor N
3 to N5 are sequentially turned off. As a result, output signal line 5 is charged at high speed by MOS transistors P1 to P5, and output signal DOUT rises to H level.

On the other hand, when input signal IN falls from H level to L level, internal nodes INA1 and INB1
Has a voltage level of H due to the inverters A1 and A2.
It rises to the level and p channel MOS transistor P1
Becomes non-conductive, and the n-channel MOS transistor N
1 is made conductive, and the output signal line 5 is an n-channel MOS.
It is discharged through the transistor N1 and its potential drops slightly. Then, the nodes (INA2, INB2), (I
The potentials of NA3, INB3), (INA4, INB4), and (INA5, INB5) sequentially become H level,
The n-channel MOS transistors N2 to N5 are sequentially turned on, and the p-channel MOS transistor P2 is turned on.
~ P5 are sequentially turned off. As a result, the output signal line 5 is discharged by a sequentially increasing current, and finally discharged at the level of the ground potential GND.

In the structure of the output circuit shown in FIG. 11, one p-channel MOS transistor is divided into five p-channel MOS transistors, and the divided p-channel MOS transistors are divided.
The channel MOS transistors are sequentially turned on to charge the output node, and similarly, one n-channel MOS transistor is divided into five n-channel MOS transistors, and the output signal line and the output node are sequentially discharged to sequentially discharge the output signal line. The following effects will be realized by sequentially driving.

As shown in FIG. 13, an inductive load (parasitic inductance) L1 is present on power supply line 1a for supplying power supply voltage Vcc to power supply node 1 by an output circuit, and a switch for supplying ground voltage to ground node 2 is provided. A similar inductive load (parasitic inductance) L2 also exists on the line 2a.
Similarly, the signal line between the output node 4 and the output pad (including the lead frame) also has a parasitic capacitance C due to the inductive load L3 and the external load and wiring capacitance. If the current supply capability of MOS transistors P and N is increased in order to drive (charge / discharge) output node 4 (4a) at high speed, the following problems occur. That is, the power line 1
A resonance circuit is formed between a and the output node 4a by the inductances L1 and L3 and the capacitance C, and the ground line 2
A resonance circuit is formed between the a and the output node 4a by the inductances L2 and L3 and the capacitance C. When input signal IN falls to L level when the potential of node 4 is at H level, n channel MOS transistor N is rendered conductive, and nodes 4 and 4a are discharged to the ground potential level with the large current supply capability. This discharge corresponds to discharging the electric charge from the load capacitance (parasitic capacitance) C to the ground potential level via the inductances L3 and L2. Therefore, a large current change occurs in the inductance abruptly, and the large drive current lowers the potential of the output node 4a below the ground potential level, so-called undershoot occurs, and this undershoot causes ringing at the output nodes 4 and 4a. appear. The ringing of the output node 4 becomes more severe as the current change increases. This is because the voltage V generated in the inductance is represented by V = -L · di / dt. Where L is the inductance of the dielectric load,
di / dt shows the time change of the current i.

The input signal IN falls from H level to L level, the p-channel MOS transistor P becomes conductive, and n
Similarly, when channel MOS transistor N is rendered non-conductive, a large drive current flows into capacitance C and the potential of node 4 rises to the level of power supply voltage Vcc or higher, as shown in FIG. Such overshoot causes ringing at node 4. When such ringing occurs, the logical level of the output node 4 is not determined until the ringing is stabilized, and the signal output timing is delayed until the ringing is stabilized, which is high speed. The signal cannot be output.

When an overshoot or an undershoot occurs, a large induced voltage is generated by the inductive load L1 or L2 on the power supply line 1a or the ground line 2a,
The power supply voltage Vcc or the ground voltage GND may fluctuate, the input / output level of another circuit using the voltage of the power supply line 1a or the ground line 2a may change, and a malfunction may occur in the other circuit.

As described above, the p-channel MOS transistors P1 to P5 or the n-channel MOS transistors N1 to N5 having a relatively small current driving force are sequentially turned on instead of driving the output node at a high speed with a large driving force. As a result, abrupt current change is prevented, and thus ringing such as overshoot and undershoot is prevented. That is, at first, the output node 4 is charged or discharged with a relatively small current power,
When the potential of the output node 4 changes and the ringing does not occur even if the output node 4 is driven at high speed, all the transistors are made conductive and the output node 4 is charged or discharged at high speed. Thus, it is possible to prevent the occurrence of ringing and prevent the delay of the output signal generation timing.

[0012]

FIG. 15 is a diagram showing a planar layout of a p-channel MOS transistor portion of the output circuit shown in FIG. 11 and its equivalent circuit. FIG.
In (A), active regions (impurity regions) are arranged separately from each other in field active region F. The drain regions D (D1 to D3) and the source regions S (S1 to S3) are arranged alternately. The gate electrodes GA1 to GA5 are arranged between the drain region D and the source region S. That is, in this field active region F, two adjacent p
One impurity region is shared by the channel MOS transistors. The gate electrodes GA1 to GA5 are interconnected by the gate electrode wiring G to form one gate electrode. The source regions S1 to S3 are connected to the power supply line V via the contact holes CHs, and the drains D1 to D3 are connected to the output signal line DT via the contact holes CHd. The output signal line DT and the power supply line V are usually formed of a low resistance aluminum wiring layer, and the gate electrode wiring G is composed of polysilicon having a relatively high resistance value. FIG. 15 (B)
As shown in, the gate electrodes GA1 to GA5 each have a resistance value R1, and the gate electrode wiring portion connecting the adjacent gate electrodes has a resistance value R2. Gate electrode wiring G
Connect all the gate electrode layers GA1 to GA5 to each other, and equivalently the length of these gate wirings becomes long, and the wiring resistance and parasitic capacitance of the gate electrode wiring G delay the propagation of the input signal IN. , MOS transistor P
The conduction timings of 1 to P5 are different from each other.

The larger the signal propagation delay in the gate electrode wiring G, the more gently the output node 4 is driven, and all the MOS transistors become conductive when the potential of the output node 4 changes sufficiently. Generation of noise such as ringing can be suppressed.

In the wiring layout of the p-channel MOS transistor shown in FIGS. 15A and 15B, if the power supply line V transmitting the power supply voltage Vcc is replaced with the ground line transmitting the ground voltage GND, the n-channel MOS transistor is formed. A wiring layout for the transistors N1 to N5 can be obtained.

However, in the case of such a conventional output circuit, the following problems occur.

That is, as can be seen from the operation waveform diagram shown in FIG. 12, for example, the node INA is generated at time Tj.
1 and INB1 both become L level, the remaining internal nodes INA3 and INB3 to INA5, INB5
Is still at H level. Therefore, the p-channel MOS transistor P1 is turned on and the n-channel MOS transistor P1 is turned on.
The transistors N3 to N5 are turned on. Therefore, from the p-channel MOS transistor P1 to the n-channel MO
A current flows to the ground potential level through S transistors N3 to N5. Therefore, as the current consumption increases, the power supply voltage Vcc of the power supply node 1 is discharged, the level of the power supply voltage Vcc fluctuates, and noise occurs, and a current flows to the ground node 2. There is a problem that the voltage level of the ground voltage GND rises and noise occurs in the ground voltage.

This is also because when the input signal IN falls from the H level to the L level, the node IN at the time Th.
When both A1 and INB1 are at H level, the node I
When NA3, INB3 to INA5, and INB5 are still at L level, the n-channel MOS transistor N1 is in the ON state, and the p-channel MOS transistors P3 to P5 are in the ON state, the power supply voltage Vcc is similarly changed to the ground voltage G.
There is a problem that noise is generated in the ND and the consumption current increases due to the through current.

Further, in order to further reduce the noise of the output signal, when the resistance of the gate electrode wiring G is increased, it is necessary to increase the resistance value R2 of the gate electrode connecting portion in FIG. 15B. In this case, since the gate electrode wiring layer is made of polysilicon, it is necessary to increase the length of this portion, the pattern area of the gate electrode wiring becomes large, and the area occupied by the output circuit accordingly increases. Occurs.

Further, in order to realize high-speed operation of the semiconductor integrated circuit including the above-mentioned output circuit, the resistance value R1 of the gate electrode wiring is made small and the signal propagation delay of the gate electrode wiring is made small. In order to make the resistance values R1 and R2 of the gate electrode wiring shown in FIG. The problem of increase arises.

Therefore, an object of the present invention is to provide a semiconductor circuit which can stably generate an output signal with a small occupied area and low power consumption.

[0021]

SUMMARY OF THE INVENTION In summary, the present invention is an output circuit including a plurality of transistor elements connected in parallel to each other to drive an output node, and when these transistors are in a conductive state, the conductive timings are mutually different. Are different from each other, and when these MOS transistors are in the non-conducting state, they are all in the non-conducting state at the same time.

According to another aspect of the semiconductor circuit of the present invention, a reference node supplying a first reference potential and an output signal line coupled to the output node are connected in parallel with each other, and each has a first logic level. A plurality of first transistors that conduct when a signal of is applied to the control electrode thereof, a control electrode line having a significant resistance value interconnecting the control electrodes of the plurality of first transistors, and a reference node. Generating a pair of complementary signals from an input signal and at least one second transistor which is provided between the control electrode line and conductive when a signal of the first logic level is applied to the control electrode;
Outputs of applying one and the other of the pair of generated complementary signals to the control electrodes of the first and second transistors, respectively.

According to another aspect of the semiconductor circuit in the present invention, the first reference node supplying the first potential and the output signal line coupled to the output node are connected in parallel to each other, and each control electrode is connected to the first reference node. A plurality of first transistors that conduct when given a signal of logic level 1 and a first control electrode line that has a significant resistance value and interconnects the control electrodes of the plurality of first transistors; At least one second transistor connected between the first reference node and the first control electrode line and conducting when a signal of a first logic level is applied to the control electrode; and a first potential A plurality of first reference nodes that are connected in parallel between a second reference node that receives a second potential of a logic complementary to the output signal line and that conducts when a signal of the second logic level is applied to the control electrode. 3 transistors and these multiple A second control electrode line having a significant resistance value for interconnecting the control electrodes of the third transistor and a second logic connected to the control electrode connected between the second power supply node and the second control electrode line. A pair of complementary logic signals is generated from an input signal and at least one fourth transistor which is conductive when a level signal is applied, and the pair of complementary logic signals is supplied to the first and second control power supply lines. Means for providing one signal of the signal pair and for providing the other signal of the complementary logic signal pair to the control electrodes of the second and fourth transistors.

A semiconductor circuit according to a third aspect of the invention receives a delay element that delays a signal applied to an input node for a predetermined time and outputs the delayed signal to an internal input node, an output signal line connected to the output node, and a reference voltage. A plurality of transistors, which are connected in parallel between the reference node and the output signal line and which conduct when a signal of the first logic is applied to their control electrodes, and a plurality of transistors, which are respectively connected between the control electrodes of these transistors. A plurality of logic gates connected in series with each other,
Each of the plurality of logic gates has a first input connected to the input node, a second input connected to the control electrode of the preceding-stage transistor, a control electrode of the next-stage transistor, and a second input of the next-stage logic gate. And an output connected to. Each of the plurality of logic gates sequentially delays the potential of the internal input node by a predetermined time when the potential of the internal input node is at the first logic level and transfers the signal of the internal input node to the second level. At the logic level, the signal at the input node is transmitted to the output with substantially the same delay time as the delay element.

According to a fourth aspect of the semiconductor circuit, the delay element of the third aspect includes a negative delay element which inverts the signal applied to the input node and delays it for a predetermined time to form an inversion delay, and includes a plurality of logic elements. Each of the gates has a second negative delay element that inverts the signal applied to the second input, and the same gate delay as the first negative delay element, and the output signal of the second negative delay element. Second, receiving the signal from the input node
A gate element that outputs a signal of the second logic level to its output when the signal applied to the input of the first logic level is the first logic level.

According to a fifth aspect of the semiconductor circuit, the delay element of the fourth aspect comprises a buffer delay element for buffering a signal applied to an input node and delaying the signal for a predetermined time, and each of the plurality of logic gates. Receives the signal applied to the second input and the signal applied to the first input, and when the signal applied to the first input is at the second logic level, the signal of the first logic level is A gate element for outputting and a negative delay element for inverting and delaying the output signal of the gate element are provided. The sum of the gate delays of the gate element and the negative delay element is substantially the same as the gate delay of the buffer delay element.

A semiconductor circuit according to a sixth aspect includes a plurality of transistors connected in parallel with each other between a reference node supplying a reference potential and an output signal line connected to the output node. Each of the plurality of transistors has one conduction node connected to the reference node, the other conduction node connected to the output signal line, one end and the other end, and a first conduction node between the one conduction end and the other conduction end. And a control electrode having a resistance value of 1.

According to a sixth aspect of the semiconductor circuit, the control electrodes of the plurality of transistors are connected to each other by alternately connecting the adjacent one end and the adjacent other end so as to form a U-shaped gate electrode layout pattern. Including connection wiring. The interconnection line has a second resistance value that is greater than the first resistance value.

[0029]

According to another aspect of the semiconductor circuit of the present invention, the control electrode line delays and transmits the signal of the control electrode of the first transistor connected by its resistance value, and the second transistor controls the plurality of transistors. The control electrode receives a signal complementary to the signal applied to the electrode, and is rendered conductive with the first transistor in a complementary manner. When the plurality of first transistors are conducting, the second transistor is non-conducting, and the plurality of first transistors are sequentially conducting by a signal given via the control electrode line, while the plurality of first transistors are conducting. Is turned off, the second transistor is turned on and transmits the reference potential to the control electrode line. The control electrode line is driven by the voltage applying means and the second transistor element, and is driven at a high speed to a voltage level that turns off the first transistor, and the plurality of first transistors are turned off at substantially the same timing. It This reduces ringing generation and current consumption at the output node.

According to another aspect of the semiconductor circuit of the present invention, the voltage applying means applies complementary signals to the first and third transistors and the second and fourth transistors. When the first transistor is conductive, the plurality of first transistors are sequentially conductive due to the resistance value of the first control electrode line. On the other hand, when the first transistor is non-conductive, the first voltage is applied by the voltage applying unit and the second transistor. The control electrode line is driven to a voltage at which these first transistors are turned off, and brought into a non-conducting state at almost the same timing.

An input signal is delayed and transmitted to the third transistor by the resistance value having the second control electrode line, and the third transistor is sequentially brought into the conducting state when being conducted, and is brought into the fourth state when being brought into the non-conducting state. Since the transistor is rendered conductive, the voltage applying means and the fourth transistor drive the second control electrode line at a high speed to a voltage level at which the third transistor is rendered non-conductive, and therefore at substantially the same timing. The third transistor is turned off. The first and third transistors complementarily become conductive / non-conductive. The current driving of the output node is sequentially performed, the occurrence of ringing is suppressed, and when one transistor is turned on, the other transistor is turned off at substantially the same timing. Through current flowing between the first and third transistors can be prevented.

According to another aspect of the semiconductor circuit of the present invention, logic gates are connected between control electrodes of a plurality of transistors, and those logic gates are connected in cascade. When the signal transmitted from the delay element to the internal input node is the first logic, the logic gate delays the signal given to each input node and applies it to the control electrode of the corresponding transistor element via its output. Thereby, the plurality of transistors are sequentially turned on. On the other hand, when the signal transmitted from the delay element to the internal input node has the second logic, the plurality of logic gates outputs the signal of the second logic level through the output of each transistor with the same gate delay as that of the delay element. Apply to the control electrode of the device. As a result, multiple transistors are all turned off at the same timing,
It is possible to reduce the consumption current (suppress the through current) and prevent the ringing of the output node due to the drive current at the time of conduction.

According to another aspect of the semiconductor circuit of the present invention, the delay element inverts and outputs the signal applied to the input node, and the logic gate also has the second negation delay element applied to the second input. The inverted signal is inverted and delayed and given to the gate. The second negative delay element applies a signal of the second logic level to the gate when the signal applied to the second input is the first logic level, and the gate applies the signal applied to the first input to the gate. Regardless, the signal given from the second negative delay element is delayed and transmitted to the logic gate of the next stage. As a result, the plurality of transistors are sequentially turned on. On the other hand, when the signal applied to the second gate is at the second logic level, the gate applies the signal at the second logic level to its output. The signal of the input node is commonly applied to the plurality of logic gates at the second input. Therefore, the delay of the gate of the logic gate is the same as the gate delay required for the delay element, the plurality of transistor elements are all rendered non-conductive at the same timing, and the current consumption (through current) is reduced.

According to another aspect of the semiconductor circuit of the present invention, the delay element stores the logic of the input signal and transmits it to the internal node. Is commonly applied with the signal of the second logic. The logic gate outputs a signal of the second logic level to its output with the same delay time as the buffer delay element, and renders all the plurality of transistors non-conductive at the same timing. When the input signal is at the first logic level, the logic gate functions as a delay element to sequentially transfer the signal supplied from the buffer delay element and sequentially turn on the plurality of transistors, thereby sequentially increasing the drive current of the output node. The occurrence of ringing at the output node is suppressed.

According to another aspect of the semiconductor circuit of the present invention, the gate electrode line interconnecting the gate electrodes of the plurality of transistors is higher than the resistance value of the wiring forming the gate electrode, and therefore the area occupied by the gate electrodes is small between the gate electrodes. The resistance value can be set to a desired value, and a plurality of transistors can be brought into a conductive / non-conductive state by shifting a timing of a desired time.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. The present invention relates to an output circuit for outputting a signal to the outside through an output terminal connected to a pad, and in a semiconductor device, the output signal line or a specific signal line is set to a logic level of an internal signal in response to an input signal. Applicable to both a circuit having a buffer function for driving to a corresponding logic level and an output circuit provided at an output stage of a certain semiconductor circuit in a semiconductor device in which a plurality of semiconductor circuits are formed on the same semiconductor chip. You can Further, the voltage level of the signal output from the semiconductor circuit of the present invention is not limited to the power supply potential Vcc and the ground voltage GND, and the high voltage Vpp higher than the power supply voltage Vcc and the negative voltage Vbb lower than the ground voltage GND and Reference voltage Vre such as intermediate potential
f Any voltage level may be used. In the following description, for convenience of description, the semiconductor circuit according to the present invention is described as a circuit that outputs a signal having an amplitude between power supply voltage Vcc and ground voltage GND.

[Embodiment 1] FIG. 1 is a diagram showing a structure and operation waveforms of a semiconductor circuit according to a first embodiment of the present invention. FIG. 1A shows a portion of a circuit which drives output node 4 to power supply potential Vcc through output signal line 5.

In FIG. 1A, a plurality of semiconductor circuits (five in this embodiment) are connected in parallel between the output signal line 5 connected to the output node 4 and the power supply node 1. A plurality of p-channel MOS transistors (insulated gate field effect transistors) P1 to P5 and a plurality of gate electrodes (control electrodes) of the plurality of p-channel MOS transistors P1 to P5 which are connected in series with each other (this embodiment). 4 resistors in the example) R1 to R
4 and an inverter A1 for inverting the input signal IN1 applied to the input node 3a and transmitting the inverted signal to the internal node INA1.
And a p channel MOS transistor P6 electrically connecting power supply node 1 and internal node IN5 in response to input signal IN1 applied to internal node 3a. The gate electrodes of the MOS transistors P1 to P5 are connected to the internal nodes INA1 to INA5, and the resistors R1 to R4 are connected.
Are connected in series between these internal nodes INA1 to INA5. That is, the resistor R1 changes to the internal node INA1.
And INA2, a resistor R2 is connected between internal nodes INA2 and INA3, a resistor R3 is connected between internal nodes INA3 and INA4, and a resistor R4 is connected between internal nodes INA4 and INA5. .

P channel MOS transistor P6 receives input signal IN1 at its gate electrode from internal node 3a through low resistance interconnection 7 formed of aluminum, for example. That is, the p-channel MOS transistor P6
And p-channel MOS transistors P1 to P5 receive signals of opposite phases (logic different) to their respective gate electrodes. Next, operation of the semiconductor circuit shown in FIG. 1A will be described with reference to an operation waveform diagram of FIG.

When the input signal IN1 is at H level, the MOS
The transistor P6 becomes non-conductive, and the input node IN
A1 to INA5 are set to L by the output signal of inverter A1.
Since it is set to the level, the MOS transistors P1 to P5 are rendered conductive. In this state, output signal line 5 and output node 4 are charged to the level of power supply voltage Vcc through MOS transistors P1 to P5.

When input signal IN1 falls from H level to L level at time T0, the output signal of inverter A1 (potential of input node INA1) rises from L level to H level. At this time, again, the MOS transistor P6
Receives an input signal IN1 via internal wiring 7 and becomes conductive to charge internal node INA5 to the power supply potential Vcc level. When the current driving capability of MOS transistor P6 (for example, the ratio W / L of channel width W to channel length L) is set to an appropriate value, internal nodes INA1 to INA are selected.
A5 is charged to the power supply potential Vcc level at high speed by inverter A1 and MOS transistor P6. As a result, the voltage levels of internal nodes INA1 to INA5 all become H level at about time T1, and MOS transistors P1 to P5 are all rendered non-conductive at about time T1. Thereby, the MOS transistors P1 to P1
When P5 is non-conductive, the current path flowing from power supply node 1 to output signal line 5 and output node 4 at high speed is cut off.

At time T2, when the input signal IN1 rises from the L level to the H level, the MOS transistor P
6 receives an H level signal at its gate electrode through internal wiring 7 and is rendered non-conductive, and internal node INA5 is disconnected from power supply node 1. When inverter A1 inverts input signal IN1 applied to input node 3a and transfers it to input node INA1, the potential level of input node INA1 drops to L level at time T3, and MOS transistor P1 is rendered conductive. Here, FIG. 1 (B)
At, inverter A1 is shown to have a significant delay time. The signal to this internal node INA1 is transmitted to internal node INA2 via resistor R1.
The resistance value of the resistor R1 and the internal nodes INA1 and I
The signal on the internal node INA1 is delayed for a predetermined time due to the wiring capacitance (parasitic capacitance) between the NA2 and the internal node INA.
2 is transmitted. That is, the potential of internal node INA2 decreases to the L level at time T4 after a lapse of a predetermined time from time T3, and MOS transistor P2 is rendered conductive. At time T4, output signal line 5 is charged by MOS transistors P1 and P2, and its charging current increases. Thereafter, resistors R2, R3 and R4 cause the potentials of internal nodes INA3, INA4 and INA5 to fall to the L level at times T5, T6 and T7, respectively, and MOS transistors P3, P4 and P5 are successively rendered conductive. As a result, the output signal line 5 and the output node 4 are charged by the charging current that increases in sequence, the potential thereof gradually rises, and the occurrence of ringing (occurrence of overshoot) at the output node 4 is reliably suppressed.

In the above structure, M for driving the output signal line
All of the OS transistors P1 to P5 are brought into a non-conducting state at a high speed when they are non-conducting, and the MOS transistors P1 to P5 are sequentially brought into a conducting state when they are in a conducting state, thereby suppressing the occurrence of ringing with low current consumption. It is possible to realize a semiconductor circuit that operates.

In the structure of FIG. 1A, MOS transistor P6 is arranged at internal node INA5 where the delay of the gate signal (the output signal of inverter A1 applied to the gate electrodes of MOS transistors P1 to P5) is the largest. are doing. However, a plurality of MOS transistors P6 may be arranged at appropriate internal node positions.

[Modification 1] FIG. 2 is a diagram showing an operation waveform diagram according to a first modification of the semiconductor circuit of the first embodiment of the present invention.

In FIG. 2A, the semiconductor circuit includes a plurality (five in this example) of n-channel MOS transistors N1 connected in parallel between the output signal line 5 and the ground node 2. To N5 and a plurality of MOS transistors N1 to N5 which are connected in series with each other (four in this example).
Of resistors R5 to R8, an inverter A2 that inverts the input signal IN2 applied to the input node 3b and transmits it to the internal node INB1, and is connected between the internal node INB5 and the ground node 2 and through the internal wiring 8. An n channel MOS transistor N6 electrically connecting internal node INB5 to ground node 2 in response to transmitted input signal IN2 is included. The internal wiring 8 is formed of a conductor having a relatively low resistance such as aluminum. Each gate electrode of the MOS transistors N1 to N5 has an internal node INB.
1 to INB5 are connected. The resistor R5 has an internal node I
The resistor R6 is connected between NB1 and INB2, the resistor R6 is connected between internal nodes INB2 and INB3, the resistor R7 is connected between the internal nodes INB3 and INB4, and the resistor R8 is connected between the internal nodes INB4 and INB5.
Connected between. The operation of the semiconductor circuit shown in FIG. 2A will now be described with reference to the operation waveform diagram of FIG. 2B.

When the input signal IN2 is at H level, M
OS transistor N6 receives an H level signal at its gate electrode through internal wiring 8 and becomes conductive. Inverter A2 inverts signal IN2 at input node 3b and transmits it to internal node INB1. Therefore, the internal node I
NB1 to INB5 are all at the L level, and MOS transistors N1 to N5 are all non-conductive.

At time T0, when input signal IN2 falls from H level to L level, the output signal of inverter A2 (potential of node INB1) rises from L level to H level at time T1 (where inverter A2 is It is assumed to have a significant delay time). On the other hand, the input signal IN2 is applied to the gate electrode of the MOS transistor N6 via the low resistance internal wiring 8, and the MOS transistor N6 is rendered non-conductive in response to the fall of the input signal IN2. First, in response to the rise of the potential of node INB1, MOS transistor N1 is rendered conductive, and output signal line 5 is discharged to the ground potential level. Then, due to the RC delay of the resistor R5 and the parasitic capacitance, the potential of the node INB2 falls from the L level to the H level at time T2, and the MOS transistor N2 is rendered conductive. As a result, output signal line 5 is discharged to the ground potential level by MOS transistors N1 and N2.

The resistors R6, R7 and R8 cause the potentials of the input nodes INB3, INB4 and INB5 to change from the L level to the H level at times T3, T4 and T5, respectively.
It rises to the level and MOS transistors N3, N4 and N5 are successively rendered conductive. As a result, the discharge current of the output signal line 5 sequentially increases, and the output signal line 5 is discharged. When the discharge current of the output signal line 5 is gradually increasing and the potential of the output node is reduced to a level at which ringing does not occur, the MOS transistors N1 to N5 are turned on, and the output signal line 5 has a large current driving force. Is discharged, and the occurrence of ringing (undershoot) at output node 4 is prevented.

At time T6, when the input signal IN2 rises from the L level to the H level, the low resistance internal wiring 8 causes M
The potential of the gate electrode of the OS transistor N6 rises to H level at a high speed, and the MOS transistor N6 becomes conductive. On the other hand, the inverter A2 causes the internal node INB to
1 becomes the L level. Internal nodes INB1 to INB5
Is driven to the L level of the ground potential level by the inverter A2 and the MOS transistor N6, these gate nodes INB1 to INB2 fall to the L level at approximately the same time T7, and the MOS transistors N1 to INB2 fall.
All N5 are made non-conductive at the same timing.

As described above, in the path for discharging the output node to the ground potential level, the n-channel MOS transistors are sequentially turned on when they are turned on, and when they are turned off, they are turned off at high speed at almost the same timing. By setting the state, it is possible to completely prevent the occurrence of undershoot and through current.

In the structure shown in FIG. 2A, MOS transistor N6 for driving an internal node is provided only for internal node INB5 having the longest delay time. A plurality of MOS transistors N6 may be provided in parallel at appropriate positions.

FIGS. 1 and 2 show a structure for individually suppressing the occurrence of overshoot and undershoot, respectively. These circuits can be independently applied to a circuit portion in which overshoot is a critical factor and a circuit portion in which ringing due to undershoot is a critical factor, depending on the application to which this semiconductor circuit is applied. .

[Modification 2] FIG. 3 shows a second modification of the first embodiment of the present invention. In FIG. 3A, the semiconductor circuit includes p-channel MOS transistors P1 to P5 connected in parallel between the power supply node 1 and the output signal line 5 and parallel connection between the ground node 2 and the output signal line 5. Channel MOS transistor N1 connected to
To N5 and resistors R1 to R5 connected between the gate electrodes of the MOS transistors P1 to P5 and connected in series with each other.
Resistors R5 to R connected between R4 and the gate electrodes of the MOS transistors N1 to N5 and connected in series with each other.
8, a p-channel MOS transistor P6 for supplying a current from the power supply node 1 to the internal node INA5 in response to the input signal IN applied to the input node 3, and the input node 3
In response to the input signal applied to the internal node INB5
Includes an n-channel MOS transistor N6 electrically connected to ground node 2, and inverters A1 and A2 inverting the input signal IN input to input node 3 and outputting the inverted signals to internal nodes INA1 and INB1, respectively.

The structure of the semiconductor circuit shown in FIG. 3A is equivalent to a combination of the semiconductor circuits shown in FIGS. 1A and 2A. The operation of the semiconductor circuit shown in FIG. 3A will be described with reference to the operation waveform diagram of FIG. 3B.

When the input signal IN is at H level, the MOS transistor P6 is non-conductive, and the MOS transistor N6 is in the non-conductive state.
Is in conduction. Internal nodes INA1 to INA5 and INB1 to INB5 are all at the L level. In this state, p-channel MOS transistors P1 to P
5 is a conductive state, n-channel MOS transistors N1 to N
5 is non-conductive, and output signal DOUT output from output signal line 5 and output node 4 is at H level.

When the input signal IN falls from the H level to the L level, as described with reference to FIGS. 1A and 1B, the internal nodes INA1 to INA5 become the H level at substantially the same timing, and p The channel MOS transistors P1 to P5 are turned off at almost the same timing. On the other hand, the internal nodes INB1 to INB5 are shown in FIG.
As described with reference to (A) and (B), the potential thereof sequentially rises to the H level. As a result, the period during which both the p-channel MOS transistor and the n-channel MOS transistor are in the conductive state is sufficiently shortened, and the shoot-through current flowing from power supply node 1 to ground node 2 is suppressed.
At this time, the output signal line 5 is also gently discharged to the ground potential level. Initially, one MOS transistor N1 discharges, and the output node 4 is discharged with a current that increases in sequence. Since the MOS transistors N2 to N5 are sequentially turned on, the output signal DOUT is discharged first slowly and then at high speed. At this time, the output signal DOUT is discharged at a high speed after the voltage level of the output node 4 is lowered to a level at which ringing does not occur, so that the output signal DOUT is discharged.
Undershoot does not occur.

When the input signal IN rises from the L level to the H level, the internal nodes INB1 to INB5 are changed from the H level to the L level at almost the same timing as described with reference to FIGS. MOS level
The transistors N1 to N5 are turned off at almost the same timing. On the other hand, p-channel MOS transistor P
As described with reference to FIGS. 1A and 1B, internal nodes INA1 to INA5 sequentially become conductive because the internal nodes INA1 to INA5 sequentially decrease from the H level to the L level. At first, the voltage level of the output signal DOUT gradually rises,
After that, the voltage level rises at a high speed. Since the output node 4 is charged at a high speed when the voltage level becomes sufficiently high, the occurrence of overshoot is surely suppressed.

By applying the configuration of the present invention to the charge circuit and the discharge circuit of the output signal line 5 and the output node 4, respectively, a stable output signal DOUT without overshoot and undershoot can be constructed. You can

As described above, according to the first embodiment of the present invention, a signal complementary to the signal applied to the gates of the output driving MOS transistors for driving the control electrodes of these MOS transistors is gated. Since the MOS transistor for receiving is added, the output drive MOS transistors are sequentially turned on when the output drive MOS transistors are turned on, and the output drive MOS transistors are not turned off at the same time when the output drive MOS transistors are turned off. Also, it is possible to generate a stable output signal with low current consumption.

In the first embodiment, the MOS
Bipolar transistors can be used instead of the transistors P1 to P5 and N1 to N5. P channel MOS when using a bipolar transistor
A PNP bipolar transistor is used instead of the transistor, and an NP is used instead of the n-channel MOS transistor.
N bipolar transistors are used.

[Embodiment 2] FIG. 4 is a diagram showing a main part of a structure of a semiconductor circuit according to a second embodiment of the present invention. FIG. 4A shows, as an example, a configuration in which output signal line 5 and output node 4 are driven by five p-channel MOS transistors P1 to P5.

In FIG. 4A, two inputs and one output are provided between the gate electrodes of the p-channel MOS transistors P1 to P5 connected in parallel between the power supply node 1 and the output signal line 5 which are connected to each other. Logic gates LG1 to LG4 are connected. These 2-input 1-output logic gates LG1 to LG
4 are connected in cascade. The gate electrodes of the MOS transistors P1 to P5 are connected to the internal nodes INA1 to INA5. The inverter A1 is connected to the internal node INA1.
Input signal IN1 applied to input node 3a is applied via. The logic gate LG1 has an internal node INA1.
Inverter A3 for inverting the signal potential of
It includes a 2-input NAND gate B1 which receives the output signal of 3 and the input signal IN1 via signal line 9. NAND gate B
The output signal of 1 is applied to the input node INA2.

The logic gate LG2 has an internal node INA2.
Inverter A4 for inverting the signal of FIG. 2 and a 2-input NAND for receiving the output signal of the inverter A4 and the signal on the signal line 9.
Includes gate B2. The output signal of NAND gate B2 is applied to input node INA3. The logic gate LG3 is
Inverter A5 that inverts the signal of internal node INA3
And a 2-input NAND gate B3 for receiving the output signal of inverter A5 and the signal on signal line 9. The output signal of NAND gate B3 is applied to input node INA4.
Logic gate LG4 includes an inverter A6 that inverts the signal of internal node INA4, and a 2-input NAND gate B4 that receives the output signal of inverter A6 and the signal on signal line 9. The gate delay of the inverter A1 is NAND
It is made substantially equal to the gate delay of each of the gates B1 to B4. Next, the operation will be described.

When the input signal IN1 is at H level, NAN
D gates B1 to B4 function as an inverter buffer. That is, the logic gates LG1 to LG4 act as a circuit including a two-stage inverter, and the internal nodes INA1 to INA1 to
INA5 is at L level. In this state, output signal line 5 is charged to the level of power supply potential Vcc.

When the input signal IN1 falls from the H level to the L level, the signal potential of the node INA1 rises to the H level by the inverter A1. This internal node INA
Due to the gate delay time of the inverter A1 for raising the potential level of 1, a predetermined time is delayed from the rise of the input signal IN1. On the other hand, in the logic gates LG1 to LG4,
A signal falling from H level to L level is transmitted to one input of NAND gates B1 to B4 through signal line 9.
In response to this, NAND gates B1 to B4 output an H level signal at their outputs. As described above, the gate delay of the inverter A1 and the NAND gates B1 to B
The gate delays required by 4 are equal. Therefore, all the internal nodes INA1 to INA5 have the same timing (time).
Rises to H level, and MOS transistors P1 to P5
All become non-conductive at almost the same timing.

When input signal IN1 rises from the L level to the H level, the potential of internal node INA1 falls from the H level to the L level. The potential change of the internal node INA1 occurs after the gate delay time of the inverter A1 has elapsed from the potential change of the input signal IN1.

When the potential of the signal line 9 becomes H level, NA
The ND gates B1 to B4 act as an inverter buffer, and each of the logic gates LG1 to LG4 functions as a buffer circuit including two stages of inverters. Internal node I
NA2, INA3, INA4, and INA5 sequentially decrease from the H level to the L level with a shift in the gate delay time of two stages included in each of the logic gates LG1 to LG4. In response to the fall of the potentials of internal nodes INA1 to INA5, MOS transistors P1 to P5 are successively rendered conductive, and output signal line 5 and output node 4 are sequentially charged to the level of power supply voltage Vcc. Therefore, when the output signal line 5 is charged, a rapid current change does not occur, the current change is gradual, the value of di / dt is small, and the occurrence of ringing (overshoot) at the output node can be sufficiently suppressed. . Also, the MOS transistor P
When the MOS transistors P1 to P5 are non-conducting, the MOS transistors P1 to P5 are brought into the non-conducting state at substantially the same timing, so that the consumption current (through current) can be surely suppressed.

[Modification 1] FIG. 5 shows a structure of a first modification of the second embodiment. In FIG. 5A, five n-channel MOS transistors N1 to N5 are provided.
Shows a circuit for discharging the output signal line 5 to the ground potential level.

In FIG. 5A, the semiconductor circuit has a logic gate LG5 connected between the gate electrodes of n-channel MOS transistors N1 to N5 and cascaded to each other.
~ LG8 and the input signal IN applied to the input node 3b
It includes an inverter A2 which inverts 2 and transmits it to the input node INB1. Gate electrodes of MOS transistors N1 to N5 are connected to internal nodes INB1 to INB5, respectively.

The logic gate LG5 has an internal node INB1.
Inverter A7 for inverting the signal of A2 and a 2-input NOR gate C1 receiving the output signal of inverter A7 and the signal applied to signal line 10 from internal node 3b. NO
The output signal of R gate C1 is applied to internal node INB2. Logic gate LG6 has an inverter A8 that inverts the signal of internal node INB2, and a 2-input NOR gate C that receives the output signal of inverter A8 and the signal of signal line 10.
2 inclusive. The output signal of the NOR gate C2 is the internal node I
Given to NB3.

The logic gate LG7 has an internal node INB3.
A9 for inverting the signal of the inverter A9, and a NOR gate C for receiving the output signal of the inverter A9 and the signal of the signal line 10.
Including 3. The output signal of the NOR gate C3 is an internal node I
It is given to NB4. Logic gate LG8 receives an inverter A10 that inverts the signal of internal node INB4, and an output signal of inverter A10 and a signal of signal line N.
It includes an OR gate C4. The output signal of NOR gate C4 is applied to internal node INB5. Inverters A2 and N
The OR gates C1 to C4 have the same gate delay. Next, referring to the operation waveform diagram shown in FIG.
The operation of the circuit shown in will be described.

When the input signal IN2 is at H level, the signal on the signal line 10 is at H level, and the NOR gates C1 to C4 are
Outputs an L level signal. In this state,
Internal nodes INB1 to INB5 are all at the L level, and MOS transistors N1 to N5 are all non-conductive.

When input signal IN2 falls from H level to L level, the potential of internal node INB1 rises from L level to H level after the lapse of the gate delay time of inverter A2. On the other hand, the signal line 10 has low resistance, and the change of the input signal IN2 is applied to one input of each of the NOR gates C1 to C4 at high speed. Therefore, in this state, NOR gates C1 to C4 all function as inverter buffers, and logic gates LG5 to LG8 are 2
It functions as a delay circuit composed of inverters in stages.

After the signal potential of internal node INB1 drops to H level, the gate delay of two stages of logic gate LG5 elapses, and then the potential of internal node INB2 rises from L level to H level. N2 is made conductive. Thereafter, the logic gate L
After the two-stage gate delay of G6 to LG8 has passed,
The potential of the internal nodes INB3 to INB5 changes from L level to H
Get up to the level. As a result, the MOS transistor N
3 to N5 are sequentially turned on. Since the output signal line 5 and the output node 4 are driven by the discharge current which increases successively, the current change rate is small and the occurrence of ringing (undershoot) at the output node 4 is suppressed.

When output signal IN2 rises from level to H level, the change in input signal IN2 is applied to NOR gates C1 to C4 via signal line 10. As a result, the NOR gates C1 to C4 function as an inverter buffer. Inverter A2 and NOR gates C1 to C4
The gate delays are almost equal. Therefore, the internal nodes INB1 to INB5 are all lowered from the H level to the L level at the same timing after one stage of gate delay has elapsed when the input signal IN2 changes. As a result, all the MOS transistors N1 to N5 are turned off at the same timing. Thereby, the generation of the through current can be completely suppressed, and the current consumption can be reduced.

[Modification 2] FIG. 6 shows a second modification of the second embodiment of the present invention. The semiconductor circuit shown in FIG. 6A is equivalent to the combination of the semiconductor circuits shown in FIGS. That is, the semiconductor circuit shown in FIG. 6A has p-channel MOS transistors P1 to P5 connected in parallel between output signal line 5 and power supply node 1.
And logic gates LG1 to LG4 connected between the gate electrodes of these MOS transistors P1 to P5 and cascaded to each other, and the input signal I of the input node 3 (3a).
An inverter A1 that inverts N and transmits it to the internal node INA1, and n-channel MOS transistors N1 to N5 connected in parallel with each other between the ground node 2 and the output signal line 5.
And a logic gate LG5 connected between the gate electrodes of these MOS transistors N1 to N5 and connected in cascade.
To LG8 and an inverter A2 for inverting the input signal IN applied to the input node 3 and transmitting the inverted signal to the internal node INB1.
including. In FIG. 6A, portions corresponding to those of the circuits shown in FIGS. 4A and 5A are designated by the same reference numerals. NA included in the logic gates LG1 to LG4
The input signal IN is applied to one input of the ND gates B1 to B4 via the signal line 10. Similarly, the logic gate LG
Input signal I is applied to one input of NOR gates C1 to C4 included in 5 to LG8 via signal line 10. Next, operation of the semiconductor circuit shown in FIG. 6A is described with reference to an operation waveform diagram of FIG. 6B.

When input signal IN is at H level, internal nodes INA1 to INA5 and INB1 to INB5 are all at L level, and output signal line 5 is charged via MOS transistors P1 to P5 and is at H level. When input signal IN falls from H level to L level, this signal change is applied to one input of NAND gates B1 to B4 included in logic gates LG1 to LG4 via signal line 9. As a result, internal nodes INA1 to INA5 rise from L level to H level at the same timing (gate delay of one stage), and MOS transistors P1 to P5 are all rendered non-conductive at the same timing.

On the other hand, the NOR gates C1 to C4 are connected to the signal line 10
This L-level signal is given via to function as an inverter. As a result, the logic gate LG functions as a delay element including a two-stage inverter. Therefore, the potentials of the input nodes INB1 to INB5 sequentially rise with a gate delay of two stages after the potential of the input node INB1 rises. That is, the MOS transistor N1
.About.N5 are sequentially turned on, and output signal line 5 is discharged to the ground potential level. The output signal DOUT is discharged with an increasing current. At this time, the current change rate is small, so
Undershoot does not occur in the output signal DOUT. Further, when the MOS transistors N1 to N5 are conducting, all the MOS transistors P1 to P5 are in the non-conducting state, and no through current is generated.

When the input signal IN rises from the L level to the H level, the logic gates LG5 to LG are supplied via the signal line 10.
A signal of H level is applied to one input of NOR gates C1 to C4 included in 8. Accordingly, NOR gates C1 to
The output signal of C4 drops to L level. As a result, the potentials of the internal nodes INB1 to INB5 all decrease from the H level to the L level with a gate delay of one stage with respect to the input signal IN applied to the input node 3, and the MOS transistors N1 to N5 all have the same timing. Is turned off.

On the other hand, in logic gates LG1 to LG4, H level signals are applied to NAND gates B1 to B4 via signal line 9, and NAND gates B1 to B4 function as inverter buffers. That is, logic gates LG1 to LG4 operate as a delay element composed of a two-stage inverter, and sequentially transmit the signal applied to input node INA1 with the gate delay of the next stage. M
The OS transistors P1 to P5 are sequentially turned on to supply a current to the output signal line 5. The current change rate of the output signal line 5 is small, the overshoot of the output signal DOUT does not occur, and the stable output signal DOUT can be obtained. Also,
At this time, the MOS transistors P1 to P5 are sequentially turned on, so that the MOS transistors N1 to N5 are turned on.
Are all in a non-conducting state, the possibility of a through current occurring is small, and the current consumption is reduced.

In the second embodiment shown in FIGS. 4 to 6, a bipolar transistor can be used instead of the MOS transistor.

[Third Embodiment] FIG. 7 is a diagram showing the structure and operation of a semiconductor circuit according to a third embodiment of the present invention. In FIG. 7A, the semiconductor circuit is the power supply node 1
And 5 p connected in parallel with each other between the output signal line 5 and
It includes channel MOS transistors P1 to P5. MOS
Gate electrodes of the transistors P1 to P5 are connected to internal nodes INA1 to INA5, respectively.

Between the gate electrodes of the MOS transistors P1 to P5, that is, between the internal nodes INA1 to INA5,
Logic gates LG1 to LG4 are provided respectively. Input signal IN1 applied to internal input node 3a is transmitted to internal node INA1 via two-stage inverters A11 and A1.

The logic gate LG1 has an internal node INA1.
It includes a 2-input NOR gate C11 for receiving the above signal and a signal on signal line 9, and an inverter A3 for receiving the output signal of NOR gate C11. The output signal of inverter A3 is transmitted to internal node INA2. Logic gate L2 receives a signal on internal node INA2 and a signal on signal line 9 2
It includes an input NOR gate C12 and an inverter A4 receiving an output signal of the NOR gate C12. The output signal of inverter A4 is applied to internal node INA3.

The logic gate LG3 has an internal node INA3.
It includes a 2-input NOR gate C13 that receives the above signal and a signal on signal line 9, and an inverter A5 that receives the output signal of NOR gate C13. The output signal of inverter A5 is transmitted to internal node INA4. The logic gate LG4 is
Two-input NOR gate C14 for receiving the signal on internal node INA4 and the signal on signal line 9, and NOR gate C14
Inverter A6 for receiving the output signal of The output signal of inverter A6 is transmitted to internal node INA5.

When the delay time of NOR gates C11 to C14 is equal to the delay time of inverter A11 and the delay time of inverters A3 to A6 is equal to the delay time of inverter A1, logic gate LG1
~ LG4 provides the same two-stage gate delay as the delay element formed of inverters A11 and A1. Next, Fig. 7
The operation of the semiconductor circuit shown in FIG. 7A will be described with reference to the operation waveforms shown in FIG.

When the input signal IN1 is at H level, the delay element including the inverters A11 and A1 outputs the signal at H level to the internal node INA1. The signal on the signal line 9 is also at the H level. When the signal on signal line 9 is at H level, the output signals of NOR gates C11 to C14 are all at L level, and at the same time, the output signals of inverters A3 to A6 are also at H level. That is, the internal node INA
1 to INA5 are all at H level, and MOS transistors P1 to P5 are all non-conductive.

When the input signal IN1 falls from the H level to the L level, the internal node INA1 changes to the inverter A11.
And, the potential decreases from the H level to the L level with a slight delay according to the two-stage gate delay of A1. On the other hand, the signal on signal line 9 drops from H level to L level at substantially the same timing as input signal IN1 applied to input node 3a. NOR gates C11 to C14 function as inverters, and logic gates LG1 to LG4 are 2
It functions as a delay circuit composed of inverters in stages.
As a result, the signals applied to internal node INA1 are delayed by logic gates LG1 to LG4 for a predetermined time (two stages of gate delay) and sequentially transmitted to internal nodes INA2 to INA5. MOS transistors P1 to P5 are successively rendered conductive to charge output signal line 5 and output node 4 to the level of power supply voltage Vcc. The current change rate di / dt of the output signal line 5 is small, and the occurrence of overshoot of the output signal DOUT output from the output node 4 is suppressed.

When the input signal IN1 rises from the L level to the H level, the signal on the signal line 9 also changes from the L level to the H level.
Get up to the level. NOR gates C11 to C14 included in logic gates LG1 to LG4 all output L level signals. Input signal IN1 is transmitted to internal node INA1 via two-stage inverters A11 and A1. That is, the input signal I applied to the input node 3a
When N1 rises from the L level to the H level, the internal nodes INA1 to INA5 rise from the L level to the H level at the same timing (with a gate delay of two stages of inverters), and the MOS transistors P1 to P5 all at the same timing. It is made non-conductive. M when not conducting
Since all the OS transistors P1 to P5 are turned off at the same timing, current consumption (through current) is suppressed.

[Modification 1] FIG. 8 shows a structure and an operation of a first modification of the third embodiment of the present invention.
Also in FIG. 8, in order to drive output signal line 5 and output node 4, five n-channel MOS transistors N
1 to N5 are provided in parallel with each other between output signal line 5 and ground node 2. Gate electrodes of the MOS transistors N1 to N5 are connected to the internal nodes INB1 to INB5.

The input node 3b is connected to the internal node INB1.
The input signal IN2 applied to the two-stage inverter A12
And transmitted via A2. Internal nodes INB1 ~
Logic gates LG5 to LG8 are connected in series between INB5. Logic gate LG5 is a 2-input NAND gate B for receiving the signal of internal node INB1 and the signal of signal line 10.
1 and an inverter A2 receiving the output signal of NAND gate B1. The output signal of inverter A2 is applied to internal node INB2. Logic gate LG6 receives NA of the signal on internal node INB2 and the signal on signal line 10.
It includes an ND gate B2 and an inverter A8 receiving an output signal of the NAND gate B2. The output signal of inverter A8 is applied to internal node INB3. Logic gate LG7
Includes a NAND gate B3 receiving a signal on internal node INB3 and a signal on signal line 10, and an inverter A9 receiving an output signal from NAND gate B3. Inverter A
The output signal of 9 is applied to internal node INB4.

The logic gate LG8 is connected to the internal node INB4.
NAND gate B4 which receives the signal on the signal line 10 and the signal on signal line 10 and an inverter A10 which receives the output signal of NAND gate B4. The output signal of inverter A10 is applied to internal node INB5. NAND gates B1 to B
4 has a delay time of inverter A12 or A2
Is equal to the delay time of. Inverter A2 and each of inverters A7 to A10 have the same delay time. Thus, when an H level signal is applied to signal line 10, the delay elements included in inverters A12 and A2 and the delay times of logic gates LG5 to LG8 become equal (two-stage gate delay). Next, FIG.
This will be described with reference to FIG. 8B which is an operation waveform diagram showing the operation of the semiconductor circuit shown in FIG.

When the input signal IN2 is at H level, the internal nodes INB1 to INB5 are all at H level, and MO
S transistors N1 to N5 are all in a conductive state. When the input signal IN2 falls from H level to L level, the signal on the signal line 10 accordingly falls from H level to L level. As a result, the output signals of NAND gates B1 to B4 included in logic gates LG5 to LG8 rise to the H level, and accordingly the output signals of inverters A7 to A10 are set to the L level.
Fall to the level. Input signal IN2 is transmitted to internal node INB1 via two-stage inverters A12 and A2. Logic gates LG5-LG8 lower the potential of corresponding internal nodes INB2-INB5 from the H level to the L level for the signal on signal line 10 with a two-stage gate delay (NAND gate and inverter). That is, internal nodes INB2-INB5 attain L level at the same time, and MOS transistors N1-N5 are rendered non-conductive.

When the input signal IN2 rises from the L level to the H level, the internal node INB1 is driven by the inverter A12.
After the lapse of the delay time of A2 and A2, the potential rises from the L level to the H level. The signal on the signal line 10 becomes H level according to the input signal IN2, and the NAND gates B1 to B4 function as inverters. Therefore, in this state, logic gates LG5 to LG8 are equivalent to a delay element composed of a two-stage inverter. The signal applied to internal node INB1 is sequentially transmitted to internal nodes INB2 to INB5 with a delay of two stages of gate delay, and MOS transistors N1 to N5 are sequentially turned on. The rate of change of the discharge current of output signal line 5 is reduced, and therefore the occurrence of undershoot of output signal DOUT from output node 4 is suppressed.

Further, when the MOS transistors N1 to N5 are non-conductive, they are all rendered non-conductive at the same timing, so that current consumption (through current) is reduced.

[Modification 2] FIG. 9 shows a structure and an operation of a second modification of the third embodiment of the present invention.
In FIG. 9A, the semiconductor circuit has a p-channel M connected in parallel between the output signal line 5 and the power supply node 1.
OS transistors P1 to P5 and an n-channel MOS transistor connected in parallel between the ground node 2 and the output signal line 5.
Transistors N1 to N5 and MOS transistors P1 to
Logic gates LG1 to LG4 connected between the gate electrodes of P5 and cascaded with each other, logic gates LG5 to LG8 connected between the gate electrodes of MOS transistors N1 to N5 and cascaded with each other, and an input node Three
Inverters A11 and A1 of two stages transmitting an input signal IN applied to internal node INA1 and inverters A12 and A2 of a next stage transmitting an input signal applied to input node 3 to input node INB1. The input signal I is also applied to the logic gates LG1 to LG4 via the signal line 9.
N is transmitted, and the input signal IN is also transmitted to the logic gates LG5 to LG8 via the signal line 10. This Figure 9
The structure of the semiconductor circuit shown in FIG. 7A is equivalent to a combination of the circuits shown in FIGS. 7A and 8A,
Corresponding parts are given the same reference numbers.

Each of logic gates LG1 to LG4 receives the signal on signal line 9 at one input and MO corresponding to the other input.
Two-input NOR gates C1 to C4 that receive the signal of the gate electrode (internal node) of the S transistor, and an inverter (A3 to C3) that receives the output signal of the corresponding NOR gate and supplies it to the gate electrode (next stage node) of the two-stage transistor. A6) is included. Each of the logic gates LG5 to LG8 has a signal line 10
NAND gates (B1 to B4) that receive the signal above and the signal of the gate electrode (internal node) of the transistor in the previous stage
And an inverter (A7 to A10) that inverts the output signal of the corresponding NAND gate and supplies the inverted signal to the gate electrode (internal node) of the transistor at the next stage. Next, the operation of the semiconductor circuit shown in FIG. 9A is an operation waveform diagram thereof, which is shown in FIG. 9B.
Will be described with reference to.

When the input signal IN is at H level, the internal nodes INA1 to INA5 and INB1 to INB5 are set to H level, the MOS transistors P1 to P5 are non-conductive, the MOS transistors N1 to N5 are conductive, and the output The signal DOUT is at the low level of the ground potential level. When the input signal IN falls from the H level to the L level, the internal nodes INB1 to INB5 fall to the L level at the same timing with two stages of gate delays, and the MOS
All the transistors N1 to N5 are turned off at the same timing. On the other hand, the internal nodes INA1 to INA5
Is sequentially lowered to the L level due to the delay time of the logic gates LG1 to LG4, and the MOS transistors P1 to P5
Are sequentially turned on. At this time, when the MOS transistors P1 to P5 are conducting, the MOS transistor N has already been
1 to N5 are in a non-conducting state, and a through current flowing from power supply node 1 to ground node 2 does not occur. The output signal line 5, that is, the output signal DOUT is the MOS transistor P.
1 to P5 drive to the power supply voltage Vcc level.
Since the MOS transistors P1 to P5 are sequentially turned on, the rate of current change in the output signal line 5 is small, and no overshoot occurs in the output signal DOUT.

When the input signal IN rises from the L level to the H level, the logic gates LG1 to LG4 change the potentials of the internal nodes INA2 to INA5 to the H level by the signals on the output line 9 with two stages of gate delays. And raise. The potential of internal node INA1 rises from L level to H level by inverters A11 and A1. That is, the potentials of all internal nodes INA1 to INA5 rise from L level to H level at the same timing, and MOS transistors P1 to P5 are all rendered non-conductive at the same timing. On the other hand, the logic gate L
In G5 to LG8, the NAND gates B1 to B4 are connected to the signal line 1
Since it functions as an inverter by the signal of 0, it functions as a delay circuit. As a result, the internal nodes INB1 to INB1
The potential of INB5 sequentially rises from the L level to the H level, and MOS transistors N1 to N5 are successively turned on. The output signal line 5 is discharged by the MOS transistor N1.
~ N5, at which time the rate of current change is small and no undershoot occurs in the output signal DOUT.

When the MOS transistors N1 to N5 are turned on, all the MOS transistors P1 to P5 are already turned off at the same timing, and the power supply node 1
No through current from the ground node 2 to the ground node 2.

As described above, when the output signal line 5 is charged or discharged, the charging current or the discharging current is sequentially increased, and when the output signal DOUT becomes a level at which ringing does not occur, the charging or discharging current is changed. To increase the output signal DO without delaying the response of the output signal and without causing ringing.
A UT can be generated. Also, p-channel MOS
The period in which both the transistors P1 to P5 and the n-channel MOS transistors N1 to N5 are in a conductive state is extremely short, generation of a through current can be sufficiently suppressed, and a circuit with low current consumption can be realized.

[Embodiment 4] FIG. 10 is a diagram showing the structure of a fourth embodiment of the present invention. The structure shown in FIG. 10 is most effective when used in combination with the first embodiment shown in FIGS. FIG. 10 shows a structure of a circuit portion for driving output signal DOUT to the level of power supply voltage Vcc. A similar configuration is used for the circuit portion that drives output signal DOUT to the ground potential GND level. Figure 10
The plane pattern layout is shown in FIG.
The element connections are shown in simplified form in FIG. 10, and an electrical equivalent circuit is shown in FIG.

In FIG. 10A, active regions (high-concentration impurity regions) are formed separately from each other in field active region F. In FIG. 10A, high-concentration impurity regions S forming source regions and high-concentration impurity regions D forming drain regions are alternately arranged. Adjacent 2
Region between two impurity regions S and D (channel region)
Are provided with gate electrode wirings Ga1 to Ga5. These gate electrode wirings Ga1 to Ga5 form the gate electrodes of the MOS transistors P1 to P5. Impurity regions D and S are shared by two adjacent transistors. This reduces the element occupation area. The gate electrode wirings Ga1 to Ga5 are interconnected by wiring layers Gb1 to Gb4 having a higher resistance value, for example, made of polysilicon. The wiring layers Gb1 to Gb4 alternately connect adjacent one ends and the other ends of the gate electrode wirings Ga1 to Ga5. That is, the wiring layers Gb1 to Gb4
Are alternately arranged on one side of the field active region F and the other side opposite to this one side. Gate electrode wiring Ga1
To Ga5 are wiring layers Gb1 through the contact hole CHg.
To Gb4.

Low resistance conductive layers 20 and 22 made of, for example, aluminum are formed on the upper layers of these gate electrode wirings Ga1 to Ga5 and wiring layers Gb1 to Gb4. Power supply voltage Vcc is applied to conductive layer 20, and conductive layer 22 transmits output signal DOUT. This conductive layer 2
0 is formed on the conductive layer 22. The conductive layer 20 is connected to the impurity layer S forming the source region via the contact hole CHs, and the conductive layer 22 is connected to the impurity region D forming the drain region via the contact hole CHd. The input signal IN1 is applied to the gate electrode wiring Ga1.

In FIG. 10B, p channel MOS
The transistor P1 is composed of a source impurity region S1, a gate electrode wiring G1 and a drain impurity region D1. The MOS transistor P2 has a drain impurity region D
1, a gate electrode wiring G2 and a source impurity region S2. The MOS transistor P3 includes a source impurity region S2, a gate electrode wiring G3 and a drain impurity region D2. MOS transistor P4
Is composed of a drain impurity region D2, a gate electrode wiring G4, and a source impurity region S3. The MOS transistor P5 includes a source impurity region S3, a gate electrode wiring G5 and a drain impurity region D3. Power supply voltage Vcc is applied to source impurity regions S1 to S3 through conductive layer 20. Drain impurity region D
1 to D3 are connected to the conductive layer 22. Gate electrode wiring G
Each of 1 to G5 has a resistance value RR1. Wiring layer Gb in which gate electrode wirings G1 and G2 have resistance value RR2
Interconnected by 1. Gate electrode wirings G2 and G
3 are connected by a wiring layer Gb2 having a resistance value RR2. The gate electrode wirings G3 and G4 are connected by a wiring layer Gb3 having a resistance value RR2, and the gate electrode wiring G4
And G5 are connected by a wiring layer Gb4 having a resistance value RR2.

Resistance value RR of gate electrodes G1 to G5
The difference between 1 and the resistance value RR2 of the wiring layers Gb1 to Gb4 is realized by, for example, adjusting the amount of impurities implanted into polysilicon, which is a wiring material.

In FIG. 10C, MOS transistor P1 receives input signal IN1 at its gate electrode G1. Gate electrode G of MOS transistors P1 and P2
Resistors having resistance values RR1 and RR2 are connected in series between 1 and G2. Resistors having resistance values RR1 and RR2 are connected in series between the gate electrodes of the two MOS transistors. By appropriately adjusting the values of these resistance values RR2, the MOS transistor P2
The delay time of the signal given to P5 can be set to a desired value. At this time, the gate electrode layers Ga1 to Ga
Even if 5 has a low resistance for high-speed operation, by sufficiently increasing the resistance value RR2 of the wiring layers Gb1 to Gb4, it is possible to cope with the low resistance of the gate electrode layer without increasing the layout area. Therefore, the MOS transistors P1 to P5 can be rendered conductive with a desired delay time. In addition, the gate electrode layer Ga1
Even when the resistance of Ga5 to Ga5 is not lowered, the wiring layers Gb1 to Gb4 have the same function even when the noise (ringing) is suppressed by increasing the time lag during which the MOS transistors P1 to P5 are turned on. Resistance value RR2
By appropriately increasing, the desired delay time can be easily realized without increasing the area.

The wiring layers Gb1 to G5 whose resistance values can be changed for the MOS transistors P1 to P5, respectively.
Since b4 is connected, the signal propagation delay time for each of the MOS transistors P2 to P5 can be efficiently set appropriately.

The structure of the gate electrode wiring shown in FIG. 10 may be applied to the conventional output circuit shown in FIG.

As described above, according to the fourth embodiment, since the gate electrode layers are interconnected by the wiring layers having a resistance value higher than that of the gate electrode layers, the area is increased. A desired signal propagation delay time can be set for each MOS transistor without causing

[0112]

According to the first aspect of the present invention, the control electrodes of a plurality of transistors connected in parallel with each other are interconnected with a control electrode line having a significant resistance value, and the control electrode line and the reference potential are further connected. Since a transistor whose control electrode receives a signal complementary to the signal applied to the control electrodes of the plurality of transistor elements is provided between the node and the node, the second transistor is controlled when the plurality of transistors are turned off. When the reference potential is transmitted to the electrode line and the plurality of transistors are turned off at the same time and the plurality of transistors are turned on, the control electrode line is sequentially turned on with a significant resistance value, resulting in low power consumption. Thus, it is possible to generate an output signal in which noise is sufficiently suppressed.

According to the second aspect of the invention, the first control electrode line connected in parallel between the first reference node and the output signal line and having the respective control electrodes having a significant resistance value is connected to each other. A plurality of first transistors connected to each other and a signal provided between the first reference electrode node and the first control electrode line and complementary to a signal applied to the control electrode of the first transistor are control electrodes. The second transistor applied to the second reference potential and the second reference potential and the node output signal line are connected in parallel to each other and the respective control electrodes are interconnected by the second control electrode line having a significant resistance value. Multiple thirds
Connected between the second control electrode line and the second reference potential node, and a signal complementary to the signal applied to the control electrode of the third transistor is applied to the control electrode. Since the semiconductor circuit is configured with the transistor, when the first transistor is conductive, all the third transistor elements are simultaneously rendered non-conductive and the first transistors are sequentially rendered conductive, while the first transistor is non-conductive. At this time, the plurality of first transistors are simultaneously turned off and the third transistors are sequentially turned on, so that an output signal in which a through current does not occur and noise is suppressed is generated. be able to.

According to the third aspect of the invention, the logic gates connected in series are arranged between the control electrodes of the transistors connected in parallel to each other, and the plurality of logic gates are connected to the delay element array when the plurality of transistors are conductive. The output signals of the logic gates are changed at the same timing when the plurality of transistors are non-conducting.When the plurality of transistors are non-conducting, the plurality of transistors are not conducting at the same timing. Can be brought into a state, current consumption can be reduced, and since the plurality of transistors are sequentially turned on when the plurality of transistors are turned on, an output signal in which noise is suppressed can be generated. .

According to the invention of claim 4, the first delay element for inverting the input signal is provided, and each of the logic gates is provided with the signal applied to the second input for receiving the output signal of the preceding gate. A second inverter that inverts the same, and the same gate delay as the first inverter, and receives the output signal of this second inverter and the input signal applied to the input node,
Since the input element has the gate element that outputs the signal of the second logic level when the input signal has the first logic level, the logic gate and the delay element have the same gate delay and all the plurality of transistor elements are turned off at the same timing. It can be in a state.

According to the invention of claim 5, the delay element is formed of a buffer delay element, and each of the logic gates receives the output signal of the gate of the preceding stage at its second input and inputs it to its first input. A gate element that receives a signal and outputs a signal of a first logic level when the input signal has a second logic level;
Since it is composed of an inverter that inverts the output signal of the gate element, the buffer delay element and the gate delay of the logic gate can be made equal, and all the plurality of transistors are turned off when the plurality of MOS transistors are made non-conductive. The non-conduction state can be set at the same timing.

According to the invention of claim 6, the control electrodes of a plurality of transistors connected in parallel to each other are interconnected by a wiring layer having a resistance value higher than that of the electrode layer forming the control electrodes. Therefore, the control electrode line having a desired signal propagation delay can be formed with a small occupied area.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration and an operation of a semiconductor circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration and an operation of a first modification of the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration and an operation of a second modification of the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration and operation waveforms of a semiconductor circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration and operation waveforms of a first modification of the second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration and operation waveforms of a second modification of the second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration and operation waveforms of a semiconductor circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration and operation waveforms of a first modification of the third embodiment of the present invention.

FIG. 9 is a diagram showing a configuration and operation waveforms of a second modification of the third embodiment of the present invention.

FIG. 10 is a diagram showing a layout and a configuration of wirings and resistors of a semiconductor circuit according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional output circuit.

12 is a signal waveform diagram representing an operation of the output circuit shown in FIG.

FIG. 13 is a diagram for explaining a problem of a conventional output circuit.

14 is a waveform chart showing an operation of the output circuit shown in FIG.

FIG. 15 is a diagram showing a layout of gate electrode wirings of a conventional semiconductor circuit and a connection mode thereof.

[Explanation of symbols]

1 power supply node, 2 ground node, 3, 3a, 3b input node, 4 output node, 5 output signal line, 7 signal wiring, 8 signal wiring, 9 signal wiring, 10 signal wiring,
P1 to P6 p-channel MOS transistors, N1 to N
6 n-channel MOS transistors, A1, A2, A1
1, A12 inverter, R1 to R4 resistance, LG1 to L
G8 logic gate, B1 to B4 NAND gate, C1
-C4, C11-C14 NOR gates, A3-A10
Inverter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 17/687

Claims (6)

[Claims] 1. A semiconductor circuit for driving an output node to a logic level corresponding to the input signal according to an input signal, the reference signal supplying a first reference potential and an output signal coupled to the output node. A plurality of first transistors connected in parallel with each other and conducting when a signal of a first logic level is applied to its control electrode; A control electrode line interconnecting the control electrodes of the first transistor; and a control electrode line, which is provided between the reference node and the control electrode line and which conducts when a signal of the first logic level is applied to the control electrode. Pair of second transistors, and a pair of signals complementary to each other are generated from the input signals, and one and the other signals of the pair of complementary signals are generated from the plurality of first transistors and the second signal. And means for applying to the control electrode of the transistor, the semiconductor circuit. 2. A first reference node supplying a first potential and an output signal line coupled to the output node are connected in parallel to each other, and a signal of a first logic level is applied to each control electrode. A first control electrode line having a significant resistance and interconnecting control electrodes of the plurality of first transistors; a first reference node; At least one second transistor which is connected between the control electrode line and the control electrode line and which conducts when the signal of the first logic level is applied to the control electrode, and a second transistor having a logic complementary to the first potential. Second receiving a potential of 2
A plurality of third transistors connected in parallel with each other between the reference node and the output signal line and conducting when a signal of the second logic level is applied to each control electrode; and a plurality of the third transistors. A second control electrode line having a significant resistance value, which complementarily connects the control electrode of the transistor, is connected between the second reference node and the second control electrode line, and the control electrode is connected to the second control electrode line. At least one fourth transistor which conducts when a signal of logic level 2 is applied, and a pair of signals of logic complementary to each other are generated in response to the input signal to generate the pair of first and second transistors. One signal of the pair of complementary logic signals is applied to the control electrode line, and the second signal is applied to the control electrode line.
And a control circuit for applying the other signal of the pair of signals of the complementary logic to the control electrode of the fourth transistor. 3. A delay element for delaying a signal of an input node for a predetermined time and outputting the delayed signal to an internal input node, an output signal line connected to the output node, and a reference node receiving a reference voltage and the output signal line. A plurality of transistors connected in parallel to each other and conducting when a signal of a first logic level is applied to its control electrode, and a plurality of logic gates respectively connected between the control electrodes of the plurality of transistors. Each of the plurality of logic gates has a first input connected to the input node, a second input connected to a control electrode of a previous-stage transistor, a control electrode of a next-stage transistor, and a logic of the next stage. An output connected to the second input of the gate, and each of the logic gates has a potential of the internal input node when the potential of the internal input node is at the first logic level. Are sequentially transmitted with a delay of a predetermined time, and when the signal of the internal input node is at the second logic level, each of the logic gates has a delay time substantially the same as the delay time given by the delay element. A semiconductor circuit that transmits a signal at an input node to a control electrode of a corresponding transistor. 4. The delay element is a negative delay element that inverts and delays the signal applied to the input node, and each of the plurality of logic gates inverts the signal of the second input. Second designated delay element and the same gate delay as the first designated delay element, and receives the output signal of the second negative delay element and the signal of the input node, and receives the signal of the second input. 4. The semiconductor circuit according to claim 3, further comprising a gate element that outputs a signal of the second logic level to its output regardless of the logic of the signal of the first input when is the first logic level. 5. The delay element comprises a buffer delay element that delays an input signal applied to the input node for a predetermined time, and each of the plurality of logic gates has the input applied to the first input. A gate element that outputs a signal of the first logic level regardless of the logic level of the signal applied to the second input when the signal of the node has the second logic level; and an inversion of the output signal of the gate element. 4. The semiconductor circuit according to claim 3, further comprising a delaying negative delay element, wherein the sum of the gate delays of the gate element and the designated delay element is substantially the same as the gate delay of the buffer delay element. 6. A plurality of transistors connected in parallel are provided between a reference node supplying a reference potential and an output signal line connected to the output node, each of the plurality of transistors being connected to the reference node. One conduction node and the other conduction node connected to the output signal line, and a control electrode forming a wiring layer having a first resistance value between one end and the other end. Second control electrodes of the plurality of transistors are arranged in parallel with each other, and the second resistance larger than the first resistance value alternately interconnects adjacent one end and adjacent other end of the control electrodes of the plurality of transistors. A wiring having a value, and a signal corresponding to an input signal is transmitted on the wiring.