JPH0691462B2 - Analog counter circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an analog counter circuit.

[Conventional technology]

Conventionally, this type of counter circuit uses an asynchronous digital counter, and the output terminal of the flip-flop in the previous stage is connected to the clock terminal of the flip-flop in the next stage. The up-counter and the down-counter can be configured by the flip-flop to be used, and the output of the flip-flop is inverted and the output is connected to the reset terminal to specify the period at which the pulse is output. I was able to.

[Problems to be solved by the invention]

The above-described conventional digital counter is configured by connecting flip-flops, and counts by latching the rising edge and the falling edge of the pulse. If the maximum number of pulses that can be counted is m and the number of flip-flops is N, the maximum number of pulses that can be counted is given by the equation (1).

m = 2 ⁿ (1) Therefore, there is a drawback that the number of circuit elements increases when the number of counts is large. Also, when changing the number to be counted, the circuit configuration is such that the output terminal of each flip-flop is connected to the selector circuit and the number to be counted by the selector circuit is selected, so that the number to be counted can be easily changed with a small number of circuit elements. There is also the drawback that you cannot do it.

An object of the present invention is to provide a circuit suitable for a case where a counter is configured with a small number of circuit elements and a number to be counted is easily changed.

Therefore, the present invention is configured by connecting the voltage conversion circuit and the voltage comparator to the digital counter configured by the conventional flip-flop connection described above, and the counting can be configured by a small number of circuit elements. The difference is that the number can be easily changed.

[Means for solving problems]

One end of the first capacitor is connected to the source and gate of the first MOS transistor, and the other end of the first capacitor is one of the first and second clocks having a phase difference of 180 degrees from each other. A plurality of partial circuits in which the drain of the second MOS transistor is connected to the source and the gate of the first MOS transistor and the source of the second MOS transistor is connected to the second power supply line. And the first circuit constituting the partial circuit
The source gate of the MOS transistor is M of the previous partial circuit.
Connected to the drain of the OS transistor, the first MOS
The drain of the transistor is connected to the source and the gate of the MOS transistor in the next stage, and the first and second clock signals are alternately supplied to the cascaded partial circuits according to the order, and the source and the gate are connected. Connecting at least one third voltage source to a predetermined voltage source
The drain of the MOS transistor is the first of the first partial circuits
Connected to the source and gate of the MOS transistor of the first stage, and the drain of the first MOS transistor of the partial circuit in the last stage is connected to one of the second capacitor, the input of the voltage comparator, and the fourth
The other of the second capacitor and the source of the fourth MOS transistor are connected to the drain of the MOS transistor, respectively, and the output of the voltage comparator is logically ORed with the output terminal. The output of the OR circuit, which is connected to the input of the circuit and receives the input signal from the input terminal and the output of the voltage comparator, is output from the gate of the fourth MOS transistor and the second of the plurality of partial circuits. It is configured by connecting to the gate of the MOS transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of the partial circuit of FIG.

The circuit of the present invention comprises a booster circuit section and a voltage comparison section, and the booster circuit section has one capacitor and two N channels.
It has a cascade connection circuit of 6 stages of partial circuits composed of MOS transistors.

As shown in FIG. 2, one end of the capacitor C1 is a 1N channel MOS.
The source and the gate of the transistor M1 are connected, and the other end of the capacitor C1 is connected to either one of the clocks φ1 and φ2 having a phase difference of 180 degrees. Also, N
The drain of the channel MOS transistor M7 is an N-channel MOS
A partial circuit is formed in which the source and gate of the transistor M1 are connected, and the source of the N-channel MOS transistor M7 is connected to the ground terminal GND.

The source and gate of the N-channel MOS transistor M1 forming the partial circuit of FIG.
N-channel MOS connected to the drain of MOS transistor
The drain of the transistor M1 is connected to the source and gate of the MOS transistor of the next stage, and regarding the connection order of the clocks φ1 and φ2, the odd number of partial circuits is connected to the clock φ1 and the even number is connected to the clock φ2. N channel
The gate of the MOS transistor M7 is a feedback terminal RTN connected to the output terminal of this analog counter circuit. As shown in Fig. 1, the N-channel of the first partial circuit and the MOS transistor M
The source and gate of 1 are connected to the drain of the N-channel MOS transistor M0, and the source and gate of the N-channel MOS transistor M0 are connected to the power supply terminal V1. The drain of the N-channel MOS transistor M6 in the circuit of the last stage is connected to one of the capacitors C7 and the input of the voltage comparator A and the drain of the N-channel MOS transistor M13, respectively, and the other of the capacitor C7 and the N-channel MOS transistor is connected. The source of M13 is connected to the ground terminal GND. The output of the voltage comparator A is connected to the output OUT of the analog counter circuit, the output of the voltage comparator A and the input terminal E of the analog counter circuit are connected to the input side of the OR circuit D,
The output terminal of the OR circuit D is an N-channel MOS transistor M
It is connected to the gates of 7 to M13.

Next, the operation of the first embodiment will be described.

The counter operates when the input terminal is set to low, and stops when the input terminal is set to high. When the input terminal is set low and the counter is kept on, the clock φ1 changes from high level to low level, and the clock φ2 changes from low level to high level, the MOS transistor M1 of the first stage partial circuit
The potential of the connection point between the source and the gate of is increased, the potential of the drain is increased, the N-channel MOS transistor M1 becomes non-conductive, the N-channel MOS transistor M0 becomes conductive, and the charge is N-channel. The capacitor C1 is charged from the power supply V1 via the MOS transistor M0. Next, when the clock φ1 changes from the low level to the high level and the clock φ2 changes from the high level to the low level, the N-channel MOS transistors M0 and M2 become non-conductive and the N-channel M
OS transistor M1 is conducting, the capacitor C ₂ is a capacitor
Charged by the charge on C1. By repeating this operation, charges are transferred one after another and finally charge the capacitor C7,
The positive input charge of voltage comparator A rises.

By operating the clocks φ1 and φ2 in this manner, electric charges are sucked from the semiconductor substrate on which the power supply and the circuit are formed to generate a high voltage in the voltage comparator A, and the voltage of the positive input terminal of the voltage comparator A is , When the voltage reaches the reference voltage reduction V2 (which is applied to the negative input terminal of the voltage comparator A) or more, the voltage comparator A operates and the output of the voltage comparator A changes from low level to high level. As a result, the N-channel MOS transistors M7 to M13 are rendered conductive, the charges charged in the capacitors C1 to C7 are discharged, the output terminal of the voltage comparator A changes from high level to low level, and clocks can be counted.

Although the N-channel MOS transistor has been described above, a P-channel MOS transistor can be used by reversing the polarities of the power supply and the input / output.

FIG. 3 is a circuit diagram showing the configuration of the second embodiment of the present invention.

In the second embodiment, the drains of the N-channel MOS transistors M14 and M15 are connected to the drain of the first-stage potential setting transistor M0, the source of the N-channel MOS transistor M14 is connected to the power supply terminal V3, and the source of the 1-N-channel MOS transistor M15. Is connected to the third power supply terminal V4 and is an N-channel MOS
The gates of the transistors M0, M14, 1M15 are connected to the output of the selector B, and there is a select terminal C of the selector B, which is different from the first embodiment.

In this circuit, one of N-channel MOS transistors M0, M14, and M15 is selected by the input of the select terminal C. Then, the voltage dropped from the voltage of any one of the power supply terminals V1, V3, and V4 by the threshold voltage of the N-channel MOS transistor is the N-channel MOS.
By adding to the source and gate of transistor M1,
There is an advantage that the number of pulses to be counted can be easily changed.

〔The invention's effect〕

As described above, the present invention has an effect that a large number of pulses can be counted with a small number of circuit elements by using the present analog counter circuit, and can be easily changed by changing the reference voltage of the voltage comparator. The effect is that it can be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the partial circuit of FIG. 1, and FIG. 3 is a configuration of the second embodiment of the present invention. FIG. V1 ・ V3 ・ V4 …… Power supply terminal, V2 …… Reference voltage source, φ ・ φ ₁
・ Φ ₂ …… Clock terminal, C _{1 to} C ₇ …… Capacitor, M 0 to
M15: N-channel MOS transistor, A: voltage comparator, B: selector, C: select terminal, D: logical sum circuit, E: input terminal, RTN: feedback terminal.

Claims (1)

[Claims] 1. A first and second clock having one end of a first capacitor connected to a source and a gate of a first MOS transistor, and the other end of the first capacitor having a phase difference of 180 degrees from each other. The drain of the second MOS transistor is connected to the source and the gate of the first MOS transistor, and the drain of the second MOS transistor is connected to the source and the gate of the second MOS transistor.
The source of the transistor is composed of a plurality of partial circuits connected to the second power supply line, and the source and gate of the first MOS transistor constituting the partial circuit are connected to the drain of the MOS transistor of the preceding partial circuit. Connected,
The drain of the first MOS transistor is connected to the source and gate of the MOS transistor of the next stage, and the first and second clock signals are alternately supplied to the cascaded partial circuits in the order. , The drain of at least one third MOS transistor whose source and gate are connected to a predetermined voltage source is connected to the source and gate of the first MOS transistor of the first-stage partial circuit, and the drain of the last stage is connected. The drain of the first MOS transistor of the partial circuit is connected to one of the second capacitors and the input of the voltage comparator and the drain of the fourth MOS transistor, respectively, and the other of the second capacitor and the fourth MO transistor are connected.
The source of the S transistor is connected to the second power supply line, the output of the voltage comparator is connected to the output terminal and the input of the logical sum circuit, and the input signal from the input end and the output of the voltage comparator are connected. The output of the OR circuit, which receives the
An analog counter circuit connected to the gates of the MOS transistors and the gates of the second MOS transistors of the plurality of partial circuits.