JPH0329411A - Delay circuit - Google Patents

Abstract

PURPOSE:To suppress the relative change in a delay time and to facilitate the design of the delay circuit with a desired delay time by using different inverter circuits deciding the delay times of the delay time respectively. CONSTITUTION:An inverter circuit deciding a delay time TPLH and an inverter circuit deciding a delay time TPHL are different from each other. Thus, an output terminal of the inverter circuit of the 3rd stage not participating in the delay time TPLH is quickly discharged at the leading of an input signal and an output terminal of the inverter circuit of the 1st stage not participating in the delay time TPHL is quickly charged at the trailing of the input signal. Thus, the inverters of the 1st and 3rd stages are charged from or discharged to the reference voltage. Thus, even when the power voltage, the temperature or the threshold voltage of a transistor(TR) is changed, the delay times TPLH, TPHL are not relatively changed and the delay times TPLH, TPHL are set individually with the different inverters, then the delay time is designed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit constructed from a CMOS semiconductor integrated circuit.

[Conventional technology] This type of delay circuit is conventionally shown in Fig. 3. circuit is known.

As shown in FIG. 3, P channel type MOS transistors P. and an N-channel MOS transistor N. constitutes an input stage CMOS inverter circuit Ill.

This CMOS inverter circuit I. (2) inverts the signal input via the input terminal IN and outputs it to the output section A;

A capacitor C1 is connected between the output section A of this CMOS inverter circuit III and the ground GND. The capacitance of this capacitor CI and the P-channel type MOS transistor P1■ and the N-channel type MOS transistor N1■
The delay time of the output signal of the CMOS inverter circuit III is determined by the time constant determined by the on-resistance of the CMOS inverter circuit III. Also, the power supply V. A P channel type MOS transistor P14 and an N channel type MOS transistor N14 connected in series between D and the ground GND are output stage CMOS transistors.
Inverter circuit engineer. ■Constitutes. In this CMOS inverter circuit engineer, does the potential of output part A reach the predetermined threshold voltage? At times, the output is inverted and output via the output terminal OUT. Furthermore, a P-channel MOS transistor P1 is connected between the power supply VDD and the output section A.
and P3 are connected in series. Further, N-channel type MOS transistors Nl2 and Nl3 are connected in series between the output section A and the ground GND. And M
OS transistors PI■ and N1. The gate electrodes of the MOS transistor P13 are commonly connected to the input terminal IN, and the gate electrodes of the MOS transistor P13
The gate electrodes of Nl3 and Nl3 are commonly connected to the output terminal OUT.

In the conventional delay circuit configured in this way, the input terminal I
When the input signal input through N changes to the ground potential, capacitor C1 is charged through P-channel type MOS transistor Pll. As a result, the potential of the output section A increases. When the potential of the output section A reaches the threshold voltage of the N-channel MOS transistor NI4, the CM
The output of the OS inverter circuit I1■ is inverted to the ground level. This time delay is the falling delay time (TPIIL)
). Is the output of CMOS inverter circuit I12 grounded? When the bell is reached, the P channel type MOS transistor Pl
3 turns on. Transistor P1. Since is already in the on state, from this moment on, the capacitor CI is rapidly charged via the P channel type MOS transistors P+++P1 and PI:l, and the power source A becomes the heavy source V. Rise to 0 level.

On the other hand, the input signal input via the input y:tli-F-IN is at the power supply potential V. When it changes to 0, the N-channel MOS transistor N1 is turned on and the capacitor CI
The stored charge is discharged through the MOS transistor Nll. As a result, the potential of the output section A decreases. When the potential of the output section A reaches the threshold voltage of the P-channel MOS transistor pt4, the output of the CMOS inverter circuit I12 is inverted to the power supply level. This time delay becomes the delay time at rise (Tpz.u). CMOS
Inverter circuit I. When the output (2) reaches the power supply voltage level, the N-channel MOS transistor NIG is turned on. Transistor N. Since ■ is already in the on state, from this moment on, the N-channel MOS transistor NIIIN+
(2) The charge in the capacitor C1 is rapidly discharged via N1G, and the output section A falls to the ground level.

In this way, the delay time of the delay circuit is determined by the delay time of the P-channel MOS transistor P. Alternatively, it is determined by the time constant of the on-resistance of the N-channel MOS transistor N+t and the capacitance of the capacitor Cj.

[Problems to be Solved by the Invention] However, in the conventional delay circuit described above, when a change occurs in the power supply voltage, temperature, or threshold voltage, insufficient charging or discharging of the capacitor C1 occurs, causing the input signal to change. Delay time TPLII and delay time T
There is a problem that there is a relatively large change in the output waveform, which causes a change in the duty ratio of the output waveform with respect to the input waveform. Also, the delay time T PIIL I T
Since pto is determined by one inverter circuit, there is a problem in that it is difficult to design a delay circuit with a desired delay time.

The present invention has been made in view of such problems, and includes:
There is little relative change in delay time at rise and fall,
It is an object of the present invention to provide a delay circuit that can easily set a desired delay time.

[Means for Solving the Problems] The delay circuit according to the present invention includes four inverter circuits each having a complementary pair of P-channel MOS transistors and N-channel MOS transistors connected between a positive power source and a negative power source.
The inverter circuit of the first stage has a smaller on-resistance than the N-channel MOS transistor, and the inverter circuit of the third stage has a smaller on-resistance than that of the N-channel MOS transistor. Channel type MOS
The L transistor is characterized in that it has a smaller on-resistance than its P-channel MOS transistor.

[Operations] In the present invention, when the input signal becomes high level, the N-channel MOS transistor of the first stage inverter circuit is turned on. Does this first-stage N-channel MOS transistor have low driving capability? Therefore, it takes a relatively long time for the output signal to fall. This time becomes the delay time TPL■ at the time of rising. Therefore, TpL■ is determined by the driving ability of this first stage N-channel type MOS transistor. This signal is sequentially inverted by the second to fourth stage inverter circuits and output via the output terminal OUT.

Furthermore, when the input signal becomes low level, the low level signal is input to the third stage inverter circuit. Then, the P-channel type MOS transistor of the third stage inverter circuit is turned on. P of this third stage inverter circuit
Since the channel type MOS transistor has a small driving capability, it takes a relatively long time for its output signal to rise. This time becomes the delay time TPIIL at the time of falling. Therefore, TPIIL is determined by the driving ability of this third stage P-channel type MOS transistor. This signal is inverted by the fourth stage inverter circuit and output via the output terminal OUT.

In this way, in the present invention, the delay time? pLI1
The inverter circuit that determines the delay time TPIIL is different from the inverter circuit that determines the delay time TPIIL. Therefore, when the input signal rises, the delay time T'pt. The output terminal of the third stage inverter circuit that is not involved in ■ is immediately discharged,
When the input signal falls, the output terminal of the first stage inverter circuit, which is not involved in the delay time TIIIL, is quickly charged. Therefore, since both the first and third stage inverter circuits discharge and charge from the reference potential, even if the power supply voltage, temperature, or threshold voltage of the transistor changes, the delay times TPLN and T'pnz ．． does not change relatively. Also, the delay time TPLI
Since I and TPIIL can be set independently using different inverters, it is easy to design the delay time.

Embodiment Next, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a delay circuit according to an embodiment of the present invention.

As shown in FIG. 1, this delay circuit includes four CMOS inverter circuits I. ,I. +I3+14 are connected in cascade.

CMOS inverter circuit I. thru I4 are respective power supplies V. D
P-channel type M connected to Aiura pair between and ground GND
OS transistor P1 and N-channel MOS transistor N. 1P channel type MOS transistor P2 and N
Channel type MOS transistor N2, P channel type M
It is composed of an OS transistor P3 and an N-channel type MOS transistor N, as well as a P-channel type MOS transistor P4 and an N-channel type MOS transistor N4.

Furthermore, the P-channel MOS transistor P+ has a smaller on-resistance, that is, is set to have a higher driving capability, than the N-channel MOS transistor Nl. N-channel type MOS transistor N3 is P-channel type MOS
Compared to the transistor P3, its on-resistance is set to be lower, that is, its driving ability is set higher. P channel type MO
S transistor P2l P4 and N channel type MOS transistor N. ．． The driving capabilities of N4 are set to be approximately equal.

In the Ivi-configured delay circuit as described above, when the input signal input to the input terminal IN becomes high level, the first stage CMOS inverter circuit 1. N-channel MO
S transistor Nl is turned on.

Since the N-channel type MOS transistor N1 has a small driving capability, it takes a relatively long time for its output signal to fall.

However, when the output level of the CMOS inverter circuit I, exceeds the input threshold level of the next-stage CMOS inverter circuit I2, the next-stage CMOS inverter circuit I2. I3 and I4 rapidly change their output states.

Therefore, the delay time TPLI1 at the time of rising is determined by the time of output change of the first stage CMOS inverter circuit I.

Also, when the input signal becomes low level, the first stage and second stage
The CMOS inverter circuits I, I2 of the stages rapidly change their output states, and the CMOS inverter circuits I, I2 of the third stage rapidly change their output states.
No. 3 P-channel type MOS transistor P3 is turned on.

However, since the P-channel MOSI transistor P3 has a small driving capability, it takes a relatively long time for its output signal to rise. Therefore, the delay time TPIIL is determined by the third stage CMOS inverter circuit I3.

FIG. 2 is a graph showing the results of simulating the operation of the delay circuit according to the embodiment of the present invention, and the measurement points are the CMOS inverter circuit r. ,I. ．． These are the nodes a+ b+ C which are the output terminals of II, the input terminal IN, and the output terminal OUT. The horizontal axis shows elapsed time, and the vertical axis shows voltage. As is clear from Fig. 2, when the input signal changes from low level to high level, the delay time TPLI
1 is the voltage at node a, that is, the CMOS inverter circuit I,
It is determined by Furthermore, when the input signal changes from high level to low level, the delay time T PHL is determined by the voltage at node C, that is, by the CMOS inverter circuit I3.

? In addition, since charging to node a and discharging from node C occur rapidly, node alC is always at the reference potential (V
oD, GND).

Therefore, even if the power supply voltage, temperature, or transistor threshold voltage fluctuates, the delay time T PLII
There is little relative change in I T pIIL, and fluctuations in the duty ratio can be prevented.

Furthermore, the delay times T PLII and T PIIL are respectively C
Since the delay time can be set individually using the MOS inverter circuits Il and I3, it becomes easy to design the delay time. Also, CMO
S inverter circuit I2 or CMOS inverter circuit I
It is also possible to determine both the delay times T PLII I T pot using 4.

[Effects of the Invention] As explained above, according to the present invention, the inverter circuits that determine the delay times TPL and TPIIL of the delay circuit are different. This makes it easy to design a delay circuit with a desired delay time.

Also, even if there is a variation in the power supply voltage, temperature, or transistor threshold voltage during the delay time, the delay may be delayed. T between
to and Tpot. Since it is possible to suppress relative changes in the duty ratio, fluctuations in the duty ratio can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a delay circuit according to an embodiment of the present invention;
FIG. 2 is a graph diagram showing simulation results of the delay circuit, and FIG. 3 is a circuit diagram showing a conventional delay circuit. If, I2, I. + I41 1+s+ I+■
; CMOS inverter circuit, P+t P21 P
31 P41P +1+ P 121 P Il
l P14: P-channel MOS transistor, N r + N2 r N3 + N4 + N l
l+N1■+N,3+N14 1 N-channel MOS transistor, C1; capacitor, IN: input terminal, OUT: output terminal

Claims (1)

[Claims] (1) Four stages of inverter circuits each having a P-channel MOS transistor and an N-channel MOS transistor connected in complementary pairs are connected in cascade between a positive power source and a negative power source, and the first stage inverter circuit is as follows: The P-channel MOS transistor has a smaller on-resistance than the N-channel MOS transistor, and in the third stage inverter circuit, the N-channel MOS transistor has a smaller on-resistance than the P-channel MOS transistor. A delay circuit characterized by having an on-resistance.