JPS6248119A - Semiconductor output circuit - Google Patents

Abstract

PURPOSE:To decrease practically sufficiently the transition speed in transiting a signal level of a tri-state output TS by using an equivalent impedance of a MOS transistor (TR) as a voltage division impedance required for setting a signal level of the three value output TS to an intermediate value. CONSTITUTION:In sending the intermediate voltage VM as the three value output TS, MOS TRs W11, W12 are turned off and switching MOS TRs W15, W16 are turned on. The MOS TRs W13, W14 act like diodes and the charging or discharge current to/from a capacitor C2 is supplied through the equivalent impedance. Since the impedance is high when viewed from a connection midpoint PO to the MOS TRs W11, W12 in this sate, the MOS TRs W11, W12 do not give adverse effect onto the charging through the MOS TRs W13, W14. Thus, the three value output TS in its voltage level is transited from a VDD to the VM or from a VSS to the VM so as to shorten sufficiently the required transition time.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to semiconductor output circuits, and in particular to MO3LS r
(metal oxtde semiconductor
or large scale integrated
This is suitable for application to a ternary output circuit in a circuit.

B. Summary of the Invention The present invention provides a semiconductor output circuit that sends out a three-value output having a high voltage level, a low voltage level, and an intermediate voltage level. When the second output transistor is turned off, the third and fourth output transistors are turned on via the switch circuit.
By outputting an intermediate voltage level as a divided voltage of the equivalent impedance of the output transistor,
The transition time when the signal level of the ternary output changes can be significantly shortened.

C. Conventional technology As a semiconductor output circuit conventionally used in MO3LSI, it is possible to send out outputs at three voltage levels.
The value output circuit is, for example, an area comparison type P L L (ph
ase 1ocked 1oop ) circuit. A conventional three-value output circuit has a logic "1" level of voltage VDD, a logic "0" level of voltage V33, and a third circuit that generates a three-value output having voltage ■A as an intermediate level. The structure shown in the figure is used.

In FIG. 3, 1 indicates the PLL circuit as a whole, and the clock signal SCK oscillated in the clock oscillation circuit 2
It operates to lock the phase of the reference signal REF (FIG. 4(B)) to the rising phase of the reference signal REF (FIG. 4(A)) which is intermittently inputted from the outside.

The reference signal REF is applied to two stages of D flip-flop circuits 3 and 4 which are connected in series. The front-stage flip-flop circuit 3 receives the reference signal REF at its D input terminal, and sends the Q output to the D input terminal of the rear-stage flip-flop circuit 4.

The reference signal REF and the Q output of the flip-flop circuit 3 are given to the first exclusive OR circuit 5, and its output EXI (FIG. 4(E)) is supplied to the 3
It is supplied to the value output circuit 8 as a B input. Furthermore, the Q outputs of the flip-flop circuits 3 and 4 are connected to the second exclusive circuit.
The output EX2 (FIG. 4(F)) is supplied as the A input of the ternary output circuit 8.

The 3-value output TS (FIG. 4(G)) of the 3'-value output circuit 8 is integrated in the low-pass filter 9 and sent as a control voltage output COT to the clock oscillation circuit 2.

In the configuration shown in FIG. 3, the output EXI of the exclusive OR circuit 5 is connected to the D input of the flip-flop circuit 3, that is, the reference signal REF (the fourth
The period from when Q output Q1 rises until the Q output Q1 rises is at the logic "1" level, and as a result represents the phase difference between the reference signal REF and the clock signal SCK.

On the other hand, the output EX2 of the exclusive OR circuit 6
(Fig. 4(F)) is the Q of the flip-flop circuit 3.
After the output Ql (41st ffl (C)) rises, the Q output Q2 (4th
(D)) becomes a logic rlJ until it rises, thereby representing one period of the clock signal SCK.

The ternary output circuit 8 outputs the outputs EX1 and EX2 according to the change in the logic level of the outputs EXI and EX2.
1” and “0”, it rises to logic “1” level (that is, voltage VDD) and outputs EXI and EX
2 falls to logic "0" level (i.e. voltage v, 3) when logic "0" and "1", outputs EXI and EX2
When is logic "0" and "0", it operates to maintain the intermediate voltage level ■9. Therefore, as shown in FIG. 4, if the clock signal SCK is not phase-locked to the reference signal REF, the signal level of the ternary output TS is logic "0".
(i.e. voltage V.) compared to the logic level "
1'' (that is, the voltage V DD) becomes narrower. Therefore, the signal level of the control IJt pressure output COT obtained by integrating this in the low-pass filter 9 becomes a value lower than the intermediate voltage level vI4. At this time, the clock oscillation circuit 2 changes and controls the oscillation frequency so as to increase the signal level of the control voltage output COT.

As a result, the phase of clock signal SCK is controlled to lock with the phase of reference signal REF. As a result, the PLL circuit 1 performs a phase locking operation in which the phase of the clock signal SCK is locked to the phase of the intermittently arriving reference signal REF.

In the area comparison type PLL circuit 1 having such a configuration, the configuration shown in FIG. 5 has conventionally been used as the ternary output circuit 8. That is, the ternary output circuit 8 includes a MOS transistor (hereinafter referred to as PMO3) Wl having a P channel.
and an N-channel MOS transistor (hereinafter referred to as NM
W2 (referred to as O3) are connected in series with each other, the drain of transistor W1 is connected to a voltage source VDD at a high voltage level, and the source of transistor W2 is connected to a voltage source VSS at a low voltage level. A B input obtained by inverting the logic level of the output EX1 of the exclusive OR circuit 5 in an inverter 7 is applied to the gate of the transistor W1, and an A input, which is the output EX2 of the exclusive OR circuit 6, is applied to the gate of the transistor W2. Given.

A capacitor C whose one end is grounded is connected at the midpoint between the source of the transistor W1 and the drain of the transistor W2.
When I is connected and transistor W1 turns on, capacitor C1 is charged by voltage source ■DD, and conversely, when transistor W2 turns on, capacitor C1 is charged.
The charging voltage is discharged to a lower voltage RVss.

In addition to this configuration, the non-ground end of the capacitor C1 is connected to the midpoint of series resistors R1 and R2 connected in series between the power supplies VDD and VS2, and the transistor W
1 and W2 are in the off state, the series resistors R1 and R
2 is applied to charge the capacitor C1, thus providing a logic "1" voltage V on the capacitor C1. and a state in which the intermediate voltage (18) of the voltage VSS of logic "0" is maintained is obtained.

Note that at this time, the impedance when looking at the transistors W1 and W2 from the capacitor C1 side is in a high impedance state.

The voltage at the non-ground side end of capacitor C1 is the three-value output TS
Sent as .

In the configuration of FIG. 5, as shown in FIG.
In other words, the signal level of the inverted output of EXI is logic "0"
, and when the A input (i.e. EX2) is logic "0", transistor W1 consisting of PMO3 is on and NMO
Transistor W2 consisting of 3 is controlled to an off state, thereby causing capacitor C1 to reach a high voltage level ■. . A charged state is obtained, and this is sent out as a ternary output TS.

Similarly, the B input is logic "1" and the A input is logic ro.
'', transistors W1 and W2 are both turned off, so that capacitor C1 is charged to the divided voltage of resistors R1 and R2 (ie, intermediate voltage V, 4), and this is sent out as ternary output TS.

Furthermore, when the B input is logic "1" and the A input is logic "1", the transistor W2 made of NMO3 turns on, and the capacitor C1 is discharged to a low voltage VSS, which is sent out as a ternary output TS. be done.

Thus, according to the configuration shown in FIG. 5, by controlling the transistors W1 and W2 on and off by the outputs EXI and EX2 of the exclusive OR circuits 5 and 6 (FIG. 3), the voltage VDD of logic "1" level and Logic "0"
A ternary output TS consisting of the level voltage Vs3 and intermediate voltages V and 4 can be obtained.

D Problems to be Solved by the Invention However, according to the configuration shown in FIG. 5, the voltage dividing resistors R1 and R2 are connected to the capacitor CI in order to obtain the intermediate value voltage VM, which causes the following disadvantages. arise.

In other words, if the resistance values of voltage dividing resistors R1 and R2 are not selected to be sufficiently large, when transistor W1 or W2 is turned on, as shown by curve 2 in FIG.
Because the values of R1 and R2 are small, a non-negligible current flows through these resistors.
There is a problem in that the charging voltage of the capacitor C1 decreases to a voltage determined by the resistance value of the capacitor C1 and the equivalent resistance value of the turned-on transistor W1 or W2. If the voltage value of the logic "1" level or the logic rOJ level decreases in this way, the operation of the subsequent stage circuit receiving the ternary output TS will become unstable.

Therefore, from this point of view, it is considered that the resistance values of the voltage dividing resistors R1 and R2 should be as large as possible, but in this way, the charging voltage of the capacitor C1 changes from the logic rlJ level or the logic rOJ level to the intermediate voltage ■9 level. When transitioning to , the transition time increases, and as shown by 1 on the curve in FIG. 6, the voltage ■. I or V. voltage v from
1. When transitioning to 1, the waveform of the ternary output TS becomes large.

If you try to obtain the control voltage output COT for the clock oscillation circuit (Fig. 3) using the 3-value output TS that has been rounded in this way, the waveform rounding will affect the control voltage output COT as an error, so the phase will be affected. This results in deterioration of lock accuracy.

The present invention has been made in consideration of the above points, and is intended to propose a ternary output circuit that can effectively solve the problems of the conventional configuration shown in FIG.

E Means for Solving the Problem In order to solve this problem, the present invention provides a first output transistor Wll which sends out an output level signal of a high voltage level VDD, and a first output transistor Wll which sends out an output level signal of a low voltage level VSS. a second output transistor W12,
The third and fourth output transistors W send out the signal level of the intermediate voltage vH between the high voltage VOO and the low voltage VSS as a divided voltage of equivalent impedance during ON operation.
13 and W14, and when the first and second output transistors Wll and W12 are turned off, a high voltage VDD and a low voltage V are applied to the third and fourth output transistors W13 and W14 through the switch circuits W15 and W2B.
. By supplying this, a level signal of intermediate voltage V4 is sent out from the third and fourth output transistors W13 and W14.

When the F-action first output transistor Wll or the second output transistor W12 is turned on, the high voltage level VDD
An output level signal of VSS is delivered through the output transistor Wll, or an output level signal of a lower voltage level VSS is delivered through the second output transistor W12.

On the other hand, when both the first and second output transistors Wll and W12 are in an off state, the level signal of the intermediate voltage Vi is transmitted to the third and fourth output transistors W13 and W14 through the switch circuits W15 and W2B. By supplying high voltage v0 and low voltage VSS to
The intermediate voltage VM is divided by the ratio of the equivalent impedance of the output transistors W13 and W14, and this is the third voltage.
and is sent out from the fourth output transistors W13 and W14.

In this way, when a ternary bell signal is output, the impedance when looking at other output transistors from the output terminal becomes high impedance when each level signal is sent, so that the predetermined level can be maintained without interfering with each other. An output level signal may be sent.

Therefore, it is possible to effectively avoid the problem that the configuration for sending the level signal of the intermediate voltage A affects the transition of the output level signal, which is the case in the conventional case, and thus it is easy to create a semiconductor output circuit with a fast transition speed. can be realized.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

As shown in FIG. 1 with the same reference numerals assigned to parts corresponding to those in FIG.
A capacitor C2 is connected to the connection midpoint PO of the capacitor C2, and the charging voltage of the capacitor C2 is sent out as a ternary output TS.

At the connection midpoint PO between the source of the MOS transistor Wll and the drain of the MOS transistor W12, there are diode-connected MOS transistors W13 and W1, respectively.
4 is connected. MOS transistor W13 is PM
M, whose gate and source are commonly connected to the connection midpoint PO, and whose drain is PMO3.
It is connected to a voltage source (2) at a high voltage level through the OS transistor W15. Also MOS) transistor W1
The gates and sources of 4 are commonly connected to the connection midpoint PO
A voltage source VSS at a low voltage level is connected to the voltage source VSS through a MOS transistor W16 whose drain is an NMOS.
It is connected to the.

Mo3) Transistors W15 and W2O each constitute a switch circuit, and the gate of transistor W15 has an NA
The output of the ND circuit NAND 1 is directly connected to the transistor W15.
and is inverted by an inverter IN2 and supplied to the transistor W16.

The NAND circuit NAND1 receives the B input as a first input, and the A input as a second input through the inverter INI.

Here, the logic levels of the A input and the B input are selected so as to generate the ternary output TS by the same combination of logic levels as described above with respect to FIG. Thus, when the B input is logic "1" and the A input is logic "0", the output of the NAND circuit NAND1 becomes logic "0", thereby turning on both MOS transistors W15 and W2O. On the other hand, under other conditions,
When the output of the NAND circuit NAND 1 becomes logic "1", both MO5I transistors W15 and W2O are turned off.

A input and B input are each Mo3) transistor W1
2 and the gate of Wll, thus turning on the MOS transistor Wll when the B input is logic "0" and the A input is logic "0", and the MOS transistor Wll is turned on when the B input is logic "1" and the A input is logic "1". ” when Mo3) transistor W12
Only turn on to operate.

In the configuration of FIG. 1, in the operation and mode in which the level of the ternary output TS is set to a high voltage level v0 in the same manner as in the case of FIG. "become. At this time, Mo formed by PMO3
The S transistor Wll turns on and the capacitor C2 is charged with the voltage vno, and this charged voltage is sent out as a three-value output TS.

From this mode of operation, the A and B inputs switch to logic "0" and "1", respectively, when entering the mode of operation in which the intermediate voltage v,4 is subsequently delivered.

At this time, Mo3) transistors Wll and W12 are both turned off, and the capacitor C is connected through these transistors.
2 becomes unable to be charged or discharged. However, at this time, since the output of the NAND circuit NAND1 becomes logic "0", the M
OS transistors W15 and W2O turn on, and Mo
3) Voltage source V! through transistor W15. +11 voltage is supplied to the drain of MOS transistor W13, and at the same time voltage source v5. voltage is Mo3) transistor W16
MO5I is supplied to the drain of transistor W14 through MO5I.

In this mode of operation, capacitor C2 has a second
As shown in Figure (A), a charging path for capacitor C2 is formed from voltage source vDD through MOS transistors W15 and W13, and a discharging path for capacitor C2 is formed from voltage source VSS through MOS transistors W16 and W14. . By the way, the Mo3) transistors W13 and W14 are diode-connected, so that a current flows between the drain and the source with predetermined equivalent impedances R11 and R12, respectively.

Therefore, as shown in FIG. 2(B), for capacitor C2, a series circuit of equivalent resistances R11 and R12 of MOS transistors W13 and W14 is connected to voltage sources VOO and v,
3 and connect capacitor C2 to the midpoint of this connection, an equivalent circuit will be constructed. As a result, capacitor C2 will have a voltage of
. , and VSS to a voltage obtained by dividing the voltage.

Following this mode of operation, the ternary output TS is at voltage level V
In the SS mode of operation, the B and A inputs are logic '1' and rlJ, respectively, thus NMo
Only the MOS transistor W12 consisting of 3 is turned on. At this time, capacitor C2 is charged by voltage source VSS through transistor W12, and this voltage is sent out as ternary output TS.

According to the configuration shown in FIG. 1, the ternary output TS is set to the voltage level VI
When using ID or VSS, MOS transistor W
ll or W12 is turned on. At this time, the switching MOS transistors W15 and W16 connected to the drains of the MOS transistors W13 and W14 are in an OFF operation, so that the transistors W13 and W14 are turned off.
14 becomes a state of high impedance when viewed from the connection midpoint Po side, and thereby becomes a state in which it does not affect the charging operation from the MOS transistors Wll and WL2 to the capacitor C2.

On the other hand, when sending out the intermediate voltage ■8 as the ternary output TS, the MOS transistors Wll and W12 are turned off, and the switching MOS transistor W1
5 and W16 are turned on. At this time, MO3I-transistors W13 and W14 function as diodes and supply charging or discharging current to capacitor C2 through their equivalent impedance. However, in this state, from the connection midpoint PO to the MOS) transistors Wll and W
12 is in a high impedance state, so that MO3I transistors Wll and W12 can be prevented from adversely affecting the charging operation through such MOS transistors W13 and W14.

Therefore, the equivalent impedances R11 and R12 of the MOS transistors W13 and W14 can be suppressed to a low value as necessary, so that the 3(L! output TS changes the voltage level from VD+ to v, as described above with reference to FIG. 1
The required transition time can be sufficiently shortened when transitioning from VSS to (4) or from VSS to (4).

In the above description, the switch circuit for the MOS transistors W-13 and W14 is configured to include the MOS transistors W15 and W16, the NAND circuit NAND 1, the inverter IN2, etc., but other configurations may be used.

Effects of the Invention As described above, according to the present invention, the equivalent impedance of a MOS transistor is used as the voltage dividing impedance necessary to set the signal level of the ternary output TS to an intermediate value. It is possible to easily obtain a semiconductor output circuit in which the transition speed when changing the signal level of the ternary output TS can be shortened sufficiently for practical use.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of a semiconductor output circuit according to the present invention, and FIG. 2 is a connection diagram showing an equivalent circuit during its operation.
FIG. 3 is a block diagram showing an area comparison type PLL circuit,
FIG. 4 is a signal waveform diagram showing the signals of each part, FIG. 5 is a connection diagram showing a conventional three-value output circuit, and FIG. 6 is a signal waveform diagram for explaining its operation. 1...PLL circuit, 2...Clock oscillation circuit, 3.4...D flip-flop circuit,
5.6... Exclusive OR circuit, 8...
...Three-value output circuit, 9...Low pass filter. A picture of a boar, d1, a figure of 4, a, w'n, etc.

Claims (1)

[Claims] A first output transistor that sends out an output level signal at a high voltage level, a second output transistor that sends out an output level signal at a low voltage level, and an intermediate voltage between the high voltage and the low voltage. and third and fourth output transistors that send out a level signal of the level signal as a divided voltage of equivalent impedance during ON operation, and when the first and second output transistors are OFF operation, the level signal is transmitted through the switch circuit. A semiconductor output characterized in that the level signal of the intermediate voltage is sent from the third and fourth output transistors by supplying the high voltage and the low voltage to the third and fourth output transistors. circuit.