JP3339428B2 - Dynamic frequency divider with reset function and dynamic frequency divider with set function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic frequency divider with a reset function and a dynamic frequency divider with a set function.

[0002]

2. Description of the Related Art As a conventional frequency divider, FIG.
1 shows a dynamic transfer gate frequency divider disclosed in Japanese Patent Publication No. 114856.

The dynamic transfer gate frequency divider as the prior art 1 includes a transfer gate 408,
409, 416, 417 and inverters 412, 41
3, 420, and 421, an input terminal is connected to the reset terminal 403, an output terminal is connected to the inverter 425 connected to the node 424, and a source terminal is connected to the higher power supply terminal 406. A P-channel MOS transistor 422 having a drain terminal connected to the node 418 and a gate terminal connected to the node 424;
An N-channel MOS transistor 423 whose source terminal is connected to the lower power supply terminal 407, whose drain terminal is connected to the node 419, and whose gate terminal is connected to the reset terminal 403 is added.

The transfer gate 408 has a control terminal connected to the clock input terminal 401, a reverse phase control terminal connected to the negative phase clock input terminal 402, an input terminal connected to the negative phase divided clock output terminal 405, and an output. A terminal is connected to node 410.

The transfer gate 409 has a control terminal connected to the clock input terminal 401, a reverse-phase control terminal connected to the negative-phase clock input terminal 402, an input terminal connected to the divided clock output terminal 404, and an output terminal. A terminal is connected to the node 411.

The input terminal of the inverter 412 is a node 410.
, And the output terminal is connected to the node 414.
The inverter 413 has an input terminal connected to the node 411 and an output terminal connected to the node 415.

The transfer gate 416 has a control terminal connected to the negative-phase clock input terminal 402, a negative-phase control terminal connected to the clock input terminal 401, an input terminal connected to the node 414, and an output terminal connected to the node 418. Have been.

The transfer gate 417 has a control terminal connected to the negative-phase clock input terminal 402, a negative-phase control terminal connected to the clock input terminal 401, an input terminal connected to the node 415, and an output terminal connected to the node 419. Have been.

The inverter 420 has an input terminal connected to the node 41.
8 and the output terminal is a divided clock output terminal 404
It is connected to the. The inverter 421 has an input terminal connected to the node 419, and an output terminal connected to the inverted-phase divided clock output terminal 405.

Next, the operation of the above-structured dynamic frequency divider with reset function will be described. The level applied to the higher power supply terminal 406 is defined as a high level, and the level applied to the lower power supply terminal 407 is defined as a low level. Since a signal having the opposite phase to the signal applied to the clock input terminal 401 is always applied to the opposite phase clock input terminal 402, only the signal applied to the clock input terminal 401 will be described below. A signal applied to the clock input terminal 401 is called a clock signal, and a signal applied to the reset terminal 403 is called a reset signal.

When the clock signal is low, the transfer gates 408 and 409 open and the transfer gates 416 and 417 close. At this time, if the reset signal is at a high level, the node 424 is output by the inverter 425.
Outputs a low level, and a P-channel MOS transistor 422 and an N-channel MOS transistor 42
3 turns on, the node 418 is charged to a high level, the node 419 is discharged to a low level, and the frequency divider is initialized. Thereafter, when the reset signal changes to low level, the nodes 418 and 419 become dynamic nodes holding high level and low level, respectively.

The divided clock output terminal 404 and the node 41
A low level, which is a negative value of the high level held at the dynamic node 418, is written into the 1 by the inverter 420, and a low level held at the dynamic node 419 is written to the antiphase divided clock output terminal 405 and the node 410. Is the negative level of the inverter 42
Written by one.

Here, when the clock signal changes from the low level to the high level, the transfer gates 408 and 409 are closed, the transfer gates 416 and 417 are opened, and the nodes 410 and 411 correspond to the dynamic nodes holding the high level and the low level, respectively. Become. Node 418
The low level which is the negative value of the high level held at the dynamic node 410 is written by the inverter 412, and the high level is output to the divided clock output terminal 404 by the inverter 420. Node 4
A high level, which is the negative value of the low level held at the dynamic node 411, is written into the 19 by the inverter 413, and a low level is output from the inverter 421 to the inverted-phase divided clock output terminal 405.

Next, when the clock signal changes from the high level to the low level, the transfer gates 408 and 4
09 is opened, the transfer gates 416 and 417 are closed, the nodes 418 and 419 become dynamic nodes holding low level and high level, respectively, and the output levels of the divided clock output terminal 404 and the inverted phase divided clock output terminal 405 are respectively The high level and the low level are maintained, and the low level and the high level are written to the nodes 410 and 411, respectively.

When the clock signal changes to the high level again, the transfer gates 408 and 409 close, the transfer gates 416 and 417 open, and the nodes 410 and 411 become low-level and high-level holding dynamic nodes, respectively. At this time, nodes 418 and 419
The high level and the low level are written by the inverters 412 and 413, respectively, and the low level and the high level are output to the divided clock output terminal 404 and the inverted phase divided clock output terminal 405 by the inverters 420 and 421, respectively. You.

When the clock signal changes to the low level again, the transfer gates 408 and 409 open, the transfer gates 416 and 417 close, and the node 418
And 419 are dynamic nodes holding high level and low level, respectively. Divided clock output terminal 404
And the output level of the inverted phase divided clock output terminal 405 is
The low level and the high level are held, respectively, and the nodes 410 and 411 are written with the high level and the low level, respectively.

By repeating the above operation, the divided clock output terminal 404 and the inverted phase divided clock output terminal 405
Has a cycle twice as long as the clock signal, in other words, a half frequency clock signal having a half frequency and a two-phase clock signal having the opposite phase.
A divided clock signal is output.

Next, a description will be given of a dynamic frequency divider with a reset function as a second conventional example shown in FIG.

As shown in FIG. 6, a conventional dynamic frequency divider with a reset function includes a transfer gate 504.
, An inverter 505, and a transfer gate 506
, A loop in which a loop is formed by the inverter 507 and the inverter 508, a frequency-divided clock output terminal 503 is connected to the output side of the inverter 508, a source terminal is connected to the lower power supply terminal 511, and a drain terminal An N-channel MOS transistor 509 connected to the node 514 and having a gate terminal connected to the reset terminal 510 is added.

The transfer gate 504 has a control terminal connected to the clock input terminal 501, an antiphase control terminal connected to the antiphase clock input terminal 502, an input terminal connected to the divided clock output terminal 503, and an output terminal. Node 5
12 is connected.

The transfer gate 506 has a control terminal connected to the negative-phase clock input terminal 502, a negative-phase control terminal connected to the clock input terminal, and an input terminal connected to the node 513.
, And the output terminal is connected to the node 514.

The inverter 505 has an input terminal connected to the node 51.
2 and the output terminal is connected to the node 513. The inverter 507 has an input terminal connected to the node 514 and an output terminal connected to the input terminal of the inverter 508. The inverter 508 has an input terminal connected to the output terminal of the inverter 507, and an output terminal connected to the divided clock output terminal 503.

Next, the operation of the dynamic frequency divider with the reset function having the above configuration will be described. Note that a level applied to the lower power supply terminal 511 is defined as a low level. Since a signal having the opposite phase to the signal applied to the clock input terminal 501 is always applied to the opposite phase clock input terminal 502, only the signal applied to the clock input terminal 501 will be described below. A signal applied to the clock input terminal 501 is called a clock signal, and a signal applied to the reset terminal 503 is called a reset signal.

When the clock signal is at a low level, the transfer gate 504 is opened and the transfer gate 50
6 closes. At this time, when the reset signal goes high, the N-channel MOS transistor 509 turns on,
The node 514 is discharged to a low level, and the frequency divider is initialized. When the reset signal changes to low level, the node 514 becomes a dynamic node holding low level.

At this time, a low level is written to the divided clock output terminal 503 by the inverters 508 and 509, and a low level is also written to the node 512.

When the clock signal changes from a low level to a high level, the transfer gate 504 closes and the transfer gate 506 opens. Therefore, the node 512 is in a dynamic holding state. The high level of the negative value of the low level held at the node 512 by the inverter 505 is written to the node 514. Therefore, the high level written at the node 514 is output to the divided clock output terminal 503.

When the clock signal changes from the high level to the low level, the transfer gate 504 opens and the transfer gate 506 closes. Therefore, the node 514 is in a dynamic holding state. At this time, although the state of the divided clock signal does not change, the high level held at the node 514 by the inverters 507 and 508 is written to the node 512.

When the clock signal changes from low level to high level, the transfer gate 504 closes and the transfer gate 506 opens. At this time, the node 512 is in a dynamic holding state. To the node 514, the low level of the high-level negative value held at the node 512 by the inverter 505 is output. Therefore, a low level is written to the divided clock output terminal.

When the clock signal changes from the high level to the low level again, the transfer gate 504 opens, the transfer gate 506 closes, and the node 514 enters a dynamic holding state. At this time, the output to the divided clock output terminal does not change, but the low level held at the node 514 by the inverters 507 and 508 is written to the node 512.

By repeating the above operation, a frequency-divided clock signal having twice the period of the clock signal, that is, a frequency-divided clock signal having a half frequency is output to the frequency-divided clock output terminal 503.

Next, a description will be given of a dynamic type frequency divider with a set function as a third conventional example shown in FIG.

As shown in FIG. 7, a conventional dynamic frequency divider with a set function is provided with a transfer gate 60.
5, a loop formed by an inverter 606, a transfer gate 607, an inverter 608, and an inverter 609, and a frequency divider having a frequency-divided clock output terminal 603 connected to the output side of the inverter 609;
It is configured by adding a channel type MOS transistor 611.

The transfer gate 605 has a control terminal connected to the clock input terminal 601, an antiphase control terminal connected to the antiphase clock input terminal 602, an input terminal connected to the frequency-divided clock output terminal 603, and an output terminal. Node 6
14.

The input terminal of the inverter 606 is the node 61.
4 and the output terminal is connected to the node 615.

The transfer gate 607 has a control terminal connected to the negative phase clock input terminal, a negative phase control terminal connected to the clock input terminal, an input terminal connected to the node 615, and an output terminal connected to the node 616. I have.

The inverter 608 has an input terminal connected to the node 61
6 and the output terminal is connected to the node 617.

The input terminal of the inverter 609 is the node 61
7 and the output terminal is a divided clock output terminal 603
It is connected to the.

The inverter 610 has an input terminal connected to the set terminal 604 and an output terminal connected to the gate terminal of the P-channel MOS transistor 611.

P channel type MOS transistor 611
Has a source terminal connected to the higher power supply terminal 613, a drain terminal connected to the node 616, and a gate terminal connected to the output terminal of the inverter 610.

The operation of the above-configured dynamic frequency divider with a set function will be described. Note that, similarly to the above description, since a signal having a phase opposite to the signal applied to the clock input terminal 601 is always applied to the inverted clock input terminal 602, the signal applied to the clock input terminal 601 is referred to as a clock signal. A signal applied to the set terminal 604 is called a set signal.

When the clock signal is at a low level, the transfer gate 605 opens and the transfer gate 60
Since node 7 is closed, node 616 is in a dynamic holding state. At this time, when the set signal goes high, P
A low level is applied to the gate terminal of the channel type MOS transistor 611 by the inverter 610. Since the high-order power supply terminal 613 is connected to the source terminal of the P-channel MOS transistor, the node 616 is set to the high level.

A high level is written to the divided clock output terminal 603 by the inverters 608 and 609.
The high level is also written to the node 614.

When the clock signal changes from a low level to a high level, the transfer gate 605 closes and the transfer gate 607 opens. Therefore, the node 614 is in a dynamic holding state. The low level of the negative high-level value held at the node 614 by the inverter 606 is written to the node 616. Accordingly, the low level written at the node 616 is output to the divided clock output terminal 603.

When the clock signal changes from the high level to the low level, the transfer gate 605 opens and the transfer gate 607 closes. Therefore, the node 616 is in the dynamic holding state. At this time, the state of the divided clock signal does not change, but the low level held at the node 616 by the inverters 608 and 609 is written to the node 614.

When the clock signal changes from low level to high level, the transfer gate 605 closes and the transfer gate 607 opens. At this time, the node 614 is in a dynamic holding state. The high level of the negative value of the low level held at the node 614 by the inverter 606 is output to the node 616. Therefore, a high level is written to the divided clock output terminal.

When the clock signal changes from the high level to the low level again, the transfer gate 605 opens, the transfer gate 607 closes, and the node 616 enters a dynamic holding state. At this time, the output to the divided clock output terminal does not change, but the high level held at the node 616 by the inverters 608 and 609 is written to the node 614.

By repeating the above operation, the frequency-divided clock output terminal 603 outputs a frequency-divided clock signal having a cycle twice as long as the clock signal, in other words, a frequency half the frequency.

[0048]

However, in the above-described frequency divider of the prior art, the frequency divider is not initialized by the reset signal or the set signal, and there is a timing at which the power consumption increases.

For example, in the frequency divider of the first conventional example shown in FIG. 8, when the reset signal is input while the clock signal is at the high level and the node 410 is kept at the high level, the node 418 Is charged to a high level by a P-channel MOS transistor 422 and the inverter 41
2 collides with the discharge to the low level, and the initialization operation is not performed correctly. When the reset signal changes to low level during the high level period of the clock signal, the node 418 is discharged to low level by the inverter 412, and desired initialization is not performed.

Similarly, when the reset signal is input while the clock signal is at the high level and the low level is held at the node 411, the node 419 becomes the N-channel type M
Discharge to a low level by the OS transistor 423;
The charging to the high level by the inverter 413 collides, and the initialization operation is not performed properly. Further, when the reset signal changes to the low level during the high level period of the clock signal, the node 419 is charged to the high level by the inverter 413, and the desired initialization operation is not performed.

The reset signal is at a high level, and the high level is held at the node 410. During the period when the clock signal is at the high level, the P-channel MOS transistor 422 is turned on, and the N-channel Since the type MOS transistor 426 is also on, P
A through current flows from the higher power supply terminal 406 connected to the source terminal of the channel MOS transistor 422 to the lower power supply terminal 407 connected to the source terminal of the N-channel MOS transistor 426, and the power consumption during initialization is reduced. The problem that the current increases is caused.

The reset signal is at high level, the low level is held at the node 411, and the N-channel MOS transistor 423 is turned on during the high level of the clock signal. Since the p-channel MOS transistor 429 is also turned on, the p-channel MOS transistor 42
9 high-side power supply terminal 406 connected to the source terminal
, A through current flows to the lower power supply terminal 407 connected to the source terminal of the N-channel type MOS transistor 423, and a problem occurs that current consumption during initialization increases.

FIG. 9 shows a simulation waveform of the frequency divider of the first prior art. As shown in FIG. 9, when the reset signal is applied over a period between the low level and the high level of the clock signal, the initialization is not performed as described above, the through current flows, and the current consumption increases. .

These problems also occur in the frequency dividers of Conventional Examples 2 and 3 described above.

The present invention has been made in view of the above circumstances, and a dynamic frequency divider with a reset function which can initialize a circuit at an arbitrary timing and does not increase power consumption at the time of initialization. It is an object to provide a dynamic frequency divider with a set function.

[0056]

In order to achieve the above object, a dynamic frequency divider with a reset function according to the present invention comprises:
A first output stage for inputting a signal output to a second output terminal and outputting the signal to a first output terminal, and a second output terminal for inputting a signal output to a first output terminal And a second output stage for output to the first output stage. The first output stage is provided with first switch means, first inverter means, second switch means, and second inverter means. The second output stage is provided with third switch means, third inverter means, fourth switch means, and fourth inverter means, and the first switch means has an input side. The first inverter means is connected to the output side of the fourth inverter means, the input side is connected to the output side of the first switch means, the output side is connected to the input side of the second switch means,
The second inverter has an input connected to an output of the second switch, an output connected to a first output terminal, and a third switch having an input connected to an output of the second inverter. The third inverter means has an input side connected to the output side of the third switch means, an output side connected to the input side of the fourth switch means, and the fourth inverter means has an input side connected to the fourth side. And the output side is connected to the second output terminal, and the first switch means, the second switch means, the third switch means, and the fourth switch means are connected to each other. A dynamic frequency divider with a reset function connected to a first clock input terminal and a second clock input terminal, wherein a source terminal is connected to a first power supply terminal, and a drain terminal is connected to a second switch means. Output side and A first first conductivity type connected to a first node connecting the input side of the second inverter means and a gate terminal connected to an output side of the fifth inverter means for receiving a reset signal from the reset terminal. A MOS transistor, a source terminal connected to the second power supply terminal, a drain terminal connected to a second node connecting the output side of the fourth switch means and the input side of the fourth inverter means,
A first second conductivity type MOS transistor having a gate terminal connected to the reset terminal, a source terminal connected to the second clock input terminal, a drain terminal connected to the output side of the first switch means, and a first inverter; A second second conductivity type MOS transistor connected to a third node connecting the input side of the means and having a gate terminal connected to the reset terminal; a source terminal connected to the first clock input terminal; and a drain terminal. Is connected to a fourth node connecting the output side of the third switch means and the input side of the third inverter means, and the gate terminal is connected to the output side of the fifth inverter means. And one conductive type MOS transistor.

The switch means is a transfer gate, and a first clock input terminal is connected to control terminals of the first switch means and the third switch means.
A second clock input terminal is connected to the negative phase control terminal, a second clock input terminal is connected to control terminals of the second switch means and the fourth switch means, and a negative phase control terminal is connected to the negative phase control terminal. , A first clock input terminal.

The dynamic frequency divider with reset function of the present invention comprises: a fifth switch means, a sixth inverter means, a sixth switch means, a seventh inverter means,
A loop is formed by the eighth inverter means,
The output terminal of the fifth inverter is connected to the output of the fifth inverter. The input terminal of the fifth switch is connected to the output of the eighth inverter. The sixth inverter has the output of the fifth switch. The output side is connected to the input side of the sixth switch means, and the seventh inverter means has an input side connected to the sixth switch means, and an output side connected to the input side of the eighth inverter means, The fifth switch means and the sixth switch means are a dynamic frequency divider with a reset function connected to the first clock input terminal and the second clock input terminal, and the source terminal is a second power supply. A third terminal having a drain terminal connected to a fifth node connecting an input side of the sixth switch means and an output side of the seventh inverter means, and a gate terminal connected to the reset terminal. And second conductivity type MOS transistor,
The source terminal is connected to the first clock terminal, the drain terminal is connected to a sixth node connecting the output side of the fifth switch means and the input side of the sixth inverter means, and the gate terminal receives the reset terminal. And a third first conductivity type MOS transistor connected to the output side of the ninth inverter means connected to the first side.

The switch means is a transgate, and the control terminal of the fifth switch means is connected to the first clock input terminal, and the reverse phase control terminal is connected to the second clock input terminal. Preferably, the control terminal of the sixth switch means is connected to the second clock input terminal, and the opposite phase control terminal is connected to the first clock input terminal.

The dynamic frequency divider with the set function of the present invention comprises a seventh switch, a tenth inverter, an eighth switch, an eleventh inverter, and a twelfth inverter. A loop is formed, an output terminal is connected to the output side of the twelfth inverter means, the seventh switch means has an input side connected to the output side of the twelfth inverter means, and the tenth inverter means has Side is connected to the output side of the seventh switch means,
The output side is connected to the input side of the eighth switch means,
The first inverter means has an input side connected to the output side of the eighth switch means, an output side connected to the input side of the twelfth inverter means, and the seventh switch means and the eighth switch means connected to the first switch means. A frequency divider with a set function connected to the clock input terminal and the second clock input terminal of
The source terminal is connected to the first power supply terminal, the drain terminal is connected to a seventh node connecting the output side of the eighth switch means and the input side of the eleventh inverter means, and the gate terminal inputs the set terminal. A fourth first conductivity type MOS transistor connected to the output side of the thirteenth inverter means connected to the output side, a source terminal connected to the second clock input terminal, and a drain terminal connected to the output of the seventh switch means. A fourth second conductivity type MOS transistor connected to an eighth node connecting the first side and the input side of the tenth inverter means, and having a gate terminal connected to the set terminal.

The switch means is a transfer gate. The control terminal of the seventh switch means is connected to the first clock input terminal, and the control terminal of the seventh switch means is connected to the second phase control terminal.
, The control terminal of the eighth switch means is connected to the second clock input terminal, and the antiphase control terminal is connected to the first clock input terminal.

[0062]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a dynamic frequency divider with a reset function and a dynamic frequency divider with a set function according to the present invention. 1 to 4 show an embodiment of a dynamic frequency divider with a reset function and a dynamic frequency divider with a set function of the present invention.

First, an embodiment of a dynamic frequency divider with a reset function according to the present invention will be described in detail with reference to FIG. FIG. 1 shows a first embodiment of a dynamic frequency divider with a reset function.

As shown in FIG. 1, the dynamic frequency divider with reset function of the first embodiment inputs the signal output to the negative-phase divided clock output terminal 105 and outputs the signal to the divided clock output terminal 104. The frequency divider includes a first output stage for performing the above operation, and a second output stage for receiving the signal output to the divided clock output terminal 104 and outputting the signal to the opposite-phase divided clock output terminal 105. In the first output stage, a transfer gate 108, an inverter 112, a transfer gate 116 and an inverter 120 are provided. Also, the transfer gate 10 is provided at the second output stage.
9, the inverter 113, and the transfer gate 117
And an inverter 121. The frequency divider is configured by adding an inverter 127, N-channel MOS transistors 122 and 126, and P-channel MOS transistors 123 and 125.

The transfer gate 108 has a control terminal connected to the clock input terminal 101, an antiphase control terminal connected to the antiphase clock input terminal 102, an input terminal connected to the antiphase divided clock output terminal 105, and an output terminal. A terminal is connected to node 110.

The transfer gate 109 has a control terminal connected to the clock input terminal 101, an antiphase control terminal connected to the antiphase clock input terminal 102, an input terminal connected to the frequency-divided clock output terminal 104, and an output terminal. Node 1
11 is connected.

The input terminal of the inverter 112 is the node 11
0 and the output terminal is connected to the node 114. The inverter 113 has an input terminal connected to the node 111.
, And the output terminal is connected to the node 115.

The transfer gate 116 has a control terminal connected to the negative-phase clock input terminal 102, a negative-phase control terminal connected to the clock input terminal 101, an input terminal connected to the node 114, and an output terminal connected to the node 118. Have been.

The transfer gate 117 has a control terminal connected to the negative-phase clock input terminal 102, a negative-phase control terminal connected to the clock input terminal 101, an input terminal connected to the node 115, and an output terminal connected to the node 119. Have been.

The inverter 120 has an input terminal connected to the node 11
8 and the output terminal is a divided clock output terminal 104
It is connected to the. The inverter 121 has an input terminal connected to the node 119 and an output terminal connected to the negative-phase divided clock output terminal 105.

The inverter 127 has an input terminal connected to the reset terminal 103 and an output terminal connected to the node 124.

N channel type MOS transistor 122
Has a source terminal connected to the negative-phase clock input terminal 102, a drain terminal connected to the node 110, and a gate terminal connected to the reset terminal 103.

P channel type MOS transistor 123
Has a source terminal connected to the clock input terminal 101,
The drain terminal is connected to node 111, and the gate terminal is connected to node 124.

P channel type MOS transistor 125
Has a source terminal connected to the higher power supply terminal 106, a drain terminal connected to the node 118, and a gate terminal connected to the node 124.

N-channel MOS transistor 126
Has a source terminal connected to the lower power supply terminal 107, a drain terminal connected to the node 119, and a gate terminal connected to the reset terminal 103.

Next, the operation of the above-configured dynamic frequency divider with reset function will be described. In the following description, the level applied to the high-order power supply terminal 106 is a high level, the level applied to the low-order power supply terminal 107 is a low level, and the opposite-phase clock input terminal 102 is always connected to the clock input terminal 101. Since a signal having a phase opposite to that of the signal to be added is added, the clock input terminal 10
Only the signal added to 1 will be described. A signal applied to the clock input terminal 101 is called a clock signal, and a signal applied to the reset terminal 103 is called a reset signal.

When the clock signal is at the low level, the transfer gates 108 and 109 are opened and the transfer gates 116 and 117 are closed.
Reference numerals 9 indicate a dynamic holding state. At this time,
The case where the nodes 118 and 119 are at a high level and a low level, respectively, will be described.

The divided clock output terminal 104 and the node 11
1, the low level which is the negative value of the high level held at the dynamic node 118 is written by the inverter 120, and the low-level signal held at the dynamic node 119 is applied to the negative-phase divided clock output terminal 105 and the node 110. Is a negative level of the inverter 121
Written by

Here, when the clock signal changes from the low level to the high level, the transfer gates 108 and 109 close, the transfer gates 116 and 117 open, and the nodes 110 and 111 become the dynamic nodes holding the high level and the low level, respectively. Become.

The node 118 has a dynamic node 110
The low level, which is the negative value of the high level held in the above, is written by the inverter 112, and the high level is output to the divided clock output terminal 104 by the inverter 120. The node 119 has a dynamic node 1
The high level, which is the negative value of the low level held in 11, is written by the inverter 113, and the low level is output from the inverter 121 to the inverted phase divided clock output terminal 105.

Next, when the clock signal changes to the low level, the transfer gates 108 and 109 are opened, the transfer gates 116 and 117 are closed, and the nodes 118 and 119 become the dynamic nodes holding the low level and the high level, respectively. The output levels of the output terminal 104 and the inverted-phase divided clock output terminal 105 are maintained at the high level and the low level, respectively, and the low level and the high level are written to the nodes 110 and 111, respectively.

When the clock signal changes to the high level again, the transfer gates 108 and 109 close, the transfer gates 116 and 117 open, and the nodes 110 and 111 become dynamic nodes holding the low level and the high level, respectively. At this time, nodes 118 and 119
, High and low levels are written by inverters 112 and 113, respectively, and low and high levels are output to the divided clock output terminal 104 and the negative-phase divided clock output terminal 105 by inverters 120 and 121, respectively. .

When the clock signal changes to the low level again, the transfer gates 108 and 109 open, the transfer gates 116 and 117 close, and the node 118
And 119 are high-level and low-level holding dynamic nodes, respectively. At this time, the output levels of the divided clock output terminal 104 and the inverted-phase divided clock output terminal 105 are maintained at low level and high level, respectively, and the high level and low level are written to the nodes 110 and 111, respectively. .

By repeating the above operation, the divided clock output terminal 104 and the inverted phase divided clock output terminal 105
, A two-divided clock signal having a cycle twice as long as the clock signal, in other words, a half-frequency clock signal having a half frequency and a two-divided clock signal having a phase opposite thereto are output.

Next, the initialization operation which is a feature of the present invention will be described. In the dynamic frequency divider with reset function of the present invention, the divided clock signal rises at the rising edge of the clock signal that appears first after the input of the reset signal. To perform such an operation, the node 110 is at the opposite level to the clock signal, the node 111 is at the same level as the clock signal, and the nodes 118 and 119 are at the high level regardless of the level of the clock signal. And low level.

Therefore, in the dynamic frequency divider with reset function of this embodiment, when a reset signal is input from the reset terminal 103, the node 118 is always set to the high level by the P-channel MOS transistor 125. Further, the node 119 is always set to the low level by the N-channel MOS transistor 126. Also, N
The channel type MOS transistor 122 allows the node 11
0 is set to a level opposite to the level of the clock signal.
Further, by the P-channel type MOS transistor 123,
The node 111 is set to the same level as the clock signal.

Since a high level is applied to the source terminal of the P-channel MOS transistor 125 by the high-order power supply terminal 106, when the reset signal changes to the high level, the gate terminal of the P-channel MOS transistor 125 is The low level is applied by the inverter 127 to turn on the P-channel MOS transistor 125, and the node 118 is set to the high level.

Since a low level is applied to the source terminal of the N-channel MOS transistor 126 from the lower power supply terminal 107, when the reset signal changes to a high level, the gate terminal of the N-channel MOS transistor 126 becomes high. Level is applied and N channel type MO
The S transistor 126 turns on, setting the node 119 to low level.

Since the negative-phase clock signal from the negative-phase clock input terminal is output to the source terminal of the N-channel MOS transistor 122, when the reset signal changes to a high level, the N-channel MOS transistor 1
A high level is applied to the gate terminal of the node 22 to turn on the N-channel MOS transistor 122, and the node 110
The level is set to the same level as the reverse phase clock signal, that is, the level opposite to the level of the clock signal.

Since the clock input signal from the clock input terminal is output to the source terminal of the P-channel MOS transistor 123, when the reset signal goes high, the inverter 127 is connected to the gate terminal of the P-channel MOS transistor 123. To apply a low level to turn on the P-channel MOS transistor 123,
The node 111 is set to the same level as the clock signal.

When the clock signal is at the low level, the transfer gates 108 and 109 open, and the transfer gates 116 and 117 close. Therefore, node 11
8 and 119 are in the dynamic holding state, and the state of each node of the circuit is determined by the value of these nodes.

When the reset signal goes high, a low level is output to the node 124 by the inverter 127, and both the P-channel MOS transistor 125 and the N-channel MOS transistor 126 are turned on.
18 is charged to a high level, and the node 119 is discharged to a low level.

The high level of the negative value of the node 119 is written into the node 110 by the inverter 121, and the node 1
The low level of the negative value of the node 118 is written to 11 by the inverter 120.

At this time, a high level is applied to the gate terminal of the N-channel MOS transistor 122. However, since both the source terminal and the drain terminal are at the high level, the operation of the circuit is not affected. Similarly, a low level is applied to the gate terminal of the P-channel type MOS transistor 123, but since both the source terminal and the drain terminal are at the low level, the circuit operation is not affected.

When the clock signal changes from the low level to the high level, the transfer gates 108 and 109 close and the transfer gates 116 and 117 open. Therefore, the nodes 110 and 111 are in the state of dynamic holding, and the state of each node of the circuit is determined by the value of each of these nodes.

Since a low level is applied to the source terminal of the N-channel MOS transistor 122 by the negative-phase clock input terminal 102, when the reset signal goes high at this time, the gate terminal of the N-channel MOS transistor 122 is The high level is applied, and the N-channel MOS transistor 122 turns on. Therefore, the node 110 is discharged to a low level.

Also, the P-channel type MOS transistor 1
Since a high level is applied to the source terminal 23 by the clock input terminal 101, if the reset signal goes high at this time, a low level is applied to the gate terminal of the P-channel MOS transistor 123 by the inverter 127, P-channel type MOS transistor 1
23 turns on. Therefore, the node 111 is charged to a high level.

At the node 118, the high level of the negative value of the node 110 is written by the inverter 112, and the node 1
The low level of the negative value of the node 111 is written to 19 by the inverter 113.

The above-described operations coincide with the operations of charging the node 118 and discharging from the node 119 by turning on the P-channel MOS transistor 125 and the N-channel MOS 126, respectively, thereby preventing a through current from flowing. .

When the reset signal is input as described above, the node 110 is set to the opposite level to the clock, the node 111 is set to the same level as the clock, and the nodes 118 and 1 are set.
19 is set to a high level and a low level, respectively, irrespective of the level of the clock signal. Therefore, as shown in FIG. 2, the reset signal is applied over the period of the low level and the high level of the clock signal. Also, initialization is performed such that the divided clock signal rises at the rising edge of the clock signal that appears first after the input of the reset signal, so that current consumption during the initialization operation period can be suppressed.

Also, regardless of whether the clock signal is at a high level or a low level, all nodes in the circuit are set to a level at which a desired operation is performed, and the circuit can be initialized at an arbitrary timing. Since there is no path through which a through current flows, there is no increase in power consumption during initialization.

Next, a second embodiment of the dynamic frequency divider with reset function of the present invention will be described with reference to FIG.

As shown in FIG. 3, the dynamic frequency divider with reset function of the second embodiment includes a transfer gate 204, an inverter 206, and a transfer gate 2
07, an inverter 208, and an inverter 209, a loop is formed, a frequency divider having a frequency-divided clock output terminal 203 connected to the output side of the inverter 209, a source terminal connected to the lower power supply terminal 213, and a drain terminal connected to the node. An N-channel MOS transistor 211 connected to the reset terminal 212 and connected to the reset terminal 212;
A P-channel M type having a source terminal connected to the clock input terminal 201, a drain terminal connected to the node 214, and a gate terminal connected to the output terminal of the inverter 210 for inverting the output of the reset signal from the reset terminal.
An OS transistor 205 is additionally provided.

The transfer gate 204 has a control terminal connected to the clock input terminal 201, an antiphase control terminal connected to the antiphase clock input terminal 202, an input terminal connected to the divided clock output terminal 203, and an output terminal. Node 2
14.

The input terminal of the inverter 206 is the node 214.
, And the output terminal is connected to the node 215.

The transfer gate 207 has a control terminal connected to the negative-phase clock input terminal 202, a negative-phase control terminal connected to the clock input terminal 201, an input terminal connected to the node 215, and an output terminal connected to the node 216. Have been.

The inverter 208 has an input terminal connected to the node 21.
6 and the output terminal is connected to the input terminal of the inverter 209. The output signal from the inverter 209 is output to the divided clock output terminal 203,
Input to the transfer gate 204.

The operation of the above-structured dynamic frequency divider with reset function will be described. Similarly to the above description, since a signal having a phase opposite to that of the signal applied to the clock input terminal 201 is always applied to the inverted phase clock input terminal 202, the signal applied to the clock input terminal 201 is called a clock signal. A signal applied to the reset terminal is called a reset signal.

When the clock signal is at a low level, the transfer gate 204 opens and the transfer gate 20
Since node 7 is closed, node 216 is in a dynamic holding state. At this time, the case where the node 216 is at the low level will be described.

At this time, a low level is written to the divided clock output terminal 203 by the inverters 208 and 209, and a low level is also written to the node 214.

When the clock signal changes from the low level to the high level, the transfer gate 204 closes and the transfer gate 207 opens. Therefore, the node 214 is in a dynamic holding state. The high level of the negative value of the low level held at the node 214 by the inverter 206 is written to the node 216. Therefore, the high level written to the node 216 by the inverters 208 and 209 is output to the divided clock output terminal 203.

When the clock signal changes from the high level to the low level, the transfer gate 204 opens and the transfer gate 207 closes. Therefore, the node 216 is in a dynamic holding state. At this time, the state of the divided clock signal does not change, but the high level held at the node 216 by the inverters 208 and 209 is written to the node 214.

When the clock signal changes from low level to high level, the transfer gate 204 closes and the transfer gate 207 opens. At this time, the node 214 enters a dynamic holding state. The low level of the negative value of the high level held at the node 214 by the inverter 206 is output to the node 216. Therefore, a low level is written to the divided clock output terminal 203.

When the clock signal changes from the high level to the low level again, the transfer gate 204 opens, the transfer gate 207 closes, and the node 216 enters a dynamic holding state. At this time, the output to the divided clock output terminal 203 does not change, but the low level held at the node 216 by the inverters 208 and 209 is written to the node 214.

By repeating the above operation, a frequency-divided clock signal having twice the period of the clock signal, that is, a frequency-divided clock having a half frequency, is output to the frequency-divided clock output terminal 203.

In the dynamic frequency divider with reset function of the present invention, the divided clock signal rises at the rising edge of the clock signal that appears first after the input of the reset signal.
In order to perform such an operation, the node 214 is always set to the same level as the clock signal by the reset signal,
6 must be set to a low level regardless of the signal level of the clock signal.

Therefore, in this embodiment, when the reset signal changes to the high level, the node 216 is discharged to the low level by the N-channel MOS transistor 211. The node 214 is set to the same level as the clock signal by the P-channel MOS transistor 205.

Since a low level is applied to the source terminal of the N-channel MOS transistor 211 from the lower power supply terminal 213, when the reset signal goes high, the gate terminal of the N-channel MOS transistor 211 goes high. Is applied, the N-channel MOS transistor 211 is turned on, and the node 216 is set to a low level.

Since the clock signal from the clock input terminal 201 is input to the source terminal of the P-channel MOS transistor 205, when the reset signal goes high, the inverter 210 connects the gate terminal of the P-channel MOS transistor 205 to the gate terminal. When a low level is applied, the P-channel MOS transistor 205 turns on,
The node 214 is set to the same level as the clock signal.

When the reset signal is input while the clock signal is at the low level, the node 214 becomes the P-channel type M
The low level is set by the OS transistor 205. At this time, the node 216 is set to a low level by the N-channel MOS transistor 211. Therefore, a low level is output to the divided clock output terminal 203.

When the clock signal changes to high level after the reset signal changes from high level to low level,
The transfer gate 204 closes and the transfer gate 207 opens. Therefore, the node 216 has the inverter 2
At 06, the high level of the negative value of the low level held at the node 214 is written. Therefore, a high level is output to the divided clock output terminal 203. As described above, the frequency-divided clock signal can rise at the rise of the clock signal after the input of the reset signal.

When the clock signal changes from the low level to the high level while the reset signal is at the high level, the node 214 is written to the high level by the P-channel MOS transistor 205. At this time, since the transfer gate 207 is open, writing to the node 216 by the inverter 206 occurs. However, since the node 214 is set to the same level as the clock signal by the P-channel MOS transistor 205, the inverter 206 The writing to the node 216 does not collide with the discharge of the node 216 to the low level by the N-channel MOS transistor.

When the clock signal changes from high level to low level after the reset signal changes to low level, the transfer gate 204 opens and the transfer gate 207 closes. At this time, the output to the divided clock output terminal does not change, but the low level held at the node 216 by the inverters 208 and 209 is written to the node 214.

When the clock signal changes from the low level to the high level, the transfer gate 204 closes and the transfer gate 207 opens. Therefore, the high level of the negative value of the low level held at the node 214 is written to the node 216 by the inverter 206. Therefore,
The divided clock output terminal 203 outputs the high level written at the node 216. Thus, the divided clock signal changes to the high level at the rise of the clock signal after the reset signal is input.

When a reset signal is input while the clock signal is at the high level, the node 214 is set to the high level by the P-channel MOS transistor 205. At this time, the node 216 is an N-channel type MOS.
The low level is set by the transistor 211. At this time, since the transfer gate 207 is open, writing to the node 216 by the inverter 206 is performed.
Since the level is set to the same level as that of the clock signal by 05, the writing by the inverter 206 and the discharging to the low level by the N-channel MOS transistor 211 do not collide.

When the clock signal changes to low level after the reset signal changes from high level to low level,
The transfer gate 204 opens and the transfer gate 207 closes. At this time, the output of the divided clock signal does not change, but the node 214 is rewritten to a low level by the inverters 208 and 209.

Thereafter, when the clock signal changes to the high level, the transfer gate 204 closes and the transfer gate 207 opens. Accordingly, the high level of the negative value of the low level held at the node 214 by the inverter 206 is written to the node 216. Therefore, a high level is written to the divided clock output terminal 203. As described above, the frequency-divided clock signal can rise at the rise of the clock signal after the input of the reset signal.

When the clock signal changes from the high level to the low level while the reset signal is at the high level, the node 214 is written to the low level by the P-channel MOS transistor 205.

When the clock signal changes from the low level to the high level after the reset signal changes to the low level, the transfer gate 204 closes and the transfer gate 207 opens. Accordingly, the high level of the negative value of the low level held at the node 214 by the inverter 206 is written to the node 216. Accordingly, a high level is output to the frequency-divided clock output terminal 203, and the frequency-divided clock signal changes to the high level at the rise of the clock signal after the reset signal is input.

As described above, when the reset signal is input and the clock signal is at the high level, the node 214 is always charged to the high level by the P-channel MOS transistor 205, and thus the node 214 is low-charged by the N-channel MOS transistor 211. Does not collide with discharge to the level. Therefore, the circuit can be initialized at an arbitrary timing.

Next, an embodiment of a dynamic frequency divider with a set function according to the present invention will be described in detail with reference to FIG. FIG. 4 shows an embodiment of a dynamic frequency divider with a set function according to the present invention.

As shown in FIG. 4, the embodiment of the dynamic frequency divider with the set function is the transfer gate 3
05, inverter 306, transfer gate 307,
A loop is formed by the inverter 308 and the inverter 309, and the output side of the inverter 309 is connected to the frequency-divided clock output terminal 303 by a frequency divider.
, A P-channel MOS transistor 311 and an N-channel MOS transistor 312.

The transfer gate 305 has a control terminal connected to the clock input terminal 301, an antiphase control terminal connected to the antiphase clock input terminal 302, an input terminal connected to the divided clock output terminal 303, and an output terminal. Node 3
14.

The input terminal of the inverter 306 is the node 31
4 and the output terminal is connected to the node 315.

The transfer gate 307 has a control terminal connected to the negative-phase clock input terminal 302, a negative-phase control terminal connected to the clock input terminal 301, an input terminal connected to the node 315, and an output terminal connected to the node 316. Have been.

The input terminal of the inverter 308 is the node 31.
6 and the output terminal is connected to the node 317.

The inverter 309 has an input terminal connected to the node 31.
7 and the output terminal is a divided clock output terminal 303.
It is connected to the.

The inverter 310 has an input terminal connected to the set terminal 304, and an output terminal connected to the gate terminal of the P-channel MOS transistor 311.

P-channel MOS transistor 311
Has a source terminal connected to the higher power supply terminal 313, a drain terminal connected to the node 316, and a gate terminal connected to the output terminal of the inverter 310.

N-channel MOS transistor 312
Has a source terminal connected to the negative-phase clock input terminal 302, a drain terminal connected to the node 314, and a gate terminal connected to the set terminal 304.

The operation of the above-configured dynamic frequency divider with a set function will be described. Similarly to the above description, the clock input terminal 3 is always
A signal applied to the clock input terminal 301 is called a clock signal because a signal having a phase opposite to that of the signal applied to 01 is applied. The signal applied to the set terminal 304 is called a set signal.

When the clock signal is at a low level, the transfer gate 305 opens, and the transfer gate 30
Since node 7 is closed, node 316 is in a dynamic holding state. At this time, a case where the node 316 is at a low level will be described.

A low level is written to the divided clock output terminal 303 by the inverters 308 and 309.
The low level is also written to the node 314.

When the clock signal changes from the low level to the high level, the transfer gate 305 closes and the transfer gate 307 opens. Therefore, the node 314 is in a dynamic holding state. The high level of the negative value of the low level held at the node 314 by the inverter 306 is written to the node 316. Therefore, the high level written to the node 316 by the inverters 308 and 309 is output to the divided clock output terminal 303.

When the clock signal changes from the high level to the low level, the transfer gate 305 opens and the transfer gate 307 closes. Therefore, the node 316 is in a dynamic holding state. At this time, the state of the divided clock signal does not change, but the high level held at the node 316 by the inverters 308 and 309 is written to the node 314.

When the clock signal changes from the low level to the high level, the transfer gate 305 closes and the transfer gate 307 opens. At this time, the node 314 is in a dynamic holding state. To the node 316, the low level of the high level negative value held at the node 314 by the inverter 306 is output. Therefore, a low level is written to the divided clock output terminal 303.

When the clock signal changes from the high level to the low level again, the transfer gate 305 opens, the transfer gate 307 closes, and the node 316 enters a dynamic holding state. At this time, the output to the divided clock output terminal 303 does not change, but the low level held at the node 316 by the inverters 308 and 309 is written to the node 314.

By repeating the above operation, the frequency-divided clock output terminal 303 outputs a frequency-divided clock signal having a cycle twice as long as the clock signal, in other words, a frequency half the frequency.

In the dynamic frequency divider with set function of the present invention, the divided clock signal falls at the rising edge of the clock signal that appears first after the input of the set signal. In order to perform such an operation, the node 31 is set by the set signal.
4 to the opposite level of the clock signal, and node 316
It must be set to high level regardless of the clock signal.

Therefore, in the dynamic frequency divider with a set function of this embodiment, when a set signal is input from the set terminal 304, the P-channel MOS transistor 311
Sets the node 316 to a high level. The node 314 is formed by the N-channel MOS transistor 312.
Is set to a level opposite to that of the clock signal.

Since a high level is applied to the source terminal of the P-channel MOS transistor 311 by the high-order power supply terminal 313, when the set signal goes high, the inverter 310 connects the gate terminal of the P-channel MOS transistor to the gate terminal. When a low level is applied, the P-channel MOS transistor 311 turns on, and the node 316
Is set to high level.

The N-channel MOS transistor 3
Since a negative-phase clock signal is applied to the source terminal 12 by the negative-phase clock input terminal 302, when the set signal goes high, a high level is applied to the gate terminal of the N-channel MOS transistor 312, and N The channel type MOS transistor 312 turns on, and the node 31
4 is set to the same level as the reverse phase clock signal from the reverse phase clock input terminal, that is, the level opposite to the clock input signal.

When the set signal is input during the period when the clock signal is at the low level, the node 314 becomes the N-channel type MO.
The high level is set by the S transistor 312.
At this time, the node 316 is set to a high level by the P-channel MOS transistor 311.

When the clock signal changes to the high level after the set signal changes from the high level to the low level, the transfer gate 305 closes and the transfer gate 3
07 opens. Therefore, the node 316 includes the inverter 30
6, the low level of the negative value of the high level held at the node 314 is written. Therefore, a low level is output to the divided clock output terminal 303. As described above, the divided clock signal can be changed to the low level at the rise of the clock signal after the input of the set signal.

Also, while the set signal is at the high level,
When the clock signal changes from the low level to the high level, the node 314 becomes the N-channel MOS transistor 3
12, a low level is written. At this time, since the transfer gate 307 is open, the inverter 3
06, writing to the node 316 is performed. However, since the node 314 is set to the level opposite to the level of the clock signal by the N-channel MOS transistor 312,
Writing by inverter 306 and P-channel type MO
There is no collision with charging by the S transistor 311.

When the clock signal changes from the high level to the low level after the set signal changes to the low level, the transfer gate 305 opens and the transfer gate 307 closes. At this time, the output to the divided clock output terminal does not change, but the high level held at the node 316 by the inverters 308 and 309 is written to the node 314.

When the clock signal changes from a low level to a high level, the transfer gate 305 closes and the transfer gate 307 opens. Therefore, the low level of the negative high-level value held at the node 314 is written to the node 316 by the inverter 306. Therefore,
The low level written to the node 316 is output to the divided clock output terminal 303. As described above, the divided clock signal can be changed to the low level at the rise of the clock signal after the input of the set signal.

When the set signal is input while the clock signal is at the high level, the node 314 is set to the low level by the N-channel MOS transistor 312. At this time, the node 316 is set to a high level by the P-channel MOS transistor 311. At this time, since the transfer gate 307 is open, writing to the node 316 is performed by the inverter 306, but the node 314 is changed to the N-channel MOS transistor 31.
Since the level of the clock signal is set to a level opposite to that of the clock signal 2, the writing by the inverter 306 and the charging by the P-channel MOS transistor 311 do not collide.

When the clock signal changes to the low level after the set signal changes from the high level to the low level, the transfer gate 305 opens and the transfer gate 3
07 closes. At this time, the output of the divided clock signal does not change, but the node 314 is rewritten to a high level by the inverters 308 and 309.

Thereafter, when the clock signal changes to the high level, the transfer gate 305 closes and the transfer gate 307 opens. Therefore, the low level of the high-level negative value held at the node 314 by the inverter 306 is written to the node 316. Therefore, a low level is written to the divided clock output terminal 303. As described above, the divided clock signal can be changed to the low level at the rise of the clock signal after the input of the set signal.

Also, while the set signal is at the high level,
When the clock signal changes from the high level to the low level, the node 314 becomes the N-channel MOS transistor 3
12, a high level is written.

When the clock signal changes from low level to high level after the set signal changes to low level, the transfer gate 305 closes and the transfer gate 307 opens. Therefore, the low level of the high-level negative value held at the node 314 by the inverter 306 is written to the node 316. Accordingly, a low level is output to the frequency-divided clock output terminal 303, and the frequency-divided clock signal can be changed to the low level at the rising edge of the clock signal after the input of the set signal.

As described above, when the set signal is input and the clock signal is at the high level, the node 314 is always discharged to the low level by the N-channel MOS transistor 312.
11 does not collide with charging to high level.
Therefore, the circuit can be initialized at an arbitrary timing.

[0164]

As is apparent from the above description, in the dynamic frequency divider with reset function of the present invention, the source terminal is connected to the first power supply terminal, and the drain terminal is connected to the output side of the second switch means. , A first node connected to a first node connecting the input side of the second inverter means and a gate terminal connected to the output side of the fifth inverter means for receiving a reset signal from the reset terminal. A MOS transistor, a source terminal connected to the second power supply terminal, a drain terminal connected to a second node connecting the output side of the fourth switch means and the input side of the fourth inverter means, and A first second terminal whose terminal is connected to the reset terminal;
A conductivity type MOS transistor, a source terminal is connected to the second clock input terminal, and a drain terminal is connected to a third node connecting the output side of the first switch means and the input side of the first inverter means. A second second conductivity type MOS transistor having a gate terminal connected to the reset terminal, a source terminal connected to the first clock input terminal,
A second terminal having a drain terminal connected to a fourth node connecting an output side of the third switch means and an input side of the third inverter means, and a gate terminal connected to an output side of the fifth inverter means; And a first conductivity type MOS transistor.

Therefore, when a reset signal is input from the reset terminal, the first node can be set to substantially the same level as the power supply level of the first power supply terminal by the first first conductivity type MOS transistor. . Further, the fourth node can be set to a level substantially equal to the power supply level of the second power supply terminal by the first second conductivity type MOS transistor. Further, the third node can be set to a level opposite to that of the clock signal from the first clock input terminal by the second second conductivity type MOS transistor. Further, the fourth node can be set to the same level as the clock signal by the second first conductivity type MOS transistor.

Therefore, the frequency-divided clock signal can be raised at the rising edge of the clock signal after the input of the reset signal from the reset terminal. Therefore, the circuit can be initialized at an arbitrary timing. In addition, since there is no path through which a through current flows at the time of initialization, an increase in power consumption during initialization does not occur.

In the dynamic frequency divider with reset function of the present invention, the source terminal is connected to the second power supply terminal, and the drain terminal is connected to the input side of the sixth switch means and the seventh terminal.
A third second conductivity type MOS transistor having a gate terminal connected to the reset terminal, a source terminal connected to the first clock terminal, and a drain connected to the fifth node connecting the output side of the inverter means. A terminal is connected to a sixth node connecting an output side of the fifth switch means and an input side of the sixth inverter means, and a gate terminal is connected to an output side of the ninth inverter means having a reset terminal connected to the input side. And a third first conductivity type MOS transistor connected thereto.

Therefore, when a reset signal is input from the reset terminal, the fifth node can be set to substantially the same level as the power supply level of the second power supply terminal by the third second conductivity type MOS transistor. . Further, the sixth node can be set to the same level as the clock signal output from the first clock input terminal by the third first conductivity type MOS transistor.

Therefore, the frequency-divided clock signal can be raised at the rising edge of the clock signal after the input of the reset signal from the reset terminal. Therefore, the circuit can be initialized at an arbitrary timing. In addition, since a path through which a through current flows does not occur at the time of initialization, an increase in power consumption at the time of initialization does not occur.

In the dynamic frequency divider with set function of the present invention, the source terminal is connected to the first power supply terminal,
A drain terminal is connected to a seventh node connecting the output side of the eighth switch means and the input side of the eleventh inverter means, and a gate terminal connects the set terminal to the input side.
A fourth first conductivity type MOS transistor connected to the output side of the inverter means, a source terminal connected to the second clock input terminal, and a drain terminal connected to the output side of the seventh switch means; A fourth second conductivity type MOS transistor is connected to an eighth node connecting the input side of the inverter means and has a gate terminal connected to the set terminal.

Therefore, when the set signal is input from the set terminal, the seventh node can be set to substantially the same level as the power supply level of the first power supply terminal by the fourth first conductivity type MOS transistor. . Further, the eighth node is set to the level opposite to the clock signal from the first clock input terminal by the fourth second conductivity type MOS transistor.

Therefore, the divided clock signal can fall at the rise of the clock signal after the input of the set signal from the set terminal. Therefore, the circuit can be initialized at an arbitrary timing. In addition, since a path through which a through current flows does not occur at the time of initialization, power consumption at the time of initialization does not increase.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a dynamic frequency divider with a reset function according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a simulation operation waveform according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a configuration of a dynamic frequency divider with a reset function according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a dynamic frequency divider with a set function according to an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration of a conventional dynamic frequency divider with a reset function.

FIG. 6 is a circuit diagram illustrating a configuration of a conventional dynamic frequency divider with a reset function.

FIG. 7 is a circuit diagram showing a configuration of a conventional dynamic frequency divider with a set function.

FIG. 8 is a diagram illustrating a problem of a conventional dynamic frequency divider with a reset function.

FIG. 9 is a diagram illustrating a simulation operation waveform of a conventional dynamic frequency divider with a reset function.

[Explanation of symbols]

101, 201, 301, 401, 501, 601 Clock input terminal 102, 202, 302, 402, 502, 602 Negative phase clock input terminal 103, 212, 403, 510 Reset terminal 104, 203, 303, 404, 503, 603 Divided clock output terminal 105, 405 Negative phase divided clock output terminal 106, 313, 406, 613 Higher power supply terminal 107, 213, 407, 511 Lower power supply terminal 108, 109, 116, 117, 204, 207, 3
05, 307, 408, 409, 416, 417, 50
4, 506, 605, 607 Transfer gates 112, 113, 120, 121, 127, 206, 2
08, 209, 210, 306, 308, 309, 31
0, 412, 420, 413, 421, 425, 50
5, 507, 508, 606, 608, 609, 610
Inverters 122, 126, 211, 312, 423, 426, 4
28,509 N-channel MOS transistors 123,125,205,311 422,427,4
29, 611 P-channel type MOS transistors 304, 604 Set terminals 110, 111, 114, 115, 118, 119, 1
24, 214, 215, 216, 314, 315, 31
6, 317, 410, 411, 414, 415, 41
8, 419, 424, 512, 513, 514, 61
4,615,616,617 nodes

Claims (6)

(57) [Claims] A first output stage for receiving a signal output to a second output terminal and outputting the signal to a first output terminal; and receiving a signal output to the first output terminal for receiving a signal output to the first output terminal. , A second output stage for outputting to the second output terminal is provided, wherein the first output stage includes a first switch unit, a first inverter unit, a second switch unit, Second inverter means are provided, and the second output stage is provided with third switch means, third inverter means, fourth switch means, and fourth inverter means, The first switch has an input connected to the output of the fourth inverter, the first inverter has an input connected to the output of the first switch, and an output connected to the output of the first switch. 2 is connected to the input side of the second switch means, and The inverter has an input connected to the output of the second switch, the output connected to the first output terminal, and the third switch has an input connected to the output of the second inverter. The third inverter means, the input side is connected to the output side of the third switch means, the output side is connected to the input side of the fourth switch means, and the fourth inverter means The input side is connected to the output side of the fourth switch means, the output side is connected to the second output terminal, the first switch means, the second switch means, and the third switch means And the fourth switch means is a dynamic frequency divider with a reset function connected to the first clock input terminal and the second clock input terminal, wherein the source terminal is connected to the first power supply terminal. Is connected to a first node connecting the drain terminal output of said second switching means and an input side of said second inverter means,
A first first conductivity type MOS transistor having a gate terminal connected to the output side of the fifth inverter means for inputting a reset signal from the reset terminal; a source terminal connected to the second power supply terminal; A second node connecting an output side of the fourth switch means and an input side of the fourth inverter means,
A first second terminal having a gate terminal connected to the reset terminal;
A conductive MOS transistor, and a source terminal connected to the second clock input terminal;
A second second conductive member having a drain terminal connected to a third node connecting an output side of the first switch means and an input side of the first inverter means, and a gate terminal connected to the reset terminal; A MOS transistor; a source terminal connected to the first clock input terminal;
A drain terminal is connected to a fourth node connecting an output side of the third switch means and an input side of the third inverter means, and a gate terminal is connected to an output side of the fifth inverter means. , A second first conductivity type MOS transistor, and a dynamic frequency divider with a reset function. 2. The switch means is a transfer gate. The first clock input terminal is connected to control terminals of the first switch means and the third switch means, and the control terminal of the first switch means and the third switch means is connected to an antiphase control terminal. Is connected to a second clock input terminal, the control terminal of the second switch means and the control terminal of the fourth switch means is connected to the second clock input terminal, and the opposite phase control terminal is The dynamic frequency divider with a reset function according to claim 1, wherein the first clock input terminal is connected. 3. A loop is formed by a fifth switch means, a sixth inverter means, a sixth switch means, a seventh inverter means, and an eighth inverter means, wherein the eighth inverter means An output terminal is connected to the output side of the fifth switch means. The input side of the fifth switch means is connected to the output side of the eighth inverter means. The sixth inverter means has an input side of the fifth switch means. An output side is connected, an output side is connected to an input side of the sixth switch means, and the seventh inverter means has an input side connected to the sixth switch means, and an output side is connected to the eighth inverter means. A dynamic circuit with a reset function connected to an input side, wherein the fifth switch means and the sixth switch means are connected to a first clock input terminal and a second clock input terminal. A frequency divider, wherein a source terminal is connected to a second power supply terminal, and a drain terminal is connected to a fifth node connecting an input side of the sixth switch means and an output side of the seventh inverter means. A third second conductivity type MOS transistor having a gate terminal connected to the reset terminal, a source terminal connected to the first clock terminal, and a drain terminal connected to the output side of the fifth switch means. Sixth
A third first conductivity type MOS transistor connected to a sixth node connecting the input side of the inverter means, and a gate terminal connected to the output side of the ninth inverter means having a reset terminal connected to the input side; A dynamic frequency divider with a reset function, comprising: 4. The switch means is a transgate, the control terminal of the fifth switch means is connected to the first clock input terminal, and the negative-phase control terminal is connected to the second clock. An input terminal is connected, a control terminal of the sixth switch means is connected to the second clock input terminal, and an anti-phase control terminal is connected to the first clock input terminal. The dynamic frequency divider with a reset function according to claim 3. 5. A loop is formed by a seventh switch means, a tenth inverter means, an eighth switch means, an eleventh inverter means, and a twelfth inverter means, wherein the twelfth inverter means An output terminal is connected to an output side of the means, the seventh switch means has an input side connected to the output side of the twelfth inverter means, and the tenth inverter means has an input side connected to the seventh switch means. And the output side is connected to the input side of the eighth switch means. The eleventh inverter means has an input side connected to the output side of the eighth switch means, and an output side connected to the twelfth switch means. The seventh switch means and the eighth switch means are connected to a first clock input terminal and a second clock input terminal. A frequency divider having a set function, wherein a source terminal is connected to a first power supply terminal, and a drain terminal connects an output side of the eighth switch means and an input side of the eleventh inverter means. Connected to node 7
A fourth first conductivity type M having a gate terminal connected to the output side of the thirteenth inverter means having the set terminal connected to the input side.
An OS transistor and a source terminal connected to the second clock input terminal;
A fourth second conductive member having a drain terminal connected to an eighth node connecting an output side of the seventh switch means and an input side of the tenth inverter means, and a gate terminal connected to the set terminal; A dynamic frequency divider with a set function, comprising: a MOS transistor; 6. The switch means is a transfer gate. The control terminal of the seventh switch means is connected to the first clock input terminal, and the reverse phase control terminal is connected to the second clock. An input terminal is connected, a control terminal of the eighth switch means is connected to the second clock input terminal, and an anti-phase control terminal is connected to the first clock input terminal. 6. The dynamic frequency divider with a set function according to claim 5, wherein: