JPH0159773B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparator made of CMOS (complementary insulated gate field effect transistor).

This type of comparator was constructed, for example, as shown in FIG. That is, 11 is the first power supply terminal to which the power supply V _DD is connected, 12 is the second power supply terminal which is grounded in this example, and 13 is the reference voltage.
Reference input terminal to which V _R is applied, 14 is comparison input
A comparison input terminal to which V _I is applied, 15 is a differential amplifier circuit, which includes a differential pair of N-channel transistors T ₁ and T ₂ , an N-channel constant current source transistor T ₃ , and a P-channel load transistor. T ₄ and T ₅ are connected as shown,
16 is a CMOS inverter, and 17 is a comparison output terminal.

In the above comparator, when the input comparison voltage V _I is higher than the reference voltage _VR , the drain of the transistor T ₂ is almost close to the ground potential (“0” level), so the output of the inverter 16 is the power supply voltage (“1” level). ”
level). Conversely, when the input comparison voltage V _I is lower than the reference voltage V _R , the drain of the transistor T ₁ is close to the "0" level, so the transistor T ₅ is turned on and its drain becomes the "1" level. Therefore, the output of inverter 16 is “0”
become the level.

By the way, since the differential amplifier circuit 15 basically operates as an analog circuit, it has the disadvantage that it cannot take advantage of the low power consumption characteristic of a CMOS circuit. Further, although it is possible to obtain the desired characteristics of the differential amplifier circuit 15 by precisely designing the elements used and controlling the manufacturing process, the characteristics are very sensitive to variations in the elements, and
A disadvantage of LSI (Large Scale Integration) was that it took up a large area on the chip.

In order to eliminate these drawbacks, by using a dynamically driven CMOS comparison circuit,
It has low power consumption and easy element design.
A comparator as shown in Figure 2, which is suitable for LSI implementation, has been considered.

That is, in FIG. 2, 21 is a comparison circuit;
22 and 23 are two-input NOR gates, and 24 and 25 are inverters, each made of CMOS. The NOR gates 22 and 23 are connected to form an R-S flip-flop 26, and _C1 to _C4 are capacitors, but when the circuit in Figure 2 is integrated into an IC, stray capacitances are used. It's okay.

In the comparison circuit 21, T ₁ to _{T 4} are N-channel transistors, T ₅ and T ₆ are P-channel transistors, and the transistors T ₅ ,
The source of T ₆ is connected to the first power supply terminal 31 (to which the power supply voltage V _DD is applied), and the gate is connected to the clock input terminal 32 . The above transistor
The drains of the transistors T ₁ and T 2 are connected to the drains of T ₅ and T ₆ , and the gates of the transistors T ₁ and _{T 2 are} connected to the reference input terminal 27 (to which the reference voltage V _R is applied). ), and is connected to the comparison input terminal 28 (to which the comparison voltage V _I is applied). The sources of the transistors T ₁ and T ₂ are connected to the second power supply terminal 29 (grounded in this example) via the drain-source paths of the transistors T ₃ and T ₄ , respectively. The gates of T ₃ and T ₄ are connected to the clock input terminal 2.
Connected to 3.

The drain interconnection point (node) A of the transistors T ₅ and T ₁ and the transistors T ₆ and T ₂
The drain interconnection point (node) B of the flip-flop 26 is connected to the reset input terminal R and the set input terminal S of the flip-flop 26, and these input terminals R and S are respectively grounded via capacitors C ₁ and C ₂ . ing.
Further, the output end and the output end Q of the flip-flop 26 are respectively grounded via capacitors C ₃ and C ₄ , and the output end Q is connected to a comparison output terminal 30 via inverters 24 and 25 .

Next, the operation of the above configuration will be explained with reference to FIG. Assume that a clock pulse φ as shown in FIG. 3 is applied to the clock input terminal 32, and when the comparison voltage V _I changes from a high value to a low value with respect to the reference voltage V _R as shown in FIG. Consider.

(a) During the period when the clock φ is at low level (“0” level), the transistors T ₅ and T ₆
is on, transistors T ₃ and T ₄ are off,
Nodes A and B are connected to the transistor from the power supply terminal 31.
Power supply voltage is precharged through T ₁ and T ₂
V _DD (“1” level), and the capacitor
C ₁ and C ₂ are charged. Therefore, the NOR gates 22 and 23 of the flip-flop 26 each output a "0" level, the output terminal Q becomes a "0" level as shown in FIG. 3, and the comparison output V ₀ of the comparison output terminal 30 is at the "0" level as shown in FIG.

(b) During the period when V _I > V _R and the clock φ is at high level (“1” level), transistors T ₅ and T ₆ are off, transistors T ₃ and T ₄ are on, and transistors T ₁ and T ₂ , a discharge current flows from the capacitors C ₁ and C ₂ (charged during the period as described above) according to V _R and _VI . Note that the transistors T ₃ and T ₄ and the transistors T ₁ and T ₂ are designed in advance so that the dimensions (preferably, the direction in which the current flows) are exactly the same, and the capacitors C ₁ and C ₂ are
If capacitors C ₃ and C ₄ are designed so that their capacitances are strictly the same, the discharge voltage waveforms at nodes A and B will be equal when V _I = V _R , but
Under the above condition of V _I >V _R , the discharge speed of node B is faster than that of node A, as shown in FIG. Therefore, the voltage at node B reaches the threshold voltage V _TH of the flip-flop 26 earlier than the voltage at node A, so that the output terminal Q of the flip-flop 26 becomes the "1" level due to the "0" input at the set input terminal S. Therefore, the output terminal is “0” regardless of the input to the reset input terminal R (voltage at node A).
become the level. Therefore, at this time, a comparison output at the "1" level is obtained at the comparison output terminal 30.

(c) During the period when V _I < V _R and the clock φ is at a high level, the same operation as in (b) above is performed, but in this case, the transistor T ₁
A discharge current larger than that of transistor T ₂ flows into the node A, and the discharge speed of the node A is faster than that of the node B. Therefore, the output terminal of the flip-flop 26 becomes "1" level due to the "0" input at the reset input terminal R, and therefore the output terminal Q becomes "0" level.
level, and a comparison output of "0" level is obtained at the comparison output terminal 30.

According to the comparator of FIG. 2 as described above, since the comparator circuit 21 is dynamically driven by the clock pulse φ, no through current flows between the power supply terminal 31 and the ground terminal, and a DC current flows through the flip-flop 26. flows during a short period of time (Δt ₁ , Δt ₂ in Fig. 3) from when the voltage at nodes A and B, which has the faster discharge rate, reaches the threshold of the flip-flop.
Since C ₁ and C ₂ are usually about 1 pF and the charge is small, the comparator has low power consumption without losing the characteristics of a CMOS circuit.

Moreover, as mentioned above, the transistors T ₁ and T ₂
It is easy to design transistors T ₃ and T ₄ equally in integrated circuits.

In the comparator shown in FIG. 2 described above, the range in which the transistors T ₁ and T ₂ do not cut off, that is, the conditions under which current flows through the transistors T ₁ and T ₂ are as follows:
When the threshold voltage of an N-channel transistor is expressed as V _THN , it is V _DD to V _THN . In other words, the voltage range that can be compared is limited to V _DD to V _THN . For example, if V _THN = 1.0V, the transistors T ₁ and T ₂ will not turn on at a voltage of 1.0V or less, and therefore cannot be compared.

The present invention was made in view of the above circumstances, and
The first comparator has a comparable voltage range of V _DD to V _THN , and the first comparator has a comparable voltage range of (V _DD − | V _THP
|) ~0V second comparator, and by selecting and deriving a normal comparison output from either one of the comparators, the voltage range that can be compared is set to 0~V _DD
This provides a comparator that can be expanded to a range of .

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 4, 41 is a first comparator whose voltage range can be compared from V _DD to V _THN . It consists of an R-S flip-flop 26 and capacitors _C1 to _C4 . A second comparator 42 has a comparable voltage range of (V _DD -|V _THP |) to 0V. Here, V _THP is the threshold voltage of the P channel transistor. This second comparator 42 is
The N-channel transistors T ₁ and T ₂ of the first CMOS comparator circuit 21 are replaced with P-channel transistors T ₁ ′ and T ₂ ′, and a second CMOS comparator circuit 21 uses a clock pulse having an opposite phase to the clock pulse φ.
It consists of a CMOS comparison circuit 21', a second R-S flip-flop 26' using NAND gates 22' and 23' in place of the NOR gates 22 and 23 of the first flip-flop 26, and capacitors _C1 ' to _C4 '. . That is, the second CMOS comparison circuit 2
1′, T ₁ ′, T ₂ ′, T ₅ ′, T ₆ ′ are P-channel transistors, T ₃ ′, T ₄ ′ are N-channel transistors, and T ₅ ′, T ₆ ′ are transistors whose sources are 1 power supply terminal 31, and its gate is connected to a clock input terminal 32' (to which a clock pulse is applied). The sources of the transistors T ₁ ′ and T ₂ ′ are connected to the drains of the transistors T ₅ ′ and T ₆ ′, and the gates of the transistors T ₁ ′ and T ₂ ′ are respectively connected to the reference input terminal. 27 and comparison input terminal 28. The above transistor
Each drain of T ₁ ′ and T ₂ ′ is connected to a corresponding transistor.
The transistors T ₃ ′, T ₄ ′ are connected to the second power supply terminal 29 through drain-source paths, and the transistors T ₃ ′,
The gate of T ₄ ' is connected to the clock input terminal 32'. And the transistor T ₁ ′,
Each drain of T ₂ ' (nodes A', B') corresponds to the reset R of the second R-S flip-flop 26'.
input terminal and the SET S input terminal.

On the other hand, the pair of output terminals of the first comparator 41, that is, the Q output terminal and the output terminal of the first R-S flip-flop 26, are connected to each input terminal of a two-input NOR gate 43, and the output terminal of this NOR gate 43 is connected to one input terminal of the inverter 44 and the AND gate 45. The output terminal of the inverter 44 and the Q output terminal are connected to respective input terminals of an AND gate 46. The second comparator 42 is connected to the other input terminal of the AND gate 45.
The output terminal of the flip-flop 26' is connected via the inverter 50, and the output terminal of the flip-flop 26' is connected to the AND gate 45.
and 46 are connected to the input end of a NOR gate 47, and the output end of this NOR gate 47 is connected to a comparison output terminal 49 via an inverter 48.

Note that the Noah gate 43, the inverter 44,
A switching selection circuit 50 is formed by the AND gates 45 and 46, the NOR gate 47, and the inverter 48.

Therefore, in the above comparator, the first comparator 4
The operation of the first comparator 42 is as shown in FIG. 5 in the same manner as described above with reference to FIG. 5 as shown in Figure 5.

In other words, (a) During the period when the clock pulse is at high level (“1” level), the transistor
T ₅ ′, T ₆ ′ are off, but transistors T ₃ ′,
T ₇ ′ is turned on, and the charges previously stored in capacitors C ₁ ′ and C ₂ ′ are discharged. Therefore, at this time, the output terminal Q of the flip-flop 26'
Both become "1".

(b) During the period when the clock pulse is at low level (“0” level), the transistor
T ₅ ′, T ₆ ′ are on, transistors T ₃ ′, T ₄ ′ are off, transistors T ₁ ′, T ₂ ′ are above voltages V _R , V _I
The resistance corresponds to the size of . Therefore, during the period of V _R <V _I , the charging current flowing from the power supply terminal 31 through the transistors T ₅ ′ and T ₁ ′ to the capacitor C ₁ ′ flows from the power supply terminal 31 through the transistors T ₆ ′ and T ₂ The charging current flowing through capacitor C ₂ ' through ' is larger, and node A' reaches the threshold voltage V _TH of flip-flop 26' earlier than node B', and flip-flop 26' reaches "1" at reset input terminal R. The output terminal becomes "0" due to input.

On the other hand, during the period ' when V _R > V _I , conversely to the above, capacitor C ₂ ' charges faster than capacitor C ₁ ', and node B' charges faster than node A'. The threshold value V _TH of flip-flop 26' is reached;
The flip-flop 26' has a set input S at "1".
The output terminal Q becomes "0" due to the input, and the output terminal remains "1".

Now, when V _I and _VR are between V _THN and V _DD , the Q output of the first comparator 41 is "1" when V _I > V _R , and when V _I <
The output becomes “1” when it is _VR . Then, the switching selection circuit 50 determines that when the Q output is "1", the output of the NOR gate 43 is "0", and the output of the AND gate 45 is "0".
The output of the inverter 44 is "0", the output of the inverter 44 is "1",
AND gate 46 output is “1”, NOR gate 4
The output of inverter 7 is “0” and the output of inverter 48 is “1”
When the output is "1", the output of the NOR gate 43 is "0", the output of the inverter 44 is "1", the outputs of the AND gates 45 and 46 are "0", the output of the NOR gate 47 is "1", The output of the inverter 48 becomes "0". That is, the output level of the comparison output terminal 49 is determined according to "1" or "0" of the Q output of the first comparator 41. At this time,
One input of the AND gate 45 is "0", and the output from the second comparator 42 via the inverter 50 is inhibited.

On the other hand, when V _I and V _R are between 0 and V _THN , for example, when V _THN = +1.0V, V _R = +0.5V, V _I =0V or +0.7V, the first comparator 41 Transistors T ₁ and T ₂ are cut off, and nodes A and B are “1”
The level remains, and both Q output and output are “0”
become. Therefore, in the switching selection circuit 50, the output of the NOR gate 43, that is, one input of the AND gate 45 becomes "1", but the other AND gate 46 becomes disabled. In this case, the operating range of the second comparator 42 is 0 to (V _DD −
|V _THP |), and its output is “0” when V _I > V _R , and “1” when V _I < V _R , so this output is inverted by the inverter 50 and converted to the above AND. The signal passes through the gate 45, then passes through the NOR gate 47 and the inverter 48, and is led out to the comparison output terminal 49.

According to the above-mentioned comparator, two CMOS comparators whose operating ranges partially overlap are used, and it is determined whether or not the comparator is operating within a normal operating range based on the output of one of the comparators. If it is normal, that output is selected, and if it is not normal, the output of the other comparator is selected and derived. Therefore, the operating range can be expanded from the upper end of one operating range to the lower end of the other operating range.

Note that in the above embodiment, the switching selection circuit 5
0 selected the output according to the detection result of the two output states of the first R-S flip-flop 26.
In place of this, a second R-S flip-flop 2
The circuit connection may be changed so that the output is selected according to the detection result of the two output states of 6'.

As described above, the present invention can provide a comparator that can expand the voltage range that can be compared from the ground potential to the power supply voltage.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional comparator, Fig. 2 is a circuit diagram showing a conventionally considered comparator, Fig. 3 is a waveform diagram shown to explain the operation of Fig. 2, and Fig. 4 5 is a circuit diagram showing one embodiment of the comparator according to the present invention, and FIG. 5 is a waveform diagram shown for explaining the operation of FIG. 4. 21, 21'...comparison circuit, 26, 26'...R
-S flip-flop, 29, 31...power terminal, 50...switching selection circuit, _T1 ~ _T6 , _T1 '~
T ₆ ′...Transistor.

Claims (1)

[Claims] 1 P with one end connected to the first power terminal
N-channel transistors T ₃ , T ₄ having one end connected to the channel transistors T ₅ , T ₆ and the second power supply terminal, and between the other ends of the transistors T ₅ , T ₃ and each of T ₆ , T ₄ N-channel transistors T ₁ and T ₂ are respectively inserted between the other ends and a reference voltage V _R and a comparison voltage V _I are applied to the respective gates,
A first CMOS (complementary insulated gate field effect transistor) comparison circuit in which a clock pulse φ is applied to each gate of the transistors T ₅ , T ₆ , T ₃ , T ₄ , and the transistors T ₅ , T of this comparison circuit. ₆ to which a pair of input ends are connected corresponding to each other end of the first
P-channel transistors _T5 ', _T6 ' each having one end connected to the first power supply terminal, and an N-channel transistor having one end each connected to the second power supply terminal.
The transistors T ₃ ′, T ₄ ′ and the transistors T ₅ ′, T ₃ ′ and the other ends of the transistors T ₆ ′, T ₄ ′ are inserted correspondingly to each other, respectively. The _clock pulse is applied to each _gate of the transistors _{T 5 ′} , T ₆ ′, T _{3 ′} , and T ₄ ′. a second CMOS comparator circuit to which a clock pulse having an opposite phase to φ is applied; and a second CMOS comparator circuit to which a pair of input terminals are connected corresponding to the other terminals of the transistors T ₃ ' and T ₄ ' of this comparator circuit. detects the output state of the R-S flip-flop and the second flip-flop or the first flip-flop, and selects the output of the second flip-flop or the output of the first flip-flop according to the output state. A comparator comprising a switching selection circuit for deriving the .