JP2919187B2 - Substrate potential supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a potential supply circuit, and more particularly to a substrate potential supply circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional substrate potential supply circuit includes a CMOS inverter 1, PMOS transistors Q1 to Q4, and capacitors C1 and C2. It operates in response to the input of the low-level pulse signal a.

In FIG. 4 showing the operation of each section in FIG. 3, when the input signal a transitions from a low level to a high level, the potential at the node F will rise to a high level due to the movement of the charge of the capacitor C2. However, when the potential of the node F becomes higher than the threshold voltage VT4 of the PMOS transistor Q4, the PMOS transistor Q4 is turned on, and the potential of the node F becomes higher than the threshold voltage VT4 of the PMOS transistor Q4. There is no.

Next, when the input signal "a" transitions from the high level to the low level, the potential of the capacitor C2 moves, and the potential of the node F drops to a negative level.
The transistor Q2 is turned on. At this time, since the output signal C of the CMOS inverter 1 changes from low level to high level, the potential of the node D tries to rise to high level due to the movement of the charge of the capacitor C1, but the PMOS transistor Q2 Is on,
This PMOS transistor Q2 lowers the voltage to the ground potential level.

When the input signal a transitions from low level to high level again, the potential at the node F rises by the amount of movement of the electric charge of the capacitor C2.
Changes from the high level to the low level, the level of the node D decreases from the ground potential level to the negative potential level due to the movement of the charge of the capacitor C1, and the PMOS transistor Q3 turns on. , The potential of node F attains the ground potential level, and PMOS transistor Q2 is turned on. At this time, since the potential of the node D is at the negative potential level, the PMOS transistor Q1 is turned on, and the substrate potential VBB is pulled down to the level of the node D and becomes a negative potential.

The nodes C, D, and F in this series of operations are as shown in FIG. 5. By repeating this series of operations, the substrate potential VBB becomes higher than the potential of the node D by the threshold voltage of the PMOS transistor Q1. The voltage drops to a voltage higher by VT1 and a negative potential can be supplied to the substrate.

[0007]

In the conventional substrate potential supply circuit, when the potential of the node D is to be set to a negative level, the potential of the node D becomes the level of the threshold voltage VT3 of the PMOS transistor Q3. Until now, the PMOS transistor Q2 is in the ON state, and an unnecessary current flows from the ground potential to the node D, and there is a problem that the ability to set the substrate potential to a negative potential is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a substrate potential supply circuit which solves the above-mentioned problem and does not reduce the ability to set a substrate potential to a negative potential.

[0009]

According to the present invention, there is provided a substrate potential supply circuit comprising: a circuit which receives a pulse signal which goes high or low as an input signal and outputs an inverted signal;
A gate and a drain (or a source, hereinafter the same) are both connected to the ground potential, and the inverted signal is inputted to a source (or a drain and the like hereinafter) via a first capacitor.
And a second PMOS transistor having a drain connected to the ground potential, the inverted signal being input to the source via the first capacitor, the input signal being input, and the inverted signal being low. When the level becomes high, a circuit for outputting a pulse signal which is always high, a gate and a drain are connected, and both are connected to the gate of the second PMOS transistor, and the inverted signal becomes low.・ When you reach the level, be sure to
The pulse signal at the level is input to the gate via the second capacitor, and a third PMOS transistor, which outputs a predetermined substrate potential from the source, and the source is the drain and the drain of the third PMOS transistor. A fourth PMOS transistor connected to the gate, the drain connected to the ground potential, and the inverted signal input to the gate via the first capacitor.

[0010]

FIG. 1 is a circuit diagram showing a substrate potential supply circuit according to a first embodiment of the present invention. In FIG. 1, a substrate potential supply circuit according to the present embodiment includes a CMOS inverter 1 that outputs an inverted output signal B of an input signal a, and a CMOS inverter 1 that outputs the inverted output signal B.
A two-input NAND gate 2 (hereinafter referred to as NAND gate 2) having one input as an input, and a two-input NAND gate 3 (hereinafter NAND) having an input signal a as one of two inputs and receiving the output of the NAND gate 2 as the other input Gate 3),
The output of the NAND gate 3 is used as the other input of the NAND gate 2, the capacitor C 1 for performing charge transfer by the output signal C of the NAND gate 2, and the output signal E of the NAND gate 3.
And the PMOS transistor Q4 and the node F, which limit the rise of the potential of the node F due to the movement of the electric charge of the capacitor C2, are input to the gate, and the drain is connected to the ground potential. A PMOS transistor Q2 which uses the potential of the node D as a ground potential, and a PMOS which operates by the potential of the node D to generate a substrate potential VBB
Transistor Q1, transistor Q1 and transistor Q
2 is provided with a PMOS transistor Q3 for preventing the transistors 2 from turning on at the same time.

The operation of the substrate potential supply circuit according to the present embodiment is as follows. When the input signal a changes from low level to high level as shown in FIG. 4, the output signal C of the NAND gate 2 changes from low level to high level. Level, and the output signal E of the NAND gate 3 goes high due to the transition of the output signal C.
Transition from level to low level. At this time, the potential of the node F, which is held down by the threshold voltage VT4 of the transistor Q4, changes from the high level to the low level. , The transistor Q2 is turned on,
Node D is at the ground potential level.

Next, when the input signal a changes from the high level to the low level, first, the output signal E of the NAND gate 3 is output.
Transitions from the low level to the high level, and the capacitance C2
Due to the charge transfer, the node F rises and the transistor Q
2 is turned off. At this time, the node D transitions from the high level to the low level in response to the transition of the output signal C of the NAND gate 2 from the low level to the high level of the output signal E of the NAND gate 3, and the capacitance C1 The electric charge moves from the ground potential level to the negative potential due to the transfer of the charge, the transistor Q3 is turned on, the node F becomes the ground potential level, and the negative potential at the node D becomes higher than the substrate potential VBB by the threshold value of the transistor Q1. When the voltage becomes a negative level equal to or higher than the voltage VT1, the transistor Q1 is turned on, and the substrate potential VBB is pulled down to the level of the node D, and becomes higher than the level of the node D by the threshold voltage VT1 of the transistor Q1.

Therefore, when the potential at the node D is going to be a negative potential, by turning off the transistor Q2 first, unnecessary current can be prevented from flowing into the node D from the ground potential. The waveforms of each node, output signal, and input signal in this series of operations are as shown in FIG. 4. By repeating this series of operations, a stable substrate potential can be supplied.

FIG. 2 is a circuit diagram showing a substrate potential supply circuit according to a second embodiment of the present invention. 2, a substrate potential supply circuit according to the present embodiment includes a CMOS inverter 1 that outputs an inverted output signal B of an input signal a, and a two-input NOR gate 4 (hereinafter referred to as NOR) that receives an input signal a as one of two inputs. A two-input NOR gate 5 (hereinafter referred to as a NOR gate 5) having the inverted output signal B as one of two inputs and the output of the NOR gate 4 as the other input, and a NOR gate 5
Is the other input of the NOR gate 4 and
CMOS that outputs inverted signal C of the output signal of gate 4
Inverters 6, CMOS inverters 7 that output inverted output signal E of the output signal of NOR gate 5, and capacitors C1 and C that transfer charges to output signal C of CMOS inverter 6.
A capacitor C2 that moves the electric charge by the output signal E of the MOS inverter 7, a PMOS transistor Q4 that limits a rise in the potential of the node F due to the movement of the electric charge of the capacitor C2, and a node F.
And the drain is connected to the ground potential, and the potential of the node D is set to the ground potential level in the ON state.
Operated by the potential of the MOS transistor Q2 and the node D,
PMOS transistor Q for generating substrate potential VBB
1, a PMOS transistor Q3 for preventing the transistor Q1 and the transistor Q2 from turning on at the same time.

The operation of the substrate potential supply circuit according to the present embodiment is such that when the input signal a changes from a low level to a high level,
The output of the NOR gate 4 changes from the high level to the low level, and after the output of the NOR gate 4 changes,
The output of the NOR gate 5 changes from a low level to a high level. At this time, the node F held down by the threshold voltage VT4 of the transistor Q4 shifts the inverted output signal E of the output of the NOR gate 5 from the high level to the low level. The potential drops.

Next, the input signal a changes from high level to low level.
When the level becomes the level, the output of the NOR gate 5 first transitions from the high level to the low level, and the inverted output signal E of the output of the NOR gate 5 transitions from the low level to the high level. At this time, the output of the NOR gate 5 undergoes a transition, and the output of the NOR gate 4 changes from low to high.
Level, and the inverted output signal C of the output of the NOR gate 4 changes from the high level to the low level.

As described above, the response of the nodes C and E of FIG. 2 to the input signal a is the same as the output signal C and the node E of FIG. 1 of the first embodiment. The circuit configuration after the node E includes the output signal C and the node E shown in FIG.
Since the circuit configuration is the same as that described below, in FIG. 2 as well as in FIG. 1, it is possible to prevent a decrease in performance and supply a stable substrate potential.

[0018]

As described above, according to the present invention, the gate potential of a PMOS transistor that pulls the substrate potential to a negative potential, the gate potential of a PMOS transistor that does not short-circuit the substrate potential and the ground point, and the substrate potential are reduced. P pulled to a negative potential
When the potential of the gate of the MOS transistor is a negative potential, a circuit for controlling an unnecessary current from flowing from the ground point is newly added to prevent the performance of the substrate potential supply circuit from deteriorating. There is an effect that a potential can be supplied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a substrate potential supply circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional substrate potential supply circuit.

FIG. 4 is a signal waveform diagram of each section of the embodiment shown in FIG.

5 is a signal waveform diagram of each section of the conventional circuit shown in FIG.

[Explanation of symbols]

 a Input signal B, C Output signal 1, 6, 7 CMOS inverter 2, 3 2-input NAND gate 4, 5 2-input NOR gate C1, C2 Capacitance Q1, Q2, Q3, Q4 PMOS transistor D, E, F Node VBB substrate potential

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 3/07 G11C 11/407 G11C 11/413

Claims (3)

(57) [Claims] 1. A circuit in which a pulse wave having a high level or a low level is an input signal and an inverted signal of the input signal is output, and a gate and a drain (or a source) are both connected to a ground potential; A signal is input to a source (or a drain) via a first capacitor.
An OS transistor, a drain (or source) connected to the ground potential, a second PMOS transistor to which the inverted signal is input to the source (or drain) via the first capacitor, and the input signal as an input A circuit for outputting a pulse signal that is always at a high level before the inverted signal transitions to a low level, and a gate and a drain (or source) are connected to each other, and both the second PM
The pulse signal that is connected to the gate of the OS transistor and that is always at the high level before the inverted signal transitions to the low level is input to the gate via the second capacitor, and the source (or A third PMOS transistor that outputs a predetermined substrate potential from the drain, a source (or drain) connected to the drain (or source) and the gate of the third PMOS transistor, and a drain (or source) connected to the ground potential And a fourth PMOS transistor connected to the gate of the first transistor and receiving the inverted signal via a gate of the first capacitor. 2. The substrate potential supply circuit according to claim 1, wherein the circuit that outputs the inverted signal includes one inverter and two NAND gates. 3. The circuit for outputting the inverted signal comprises three inverters and two NOR gates.
3. The substrate potential supply circuit according to claim 1.