JPH06187785A - Atd circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements and to reduce required pattern area in an ATD circuit provided in a semiconductor integrated circuit such as a SRAM and the like. CONSTITUTION:A resistance element R21, a P channel transistor QP21 and a N channel transistor QN21 are connected in series between power supply voltage Vdd and ground voltage Vss in this order. An address input signal is impressed to gates of the P channel transistor QP21 and the N channel transistor QN21 through an address input circuit, which is composed of a NOR circuit 22 and an inverter 23 connected to an address terminal 21. An ATD signal is taken out from a connecting point of the resistance element R21 and a source of the P channel transistor QP21 via an inverter 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATD circuit included in a semiconductor integrated circuit such as SRAM, and more particularly to an ATD circuit having a reduced number of elements.

[0002]

2. Description of the Related Art ATD (Address Transi)
of the SRAM (Sta)
tic Random Access Memory)
Is a circuit which is provided at a plurality of address input terminals of a semiconductor integrated circuit such as, and detects the change when an address input signal applied to the address input terminal changes, and generates an ATD signal as a pulse signal.

FIG. 3 is a circuit diagram showing a conventional ATD circuit. In the drawing, (1) is an address input terminal, (2) is a NOR circuit in which one input is connected to the address input terminal and the other input is connected to the chip selection signal * CS,
Chip selection signal * CS is low level (ground voltage Vss)
The address data input becomes enable. (3) and (4) are inverters for waveform shaping, and the NOR circuit (2) and the inverters (3) and (4) form an address input circuit. (5), (6), and (7) are inverters that constitute the delay circuit (13),
(8) is an inverter for inverting the output of the inverter (4), and (9), (10) and (11) are inverters for constructing the delay circuit (14). And Q
_P1 is a P-channel transistor whose source is connected to the power supply voltage Vdd and whose gate is connected to the ground voltage Vss in a normally-on state. Q _N1 and Q _N2 are the drain of the P-channel transistor Q _P1 and the ground voltage. An N-channel transistor connected in series between Vss, the output of the inverter (4) is connected to the gate of the N-channel transistor Q _N1 , and a delay circuit is connected to the gate of the N-channel transistor Q _N2. The output of the inverter (7) which is the output of (13) is connected. Q _N3 and Q _N4 are N-channel transistors connected in series between the drain of the P-channel transistor Q _P1 and the ground voltage Vss, and the output of the inverter (8) is output to the gate of the N-channel transistor Q _N3. Is connected to the N-channel transistor Q
The output of the delay circuit (14) is an inverter for the gate of _N4.
(11) output is connected. The ATD signal is connected to the drain of the P-channel transistor Q _{P1 and} the drains of the N-channel transistors Q _N1 and Q _N3.
It is output from the terminal (a) via the inverter (12).

Next, the operation of the above-mentioned conventional circuit will be described with reference to FIGS. FIG. 4 is an operation timing chart of the circuit shown in FIG. First, the address input signal applied to the address input terminal (1) is at a low level (ground voltage V
In the case of ss), the output of the inverter (4) becomes high level (power supply voltage Vdd) and the N-channel transistor Q
_{Although N1} is on, the output of the inverter (7) is low level, so the N-channel transistor Q _N2 is off. Further, the output of the inverter (8) is at the low level and the N-channel transistor Q _N3 is off, and the output of the inverter (11) is at the high level and the N-channel transistor Q _N4 is on. Therefore, since the N-channel transistors Q _N2 and Q _N3 are off, the node (a)
Is cut off from the ground voltage Vss and becomes a high level by the P channel transistor Q _P1 . In response to this, the inverter (12) outputs a low level ATD signal.

When the address input signal rises from low level to high level, the inverter (4)
Output falls to low level, and in response to this, the output of the inverter (8) rises to high level and the N-channel transistor Q _N3 is turned on. On the other hand, the inverter (8)
Is output to the delay circuit (14) and is delayed via the inverters (9), (10) and (11) so that the output of the inverter (11) falls to low level and the N-channel transistor Q _N4. Turns off. Therefore, the N-channel transistors Q _N3 and Q _N4 are turned on at the same time from when the output of the inverter (8) rises to the high level until the output of the inverter (11) falls to the low level. The output voltage of the inverter (12) rises to the high level in response to the switching voltage * V _{T of} the inverter (12) being pulled to the low level. When the N-channel transistor Q _N4 is turned off, the node (a) is cut off from the ground voltage Vss because the N-channel transistor Q _N1 is also turned off, and the node (a) is set to the high level by the P-channel transistor Q _P1 . The switching voltage * V _{T of the} rising inverter (12) is exceeded, and in response to this, the output of the inverter (12) falls to a low level. As a result, the inverter (12) outputs an ATD signal which is a high level pulse.

Then, the address input signal is at a high level.
In steady state, N-channel transistor Q_N1Over
And Q_N4The off state of the
The output of (12) maintains the low-level ATD signal.
Next, the address input signal changes from high level to low level.
When it falls, the output of the inverter (4) is high level.
N-channel transistor Q rising to the bell _N1Is on
To do. On the other hand, the output of the inverter (4) is the delay circuit (13).
Input to inverters (5) and (6) and (7)
The output of the inverter (7) is low level after being delayed through
Falling to N-channel transistor Q_N2Turns off
It Therefore, the output of the inverter (4) goes high.
Then the inverter (7) falls to the low level.
N channel transistor Q between_N1And Q_N2At the same time
When turned on, node (a) is pulled to low level.
Built-in, switching voltage * V of inverter (12)
_TBelow, the output of the inverter (12) in response to this
Rises to a high level. And N channel Tran
Dista Q_N2Is off, N-channel
Langista Q_N3Node (a) is grounded because it is also off
It is cut off from the voltage Vss and the P-channel transistor Q
_P1Rises to high level by inverter (12)
Switching voltage * V_TThat is all.
The output of the inverter (12) falls to low level. This
This causes a high level pulse from the inverter (12).
Is output.

In this way, the ATD signal that becomes a high level pulse is output only when the address input signal rises from a low level to a high level or when it falls from a high level to a low level.

[0008]

By the way, in recent years SRA
In semiconductor integrated circuits such as M, the number of address input terminals tends to increase as the memory capacity increases. ATD
The circuit is provided for each address input terminal. In the above-described conventional ATD circuit, the number of elements required for the circuit configuration is large, and therefore the peripheral circuit increases as the number of address input terminals increases. There is a problem that the pattern area required to form the chip increases, which hinders the reduction of the chip size.

The present invention has been made in view of the above-mentioned problems, and realizes a function equivalent to that of a conventional ATD circuit,
Moreover, it is an object of the present invention to provide an ATD circuit with a reduced number of elements.

[0010]

According to the present invention, as shown in FIG. 1, a resistance element R ₂₁ , a P-channel transistor Q _P21 and an N-channel transistor Q _N21 are connected in series in this order between a power supply voltage Vdd and a ground voltage Vss. Connected to the P
The _{gate of the} channel transistor Q _P21 and the _gate of the N-channel transistor Q _N21 have an address input terminal (2
NOR circuit (22) and inverter (2) connected to 1)
3) The address input signal is input via the above-mentioned 3), and the ATD signal is taken out from the connection node (b) between the resistance element R ₂₁ and the P-channel transistor _{QP 21} via the inverter (24). It is characterized by.

[0011]

According to the above means, when the address input signal applied to the address input terminal is in the low level or high level steady state, the P channel transistor Q _{P2
Since one of the 1} and N-channel transistor Q _N21 is off, the potential of the node (b) is the power supply voltage V
It becomes a high level by the resistance element R ₂₁ connected to dd, and in response to this, A is output from the inverter (24).
The TD signal becomes low level. In the transition period in which the address input signal rises from the low level to the high level, or in the transition period in which the address input signal falls from the high level to the low level, a period in which both the P-channel transistor _QP21 and the N-channel transistor _QN21 are turned on occurs, which causes a transient transition. The node (b) is pulled to the low level side and the switching voltage of the inverter (24) *
It becomes V _T or less. As a result, the ATD signal which is a high level pulse is output from the inverter (24), and the function equivalent to that of the conventional circuit can be realized.

As described above, according to the present invention, the power supply voltage Vd
resistor R connected in series between the voltage d and the ground voltage Vss
₂₁ and P channel transistor Q _P21 and N channel transistor Q _N21 and the inverter (24)
Since the D circuit can be configured, the number of elements can be significantly reduced as compared with the conventional circuit, and the pattern area can be reduced.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram showing an ATD circuit of the present invention.
In the figure, (21) is an address input terminal, (22) is a NOR circuit in which one input is connected to the address input terminal (21) and the other input is connected to the chip selection signal * CS. When the signal * CS is low level (ground voltage Vss), the address data input becomes enable.
Reference numeral (23) is an inverter connected to the output of the NOR circuit (22) for waveform shaping, and the NOR circuit (22) and the inverter (23) constitute an address input circuit.

The power supply voltage Vdd and the ground voltage Vss
A resistive element R ₂₁ and P-channel transistors Q _P21 and N-channel transistor Q _N21 between the is connected in series in this order, P-channel transistors Q _P21 and N
The _gate of the channel transistor Q _N21 is connected to the output of the inverter (23). Furthermore, the resistance element R ₂₁
And the ATD signal is taken out from the connection node (b) between the source of the P-channel transistor _{QP21 and} the _source of the P-channel transistor _QP21 via the inverter (24).

Here, the inventor of the present invention used a 0.8 μm process.
For mounting on SRAM semiconductor integrated circuit using
A specific example of the designed ATD circuit of the present invention will be described below.
First, the resistance element R_{twenty one}Eliminates the dependency on the power supply voltage Vdd.
Formed using a polysilicon film to obtain the specified characteristics.
The resistance value is 20k considering the pattern area etc.
It is set to Ω. Furthermore, P-channel transistor
Q_P21And N-channel transistor Q_N21Is a resistance element R
_{twenty one}During the period in which inquiries with
-In consideration of the node, make the potential of node (b) as steep as possible
Switch on the inverter (24) surely when it is turned off
Voltage * V_TBecause it must be
It is desirable that the resistance value be relatively small, and the P channel
Transistor Q_P21Transistor size is 30/1.
0 μm, N-channel transistor Q_N21Tran
The transistor size is 10 / 0.8 μm. Again
In the Akira ATD circuit, the role of the inverter (24)
Is a rectangular pulse waveform that shapes the potential change of node (b).
And the switching voltage of the inverter (24)
* V_TDepending on the level of the
Since it is arranged, the pulse obtained by the conventional ATD circuit
Adjusted to ensure the same level as the width,
In the embodiment, the switching voltage of the inverter (24)
* V _TIs set to be about (2/3) × Vdd
There is.

Next, the operation of the above-described ATD circuit of the present invention.
Will be described with reference to FIGS. 1 and 2. FIG. 2 shows in FIG.
FIG. 3 is an operation timing diagram of the circuit shown in FIG.
It was obtained as a result of simulation.
In the following description, V_tpAnd V_tnEach is P-cha
Channel transistor Q _P21And N-channel Transis
Q_N21It shows the threshold voltage of.

First, the address input signal applied to the address input terminal (21) is at a low level (ground voltage Vss).
At the time of, the output of the inverter (23) is at low level, which causes the P-channel transistor Q _P21
Is on, but the N-channel transistor Q _N21 is off. Thus Bruno - de (b) is a ground voltage is cut off from the Vss, the power supply voltage resistor connected Vdd R ₂₁
The potential of the node (b) is at a high level (source voltage V
dd), and in response to this, the inverter (24)
Outputs a low-level ATD signal.

When the address input signal rises from the low level to the high level, the output of the inverter (23) also rises from the low level to the high level, and when it exceeds V _tn , the P channel transistor Q _P21 and the N channel transistor Q _N21 are turned on. by both turned on, Bruno - de potential of (b) falls suddenly Shun towards the low level inverter - becomes less switching voltage * V _T of motor (24), receives this inverter - other (24) The output rises to high level. The inverter - data output (Vdd-V _tp) rises when the P-channel transistor Q _{P2 1} to more (23) is turned off. As a result, the node (b) is cut off from the ground voltage Vss, and the potential of the node (b) gradually rises to a high level via the resistance element R ₂₁ connected to the power source voltage Vdd, and the inverter is turned on. (2
4) The switching voltage * V _T or more is exceeded, and in response to this, the output of the inverter (24) falls to the low level. As a result, when the address input signal rises from the low level to the high level, the inverter (2
An ATD signal that is a high-level pulse is output from 4).

Thereafter, when the address input signal is in the high level steady state, the output of the inverter (23) also maintains the high level steady state, and the P-channel transistor Q
_P21 is turned off. With this, the inverter (24)
The ATD signal output from will maintain a low level. Next, when the address input signal falls from the high level to the low level, the output of the inverter (23) also falls from the high level to the low level, (Vdd-
When the voltage goes below V _tp ), both the P-channel transistor Q _P21 and the N-channel transistor Q _N21 are turned on, so that the potential of the node (b) suddenly falls toward the low level and the inverter (24) The switching voltage * V _T or less, and in response to this, the inverter (24)
Output rises to a high level. When the output of the inverter (23) falls below V _tn , the N-channel transistor Q _N21 turns off. As a result, the node (b) is cut off from the ground voltage Vss, and the potential of the node (b) gradually rises to the high level via the resistance element R ₂₁ connected to the power source voltage Vdd, and the inverter ( 24)
Of the switching voltage * V _T or more, and in response to this, the output of the inverter (24) falls to a low level. As a result, even when the address input signal falls from the high level to the low level, the inverter (24) outputs the ATD signal which is a high level pulse.

In this way, the address input terminal (2
The inverter (24) outputs an ATD signal that becomes a high-level pulse only when the address input signal applied to 1) rises from a low level to a high level or falls from a high level to a low level. Therefore, it is possible to realize the same function as the conventional one.
Here, the pulse width of the ATD signal that is a high-level pulse obtained based on the above-described design conditions is the power supply voltage V
When dd is 5.0 V, it becomes about 3 to 5 ns, and SRA
It has been realized that it is practically applicable in the application to the M semiconductor integrated circuit.

As described above, according to the present invention, the power supply voltage Vd
resistor R connected in series between the voltage d and the ground voltage Vss
₂₁ and P channel transistor Q _P21 and N channel transistor Q _N21 and the inverter (24)
Since the D circuit is configured, the number of elements can be significantly reduced as compared with the conventional circuit, and the pattern area can be reduced.

[0022]

According to ATD circuit of the present invention as described in the foregoing, a resistor connected in series elements R ₂₁ and P-channel transistor Q _{P2 1} and the N-channel transistor Q between the power supply voltage Vdd and the ground voltage Vss _{Since the N21} and the inverter (24) can realize a function equivalent to that of the conventional circuit, the number of elements can be significantly reduced as compared with the conventional circuit, and the pattern area can be reduced. It becomes possible. Therefore, in a semiconductor integrated circuit such as SRAM in which the number of address input terminals tends to increase, it has a great effect on reducing the chip size.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an ATD circuit according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing an ATD circuit according to a conventional example.

FIG. 4 is an operation timing chart of the circuit shown in FIG.

[Explanation of symbols]

21: Address input terminal 22: NOR circuit 23: Inverter 24: Inverter R ₂₁ : Resistor element Q _P21 : P-channel transistor Q _N21 : N-channel transistor * CS: Chip selection signal Vdd: Power supply voltage Vss: Ground voltage

Claims (1)

[Claims] 1. A resistance element, a P-channel transistor and an N-channel transistor are serially connected in this order between a power supply voltage Vdd and a ground voltage Vss, and an address input is applied to a gate of the P-channel transistor and the N-channel transistor. An address input signal is applied through an address input circuit connected to the terminal, and an ATD signal is taken out through an inverter from the connection point between the resistance element and the source of the P-channel transistor. Characteristic ATD circuit.