JP2944277B2 - Buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit, and more particularly to a buffer circuit having a CMOS structure.

[0002]

2. Description of the Related Art Conventionally, a buffer circuit having a CMOS structure, as shown in an example in FIG. 3, includes an inverter formed of a P-channel MOS transistor 23 and an N-channel MOS transistor 24 corresponding to a load capacitance 27. Many inverter-type circuits composed of an inverter formed by a P-channel MOS transistor 25 and an N-channel MOS transistor 26 are used, and the gate output of the preceding stage is directly connected to the input side of a buffer circuit in many cases. .

[0003]

In the conventional buffer circuit described above, since the steep rising and falling waveforms of the gate output of the preceding stage are directly input to the buffer circuit, the waveform of the buffer output also rises and falls. Both have steep waveforms, and furthermore, a maximum current flows transiently due to the charging and discharging of the load capacitance, and the potentials of the power source and the ground of the source float due to the voltage drop of the wiring and the like, resulting in deterioration of characteristics and There is a drawback of causing a malfunction or the like.

[0004]

A buffer circuit according to a first aspect of the present invention is a buffer circuit having a CMOS configuration, wherein a buffer output circuit connected in cascade to an inverter circuit forming a predetermined preceding stage has an output of the inverter circuit as a source. , A first N-channel MOS transistor having a gate connected to a high-potential power supply via a first resistor, and an output of the inverter circuit input to a source, and a gate connected via a second resistor. A first P-channel MOS transistor connected to a low-potential power supply, a source connected to the gate of the first N-channel MOS transistor, and a gate connected to the drain of the first N-channel MOS transistor; A second P-channel MOS transistor having a drain connected to the output terminal; and a source connected to the first P-channel MOS transistor. Is connected to the gate of the OS transistor, a gate connected to the drain of said first P-channel MOS transistor, a second N-channel MOS transistor having a drain connected to said output terminal,
It is comprised including.

A buffer circuit according to a second aspect of the present invention comprises a CM
In the buffer circuit having the OS configuration, an output of the inverter circuit is input to a source as a buffer output circuit cascaded to an inverter circuit forming a predetermined preceding stage, and a gate is connected to a high-potential power supply via a first resistor. A first N-channel MOS transistor to be connected, a first P-channel MOS transistor having a source connected to the output of the inverter circuit, and a gate connected to a low-potential power supply via a second resistor; Are connected to the gate of the first N-channel MOS transistor, the gate is connected to the drain of the first N-channel MOS transistor via a third resistor, and the second is connected to the output terminal. A P-channel MOS transistor having a source connected to the gate of the first P-channel MOS transistor; Said first P but via a fourth resistor
Connected to the drain of the channel MOS transistor,
A second N-channel MOS transistor having a drain connected to the output terminal, a source connected to a high-potential power supply, a gate connected to the gate of the second P-channel MOS transistor, and a drain connected to the output terminal A third P-channel MOS transistor connected to the second N-channel MOS transistor, a source connected to a low-potential power supply, a gate connected to the gate of the second N-channel MOS transistor, and a drain connected to the output terminal. 3 N-channel MOS
And a transistor.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, an inverter circuit formed of a P-channel MOS transistor 1 and an N-channel MOS transistor 2, an N-channel MOS transistor 3, and a P-channel MOS transistor 4, an P-channel MOS transistor 5, an N-channel MOS transistor 6, and an inverter / buffer circuit formed by resistors 7 and 8.

In FIG. 1, an input signal 101 is input to an inverter circuit formed by a P-channel MOS transistor 1 and an N-channel MOS transistor 2, output as a signal 102, and output from an N-channel MOS transistor 3 and a P-channel MOS transistor 4. of,
Input to each source. The inverter circuit itself is a conventionally used circuit, but the feature of the present invention lies in the inverter buffer circuit having the above-described configuration.

The charging of the load capacitor 9 through the buffer output signal 107 output from the drain of the P-channel MOS transistor 5 forming the inverter / buffer circuit is completed, and the P-channel MOS transistor 5
Is at the power supply voltage level, and when signal 106 at the source of N-channel MOS transistor 6 is at the ground potential level, N-channel M
OS transistor 3 and P-channel MOS transistor 4
Are both turned on. When the signal 102 output from the preceding inverter circuit is at “1” level,
The P-channel MOS transistor 5 is turned off, the N-channel MOS transistor 6 is turned on, and the level of the buffer output signal 107 tends to decrease to the ground potential via the resistor 8 and the N-channel MOS transistor 6. However, a current flows through the resistor 8 and the N-channel MOS transistor 6, and the resistor 8
, The gate potential of P-channel MOS transistor 4 floats, and P-channel MOS transistor 4 is turned off. For this purpose, a P-channel MOS
The drain of the transistor 4 is in a level holding state, the potential immediately before that is held as it is, and a current limited by this potential level flows through the N-channel MOS transistor 6 and the resistor 8.

When the discharge in the load capacitor 9 approaches completion and the discharge current decreases, the voltage drop in the resistor 8 decreases, the P-channel MOS transistor 4 returns to the on state, and the drain potential of the P-channel MOS transistor 4 rises. In response to this, the current flowing through the N-channel MOS transistor 6 is increased and the current is maintained at a predetermined value. However, the current required at the load is reduced by N-channel MOS transistor 6
If the driving capability of the buffer falls below the required driving capability, a current higher than the required current cannot flow, and eventually the buffer output signal 107 reaches the ground potential level and no current flows. Similarly, the potential of the drain of N-channel MOS transistor 3 is limited by the voltage drop in resistor 7, thereby limiting the driving capability of P-channel MOS transistor 5 and setting the current flowing in P-channel MOS transistor 5. It is possible to limit to less than the value.

As described above, the excessive current generated in the inverter / buffer circuit, including the current caused by charging / discharging in the load capacitance and the through current resulting from the simultaneous ON state of the P-channel MOS transistor 5 and the N-channel MOS transistor 6, It can be limited to a predetermined value or less.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. As shown in FIG. 2, in the present embodiment, a P-channel MOS transistor 10
And an inverter circuit formed of N-channel MOS transistors 11, N-channel MOS transistors 12, 17 and 21, P-channel MOS transistors 13, 16 and 20, resistors 14, 15, 18 and 1.
9 and an inverter buffer circuit.

The present embodiment is different from the first embodiment in that resistors 14 and 15
, The control range of the potential of the drains of the N-channel MOS transistor 12 and the P-channel MOS transistor 13 is expanded, and the functions of the P-channel MOS transistor 16 and the N-channel MOS transistor 17 connected to the resistors 18 and 19 , Resistance 18
The focus is on expanding the control range of the resistive voltage dividing ratio with respect to and 19, and for driving the load capacitance 22,
P channel MOS transistor 20 and N channel MOS
That is, the transistor 21 is mainly used. The basic operation is the same as that of the first embodiment.

[0014]

As described above, according to the present invention, in the inverter type buffer circuit, the current flowing through the MOS transistor in the output buffer circuit is limited to a set value or less to prevent the source power supply and the ground potential from lowering. This has the effect of preventing deterioration of characteristics and malfunctions caused by such problems.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 4, 5, 10, 13, 16, 20, 23, 25
P-channel MOS transistors 2, 3, 6, 11, 12, 17, 21, 24, 26
N-channel MOS transistors 7, 8, 14, 15, 18, 19 Resistors 9, 22, 27 Load capacitance

Claims (2)

(57) [Claims] In a CMOS buffer circuit, an output of the inverter circuit is input to a source as a buffer output circuit cascaded to an inverter circuit forming a predetermined preceding stage, and a gate is connected via a first resistor. A first N-channel MOS transistor connected to a high-potential power supply; a first P-channel MOS transistor having a source to which an output of the inverter circuit is input and a gate connected to a low-potential power supply via a second resistor A MOS transistor, a source connected to the gate of the first N-channel MOS transistor, and a gate connected to the first N-channel MOS transistor.
A second P-channel MOS transistor having a drain connected to the output terminal and a source connected to the gate of the first P-channel MOS transistor, and a gate connected to the first P-channel MOS transistor;
A second N-channel MOS transistor connected to the drain of the transistor and having the drain connected to the output terminal. 2. A buffer circuit having a CMOS configuration, wherein an output of the inverter circuit is input to a source as a buffer output circuit cascaded to an inverter circuit forming a predetermined preceding stage, and a gate is connected via a first resistor. A first N-channel MOS transistor connected to a high-potential power supply; a first P-channel MOS transistor having a source to which an output of the inverter circuit is input and a gate connected to a low-potential power supply via a second resistor A MOS transistor, a source connected to the gate of the first N-channel MOS transistor, and a gate connected to the first N-channel MOS transistor via a third resistor.
A second P-channel MOS transistor having a drain connected to the output terminal, a source connected to the gate of the first P-channel MOS transistor, and a gate connected to the fourth P-channel MOS transistor. The first through a resistor
A second N-channel MOS transistor having a drain connected to the output terminal, a source connected to a high-potential power supply, and a gate connected to the second P-channel MOS transistor. Connected to the gate of
A third P-channel MOS transistor having a drain connected to the output terminal, a source connected to a low-potential power supply, and a gate connected to the gate of the second N-channel MOS transistor;
A third N-channel MOS transistor having a drain connected to the output terminal.