JP2871902B2 - Current cell circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current cell circuit, and more particularly to a current cell circuit of a current cell matrix type DA converter.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional current cell circuit includes a power supply terminal 20, an output terminal 21, a switching signal input terminal 22, an inversion signal input terminal 23 of a switching signal, And a current source circuit 2.

Here, a voltage source circuit 1 includes a resistor 3 and a MOS
The current source circuit 2 has MOS transistors 6 to 14.

Next, the operation of the current cell circuit shown in FIG. 2 will be described. The transistor 5 determined by the impedance of the resistor 3 and the transistors 4 and 5 constituting the voltage source circuit 1
The gate potential (hereinafter abbreviated as V _G1) is, by biasing the gate of the transistor 6 of the current source circuit 2, (hereinafter referred to as I _Q6) drain current of the transistor 6 determines, switching signal input terminal 22 and the switching signal Inverting terminal 23
The switching signal V _IN to be input, for example, transistors 10, 11 and 12 are turned on, the transistor 9 and 13,
When the transistor 14 is turned off, the gate potential of the transistor 4 (hereinafter abbreviated as V _G2 ) determined by the impedance of the resistor 3 and the transistors 4 and 5 constituting the voltage source circuit 1 connects the gate of the transistor 8 of the current source circuit 2. Bias, and as a result, the output current of the current cell circuit (hereinafter, I _OUT
Constant current I _Q6 flows, also transistors 10, 11 and 12 is turned off as abbreviated), the transistor 9,13,1
If 4 is turned on, the gate of the transistor 8 of the current source circuit 2 is not biased, the gate of the transistor 7 is V _G2
Therefore, I _OUT does not flow to the output terminal 21.

That is, the output terminal 2 is _switched by the switching signal V _IN .
A constant current I _OUT flows or does not flow through the circuit 1 to function as a current cell circuit.

[0006]

The current cell circuit of the above-mentioned conventional current cell matrix type DA converter is as follows.
Transistors 11 and 12 is turned on, the gate potential V _G2 is at switching timing of the switching signal V _IN to bias the gate of the transistor 8, because there is a moment when the transistor 11 and the transistor 9 is turned on at the same time, the gate of the transistor 4 is A settling time is required until the voltage drops to the ground potential and the gate of the transistor 4 returns to V _G2 , and furthermore, the movement of charges during this time affects V _G1 via the gate overlap capacitance of the transistor 4. ,
By the gate potential of the transistor 6 is restored to V _G1,
Settling time is required.

For this reason, I _OUT (=
I _Q6) is to settle into a steady-state value, referred to as a certain amount of settling time (less than T _{set (out))} is required.

That is, in the conventional circuit, at the time of switching of the switching signal V _IN, a certain settling time is required until V _G1 and V _G2 reach a steady value, so that the I _OUT settling time of the current cell circuit is _reduced. There was a drawback of worsening.

It is an object of the present invention to solve the above-mentioned drawbacks, and to have a constant V _G1 and V _G2 at the switching timing of the switching signal V _IN .
An object of the present invention is to provide a current cell circuit in which the settling time of I _OUT is not deteriorated.

[0010] configuration of the current cell circuit of the present invention, respectively
First and second transistors connected in series with a gate connected to a drain and one of them connected to a high-potential power supply (or a low-potential power supply)
And the other is connected to the source of the first transistor.
Or a resistor connected to the drain and the second transistor
Source or drain of low potential power supply (or high power supply)
And a series connection of the third and fourth transistors and a series connection of the fifth and sixth transistors to connect the source or drain electrode of the seventh transistor and the drain thereof. Alternatively, connect the source electrode to a low potential power supply (or
Or a higher power supply), the gate of the first transistor is connected to the gates of the third and fifth transistors, the gate of the second transistor is connected to the gate of the seventh transistor, The gate of the sixth transistor is connected to a switching signal input terminal, the gate of the fourth transistor is connected to an inverted signal input terminal of the switching signal , and the source of the fifth transistor is a current output terminal.
And a current switching circuit .

[0011]

FIG. 1 is a circuit diagram showing a current cell circuit according to one embodiment of the present invention.

In FIG. 1, a current cell circuit according to the present embodiment includes a MOS transistor 4 in which a gate electrode and a drain electrode are connected to a power supply 20 via a resistor 3, and a gate electrode and a drain electrode in a source electrode of the transistor 4. And a MOS transistor 5 whose source electrode is grounded and a gate electrode and a drain electrode of the transistor 5 are connected,
A MOS transistor 15 having a source electrode grounded, a source electrode connected to the drain electrode of the transistor 6, and a gate electrode connected to the switching signal input terminal 22, and a source electrode connected to the drain electrode of the transistor 6 And a switching signal inversion signal input terminal 2
A MOS transistor 16 having a gate electrode connected to 3;
A MOS transistor 8 having a source electrode connected to the drain electrode of the transistor 15, a gate electrode connected to the gate electrode and the drain electrode of the transistor 4, and a drain electrode connected to the output terminal 21;
The MOS transistor 7 has a source electrode connected to the drain electrode 6, a gate electrode connected to the gate electrode and the drain electrode of the transistor 4, and a drain electrode connected to the power supply 20.

That is, this embodiment includes a voltage source circuit 1 and a current source circuit 2.

In FIG. 1, the same blocks, the same terminals, and the same elements as those in FIG. 2 have the same numbers.

That is, in this embodiment, the MOS transistors 6, 7, 8, 15, and 16 constitute the current source circuit 2, and include the power supply terminal 20, the output terminal 21, the switching terminal 22, and the inverted input of the switching signal. The terminal 23 is the same as the conventional one, and the voltage source circuit 1 also has the same configuration as the conventional one.

[0016] During switching timing of the switching signal V _IN, even transistors 15 and 16 are simultaneously turned on, the gate potential of the transistors 7 and 8 are connected directly to V _G2, 0
It does not fall to V and is always biased at _VG2 constant.

Therefore, unlike the conventional circuit, the charge transfer does not affect _VG2 via the gate-source overlap capacitance of the transistor 4, and the gate of the transistor 6 is always biased at _VG1 constant. . The gates of the transistors 7 and 8 are VG2, and the gate of the transistor 6 is V _{G2.
Since the} constant bias is always applied to _G1 , the switching signal V _IN merely turns on or off the transistor 15 or the transistor 16, and the constant current I _OUT flows or does not flow to the output terminal 21. It functions as a circuit.

FIG. 3 is a circuit diagram showing a current cell circuit according to another embodiment of the present invention.

FIG. 3 shows a circuit diagram in which the N-channel transistors of FIG. 1 are replaced with P-channel transistors.

Since the configuration and operation are the same as those of the first embodiment, the description will not be repeated.

[0021]

As described above, according to the present invention, for example, when connecting the gate potential of the transistor 8 directly V _G2, always gate of the transistor 8 even when switching timing of the switching signal V _IN is biased at V _G2 As a result, the gate of the transistor 6 is also biased at _VG1 at a constant value, so that the _settling time of I _OUT does not deteriorate and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a current cell circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional current cell circuit.

FIG. 3 is a circuit diagram showing a current cell circuit according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage source circuit 2 Current source circuit 3 Resistance element 4-16 MOS transistor 20 Power supply terminal 21 Output terminal 22 Switching signal input terminal 23 Switching signal inversion signal input terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/74 H03K 17/687 H03K 17/693

Claims (1)

(57) [Claims] A gate connected to a drain;
Column-connected first and second transistors , one of which is at high potential
Power supply (or lower power supply) and the other one is connected to the first
Resistor connected to the source or drain of the transistor
And the source or drain of the second transistor
A voltage source circuit connected to a potential power source (or a high-level power source) ; and a series connection of the third and fourth transistors and a series connection of the fifth and sixth transistors. Connect the electrode and its drain or
Connect the source electrode to a low-potential power supply (or high-potential power supply)
Connecting the gate of the first transistor to the gate of the third and fifth transistors, connecting the gate of the second transistor to the gate of the seventh transistor,
A gate of the sixth transistor is connected to a switching signal input terminal, a gate of the fourth transistor is connected to an inverted signal input terminal of the switching signal , and the fifth transistor
A current switching circuit having a current source as a current output terminal .