JPS63125016A - Output circuit - Google Patents

Abstract

PURPOSE:To decrease the level fluctuation of power supply and ground by connecting a resistor having a sufficient larger resistance than the conduction resistance of a drive transistor (TR) between the drive TR and an output TR. CONSTITUTION:The conduction on-resistance of CMOS TRs Q3-Q6 is selected sufficiently smaller than resistors R1, R2. The capability to drive output TRs Q1, Q2 depends on the resistances of the resistors R1, R2, the delay time when the gate input signal of the output TRs Q1, Q2 rises or descends is controlled by the resistors R1, R2 and kept nearly constant independently of the power potential. Thus, when the power potential is at a high level, the switching speed of the output TRs Q1, Q2 is increased, resulting in increasing the level fluctuation of power supply and ground levels and in incurring mis-recognition of the signal level given to an input terminal. Such defect is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an output circuit that includes a plurality of simultaneously switchable output transistors and is constructed of a semiconductor integrated circuit.

[Conventional technology]

A typical example of this type of output circuit is a multi-bit memory folding circuit. In such an output circuit, a plurality of output transistors are turned on simultaneously, and an output current of several tens to 100 mA may instantaneously flow into the ground or flow out from the power supply. At this time, the level of the power supply or ground varies according to the following equation (1) due to the inductance component parasitic to the power supply or ground.

dv=-L Positive L dt (1) In other words, when the output current suddenly flows into the ground, the ground level rises for a moment, and conversely, when the output current suddenly flows from the power supply, the power level rises for a moment. The level goes down. Furthermore, when the output transistors are simultaneously turned off and the flowing output current is suddenly cut off, the ground and power supply levels fluctuate in the opposite direction to the level fluctuations described above.

Further, due to the parasitic capacitance between the ground and the power supply, if the ground level fluctuates, the power supply level will also fluctuate, and conversely, if the power supply level fluctuates, the ground level will fluctuate as well.

As shown in FIG. 4, a conventional output circuit of this type includes two output transistors Q1. Q2 and output transistor Q+
CMOS transistors Q7 and Q8 that drive output transistor Q2) and CMOS transistor Q that drives output transistor Q2.
9 and Qto.

When the output control signal φ is at a low level, regardless of the state of the input signal IN, the P-channel output transistor Q+
The gate of the N-channel output transistor Q2 is at a high level, and the gate of the N-channel output transistor Q2 is at a low level. Therefore, two output transistors Ql.

Both Q2 become non-conductive, and the output terminal OUT becomes high-input.
It becomes a state of pedance.

When the output control signal φ is at a high level, the state of the input signal IN is the same as that of the output transistor Q1. transmitted to the gate of Q2,
If the input signal IN is at a high level, the output transistor Q1.
Both gates of Q2 are at low level. Therefore, the output transistor Q+ becomes conductive, the output transistor Q2 becomes non-conductive, the output terminal OUT becomes high level, and the output current changes to the output transistor Q! flows from the power supply to the external load via the Conversely, if the input signal IN is at a low level, the output transistors Q1. The gates of Q2 are both at a high level, the output transistor Q1 is non-conductive, and the output transistor Q2 is conductive, and as a result, the output terminal OUT is at a low level, and the output current is transferred from the external load to ground through the output transistor Q2. flows into.

[Problem that the invention seeks to solve]

In the conventional circuit described above, the output transistor Q+.

The gate input signal of Q2 is connected to CMO3) transistors Q7 and Q8. Since it is generated directly in Q9 and Qto,
When used with a high power supply potential, the potential difference between the source and drain of each CMO3) transistor may become large, and the CMO
3) Transistor Q7゜Q8. The capabilities of Q9 and Qto are increased and the output transistors Q1. The rise and fall of the Q2 gate input signal becomes steep, as shown in Figure 3 (B).
The switching speed of the output transistors Ql and Q2 also becomes faster.

As a result, the change in the output current also becomes rapid, so the absolute value of the output transistor Q
1. Due to the switching of Q2, the range of power supply and ground level fluctuations increases as described above.

If this kind of development occurs, when the power supply or ground level rises, the level applied to the input terminal of the semiconductor integrated circuit will be perceived as a relatively low level, and a high level will be mistakenly recognized as a low level. Sometimes. Similarly, when the power supply or ground level drops, the low level applied to the input terminal may be mistakenly recognized as a high level.

Therefore, the higher the power supply potential is, the more likely it is that the level of the input terminal of the semiconductor integrated circuit will be erroneously recognized.

In contrast to the conventional output circuit described above, the output circuit of the present invention has the following features:
The switching time of the output current is kept almost constant even when the power supply potential changes, and it has an original content in that it is possible to reduce level fluctuations in the power supply and ground due to changes in the output current, which are particularly likely to occur when the power supply potential is high.

[Means for solving problems]

The circuit of the present invention includes a plurality of output transistors that can be switched simultaneously, a drive transistor that drives each of the output transistors, and a circuit that is connected between the drive transistor and the output transistor and has a resistance that is sufficiently larger than the conduction state of the drive transistor. It is characterized by having a resistor having the following characteristics, and is constituted by a semiconductor integrated circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, two output transistors Q l, Q 2
and two CMs for driving the output transistor Ql.
OS transistor Q3. Q4 and output transistor Q2
two CMO3)-transistors Q5.
Qc, and CMOS transistor Q3. A resistor R connected between the node of Q4 and the gate of the output transistor Q+
1, and a CMOS transistor Q5. It has a resistor R2 connected between the node of Q6 and the gate of output transistor Q2.

CMOS transistors Q3, Q4, Q5 and Q6
The resistance when conducting is set to be sufficiently smaller than the resistances R, , R2. As a result, the ability to drive the output transistors Ql, Q2 is determined by the values of the resistors R, , R2. That is, the delay time when the gate input signals of the output transistors Ql and Q2 rise or fall is controlled by the resistors R1 and R2, and as shown in FIG. can be kept constant.

From the above, in the output circuit of the present invention, no matter what level the power supply potential is, the output transistors Q1. Q2
The switching time required when Q1. The switching speed of Q2 becomes faster, and as a result, the drawback that the level fluctuation of the power supply and ground becomes large, which makes it easy to misrecognize the level of the signal applied to the input terminal, is improved.

FIG. 2 is a circuit diagram showing a second embodiment of the invention.

Referring to FIG. 2, in this embodiment, instead of connecting the resistors R1 and R2 to the output terminals of the CMOS transistors Q3, Q4, Q5, and Q6 that drive the output transistors Ql and Q2 as in the first embodiment, , the drains of CMOS transistors Q3, Q4, Q5, Q6 and CM
It can be seen that resistors R3 and R4, R5 and R6 are provided between the nodes of OS transistors Q3 and Q4, Q5 and Q6.

CMO3) transistors Q3, Q4, Q5,
When the conductive resistance value of Q6 is set to be sufficiently smaller than the resistors Rs, R4, R5, and R6 connected to the respective drains, the CMOS transistors Q3. Q4 and resistance R,,R
The ratio of the resistance value of the CMOS inverter composed of 4 when the dark light is not conducting is determined by the value of the resistor R9゜R4, and
CMOS transistor Q5. The above ratio of the CMOS inverter consisting of Q6 and resistors R2 and R6 is
It will be determined by the value of 6.

That is, the delay time when the gate I/input signal of the output transistors Ql and Q2 rises from low level to high level is controlled by resistors R5 and R, respectively, and conversely, the delay time when it falls from high level to low level is controlled by resistors R5 and R, respectively. The delay time is determined by resistor R4,
Controlled by R6. Therefore, the delay time can be kept almost constant without depending on the power supply potential, and the same effect as in the first embodiment can be obtained.

Furthermore, in the first embodiment, the output transistors Ql, Q
Whereas the delay times required for the rise and fall of the gate input signal No. 2 were both controlled by the resistor R8 or R2, this embodiment has the advantage that the delay times for rise and fall can be controlled separately. .

〔Effect of the invention〕

As explained above, in the present invention, a resistor is provided at the output terminal of the drive circuit that generates the gate input signal of the output transistor, and the ability to drive the output transistor is controlled by this resistor. The switching time of is now kept almost constant regardless of the power supply potential, and therefore, when the power supply potential is high, fluctuations in the power supply and ground levels due to changes in the output current are smaller than in the past. As a result, the present invention has the effect of eliminating the drawback that the level of the input signal is likely to be erroneously recognized due to level fluctuations in the power supply or ground when the power supply voltage is high.

[Brief explanation of the drawing]

FIG. 1 shows the first embodiment of the present invention, FIG. 2 shows the second embodiment, FIG. 3 shows the gate input waveform of the output I transistor in the present invention and the conventional example, and FIG. 4 shows the conventional example. FIG. Ql, Q2...output transistor, Q3, Q4
. Q5, Q6, Q7, Qa, Q9,
Q+o-CMOS transistor, R,, R2, R,, R
4.R. R6...Resistance. Figure 1 Winter Figure 2

Claims (1)

[Claims] multiple output transistors that can be switched simultaneously;
A semiconductor, comprising a drive transistor that drives each of the output transistors, and a resistor connected between the drive transistor and the output transistor and having a value sufficiently larger than the resistance when the drive transistor is conductive. An output circuit consisting of an integrated circuit.