JPH0323715A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the output ringing of Low data from occurring by connecting a resistor with a large resistance value in series first when generating the Low data. CONSTITUTION:When an input signal psi2 changes from High to Low and an input signal psi2 changes from Low to High, in other words, when the output of the Low data is generated, a transistor 2 is turned on first, and after that, a transistor 3 is turned on with certain delay. Meanwhile, when the output of High is issued, the input signal psi1 changes from Low to high and the input signal psi2 changes from High to Low. Namely, when the output of Low is issued, it is pulled in a ground electrode GND with the transistor 2 via the resistor R4. Thus, the output of Low is pulled in the GND via the resistor with the large resistance value first when it is issued, and after that, it is pulled in the ground electrode(GND) via the transistor with high driving capability. In such a way, it is possible to prevent the output ringing without lowering output driving capability.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to an output circuit, and in particular makes it possible to control the insertion of a resistor between an output terminal and a grounding terminal (GND) when outputting low data. This relates to the output circuit.

[Conventional technology]

FIG. 2 shows a circuit diagram of a conventional output circuit. In the figure, 1 and 2 are n-type xios transistors, L is an inductance component, C is a condenser, and φ1, 1 are input signals shown in FIG. When the output is High, φ1 is H, 1, is L
Also, when the output is Low, φ1 becomes H, and 1, becomes H. Normally, the wiring connected to the output has an inductance component and capacitance, so for example, when the output is high
When the signal changes from high to low, ringing occurs as shown in FIG. 3. The rise from GND at this time is called VOL. Particularly in a CMOS type dynamic memory, the input signals φ1 and φ2 are generated by a CMOS inverter and have a waveform with very sharp rises and falls. Also,! ! g! In order to increase the capacity, the sizes of the output stage transistors 1 and 2 are often increased.

[Problem to be solved by the invention]

Conventional output circuits were configured as described above, so when the VOL standard is 0.4V, such as in a dynamic memory, output ringing occurs depending on the magnitude of L and C, and the VO
There was a problem that the voltage exceeded the L standard of 0.4V.

The present invention has been made to eliminate the above-mentioned problems 11, and aims to provide an output circuit that can prevent output ringing.

[Means to solve the problem]

The output circuit according to the present invention has an output terminal and a ground power supply (GND).
) between one n-type transistor connected to the polycrystalline S
It is equipped with a large resistance made of an i-compound, and is further equipped with one n-type transistor in parallel between the output terminal and the ground Wt source (GND).

[Operation] When the output circuit of this invention generates t, ow data, it first connects a large resistor in series.
Prevents output ringing of low data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an output circuit according to an embodiment of the present invention. In the figure, 1 to 3 are n-type transistors, 4 is a large resistor made of a polycrystalline Si compound or an n-type diffusion layer, 5 is a delay circuit, L is an inductance component,
C is the capacity. Still ψ1, ψ are input signals with the timing shown in FIG.

Next, the operation will be explained.

When the input signal ψ1 goes from High to Low, and when the input signal ψ2 goes from Low to old gh, that is, when a Low output is generated, first the transistor 2 turns on, and then the transistor 3 turns on with a certain delay. On the other hand, when outputting High, the input signal ψ1 changes from Low to High.
igh. The input signal ψ becomes Low from }iii. That is, at the time of Low output, the iζ is first drawn into the ground electrode GND from the transistor 24ζ through the resistor R4.

〔Effect of the invention〕

As described above, according to the present invention, in a dynamic memory with strict low output NOH standards, when a low output is made, it is first connected to GND through a large resistance, and then connected to the ground electrode (GND) through a transistor with a large drive capacity.
), it is possible to prevent output ringing without reducing output drive capability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the output circuit of the present invention;
FIG. 2 is a circuit diagram of a conventional output circuit, and FIG. 3 is a timing chart of each signal in FIGS. 1 and 2. In the diagram, 1 to a are n-type transistors, 4 is a resistor, 5 is a delay circuit, R is a resistor, L is an inductance component, and R is a capacitance. In the diagram, the same symbols indicate the same or equivalent parts. .

Claims (1)

[Claims] In a data output buffer composed of n-type transistors, a large resistor made of a polycrystalline silicon compound is provided between the output terminal and one n-type transistor connected to a ground power supply, and a large resistor made of a polycrystalline silicon compound is connected in parallel between the output terminal and the ground power supply. An output circuit comprising one n-type transistor.