JPH03204223A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the switching delay time by connecting an input terminal to each transistor(TR) gate with a resistor having a stepwise different resistance. CONSTITUTION:MOSFETs 31, 32, 33-3n are connected in parallel, resistors 21, 22, 23-2n-1 are connected in series with an input resistor 1, the connecting point of the resistors 21, 22 is connected to a gate of the MOSFET 32, the connecting point of the resistors 22, 23 is connected to the gate of the MOSFET 33 and the resistor 2n-1 is connected to the gate of the MOSFET 3n respectively. Since the switching delay time depends on the resistance of the input resistor 1 and the gate capacitance, the delay time Td is shortened by reducing the resistance of the input resistor 1 and the switching time is delayed for a TR whose resistance up to the gate is large in the case of viewing from the input terminal 1. Thus, the rising/falling time of the switching waveform viewed from the output terminal is prolonged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a plurality of field effect transistors connected equivalently in parallel.

[Prior Art] When switching a field effect transistor, the rise and fall times of the output are determined by the load condition, gate drive method, etc. Conventionally, there is a method to lengthen the rise and fall times. There was a way to put a resistor in the input.

FIG. 5 is a circuit diagram of a conventional example of a semiconductor device, and FIG. 6 is a waveform diagram of its input and output.

This semiconductor device includes MOSFET 12. ．． 12□.

123, -, +2n are connected in parallel, and each MOS F
ET121-12. A resistor 1 is connected between the gate and the input terminal of
1 is connected, and because of this resistor 11, the rise and fall of the output are long as shown in FIG. 6 (the broken line shows the case where the resistance value of the input resistor 11 is small).

[Problems to be Solved by the Invention] The conventional semiconductor device described above has the disadvantage that the switching delay time increases because the input resistance value is increased to increase the rise and fall times. If the value is too large, there is a drawback that abnormal operation may occur due to the capacitance between the gate and the train.

An object of the present invention is to provide a semiconductor device with a small switching delay time.

[Means to solve the problem]

In the semiconductor device of the present invention, resistors that differ in stages are connected between the input terminal and the gate of each field effect transistor.

[Function] By connecting the gate with resistances that differ in stages, the rise time and fall time can be lengthened without increasing the switching delay time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor device showing an embodiment of the present invention;
FIG. 2 is a diagram of its input and output waveforms.

This semiconductor device includes MOSFET 3. ．． 3□.

33,..., 3o are connected in parallel, and the input resistor 1 is connected to the resistors 21, 22, . ..., 2n-1 are connected in series, the connection point between resistors 2I and 22 is the gate of MOSFET 3□, and the resistors 22 and 2n-1 are connected in series. The connection point is MOS FET
At the gate of 3s,..., resistor 2n-1 is MO3
Each is connected to the gate of FET3n.

The switching delay time is determined by the value of the input resistor 1 and the gate capacitance, so by decreasing the value of the input resistor 1, the delay time Td becomes shorter, and a transistor with a large resistance value from the input terminal to the gate is Switching becomes slower, and the rise and fall times of the switching waveform seen from the output terminal become longer.

FIG. 4 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.

This example uses MOSFET 3. , 32.33. ...,
Resistors 4+, 4z, 4s, . . . , 4o having stepwise different resistance values are connected between the gate of 3□ and the input terminal.

This embodiment also provides the same effects as the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, by connecting the input terminal to the gate of each transistor using resistors with different resistance values in stages, the rise and fall times of switching are lengthened. This has effects such as reducing noise generation and reducing back electromotive force in an L (reactance) load.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention;
Fig. 2 is an input/output waveform diagram thereof, Fig. 3 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention, Fig. 4 is a circuit diagram of a conventional semiconductor device, and Fig. 5 is an input/output waveform diagram thereof. It is. 1... Input resistance, 21-2. ．． 4. ~4rl...Resistance, 31~3o...
- Field effect transistor, Td...delay time, T1...fall time, T2...rise time. Figure 1

Claims (1)

[Claims] 1. A semiconductor device including a plurality of field-effect transistors connected equivalently in parallel, characterized in that resistances with different values are connected in stages between the input terminal and the gate of each transistor. semiconductor device.