WO2015033631A1

WO2015033631A1 - Transistor circuit

Info

Publication number: WO2015033631A1
Application number: PCT/JP2014/064775
Authority: WO
Inventors: 栄治荻野
Original assignee: シャープ株式会社
Priority date: 2013-09-06
Filing date: 2014-06-03
Publication date: 2015-03-12

Abstract

In order to suppress an excessive increase of a potential at a cascode connection point, this cascode circuit is provided with a normally-on type transistor (11) and normally-off type transistors (121, 122), the first transistor (11) and the second transistor (121) are cascode-connected to each other, a source electrode of the transistor (121) and a source electrode of the transistor (122) are connected to each other, and a drain electrode of the transistor (121) and a drain electrode of the transistor (122) are connected to each other.

Description

Transistor circuit

The present invention relates to a transistor circuit having a normally-on transistor and a normally-off transistor that are cascode-connected to each other.

For example, Patent Document 1 discloses a conventional cascode circuit in which a normally-on transistor and a normally-off transistor are cascode-connected.

Japanese Patent Publication “Japanese Patent Laid-Open No. 2013-42270 (published on February 28, 2013)”

However, in the conventional cascode circuit, during the transient switching operation, the potential of the connection part between the source electrode of the normally-on type transistor and the drain electrode of the normally-off type transistor is overshooted. High-voltage stress exceeding the breakdown voltage between the drain-source of the normally-off transistor may be applied to the drain electrode of the normally-off transistor. As a result, there is a problem that the reliability of the normally-off transistor is affected.

The present invention has been made in view of the above problems, and its purpose is to increase the potential at the connection point of both transistors in a cascode circuit having a normally-on transistor and a normally-off transistor. It is to reduce.

In order to solve the above problems, a transistor circuit according to one embodiment of the present invention includes a normally-on first transistor, and normally-off second and third transistors, The second transistor is cascode-connected, one of the two conductive electrodes of the second transistor is connected to one of the two conductive electrodes of the third transistor, and the two conductive electrodes of the second transistor are connected to each other. The other and the other of the two conduction electrodes of the third transistor are connected.

According to one aspect of the present invention, there is an effect that it is possible to suppress an excessive increase in the potential of the cascode connection point.

1 is a circuit diagram illustrating a configuration of a cascode circuit according to Embodiment 1. FIG. It is a circuit diagram which shows the structure of one transistor of the switching circuit of the cascode circuit shown by FIG. It is a circuit diagram which shows the structure of the other transistor of the switching circuit of the cascode circuit shown by FIG. It is a top view which shows the structure of the switching circuit with which the cascode circuit shown by FIG. 1 is provided. It is a graph which shows the voltage waveform of the intermediate voltage of the cascode circuit shown by FIG. FIG. 6 is a circuit diagram illustrating a configuration of a cascode circuit according to a second embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a cascode circuit according to a third embodiment. 6 is a graph showing a voltage waveform of an intermediate voltage of the cascode circuit according to the second embodiment. 6 is a graph showing a voltage waveform of an intermediate voltage of a cascode circuit according to a third embodiment. It is a circuit diagram which shows the structure of the cascode circuit of a reference example. It is a circuit diagram which shows the structure in the case of operating the cascode circuit of a reference example. 12 is a graph showing voltage / current waveforms when the cascode circuit of the reference example shown in FIG. 11 is operated, (a) shows a voltage waveform applied to the gate electrode of a normally-off transistor, and (b) shows a voltage waveform. The voltage waveform applied to one terminal is shown, (c) shows the current waveform flowing from the terminal to the other terminal, and (d) shows the voltage waveform applied to the cascode connection node. It is the graph which expanded the voltage waveform shown in a part of (d) of Drawing 12 in the time direction. It is a circuit diagram which shows the structure in the case of operating the cascode circuit of this invention.

Embodiment 1
Embodiment 1 will be described below with reference to FIGS. 1 to 6 and the like.

<Configuration of the cascode circuit>
FIG. 1 is a circuit diagram showing a configuration of a cascode circuit (transistor circuit) 1 according to the present embodiment. As shown in FIG. 1, the cascode circuit 1 includes a normally-on type transistor 11 (first transistor) and a switching circuit 12.

The switching circuit 12 includes a normally-off transistor 121 (second transistor) and a normally-off transistor 122 (third transistor). The source electrode (conductive electrode) of the transistor 121 and the source electrode (conductive electrode) of the transistor 122 are connected, the drain electrode (conductive electrode) of the transistor 121 and the drain electrode (conductive electrode) of the transistor 122 are connected, and the transistor 121 The gate electrode (control electrode) of the transistor and the gate electrode (control electrode) of the transistor 122 are directly connected. The gate electrode of the transistor 121 is connected to the terminal 21 which is an input terminal through the internal resistance 15.

Transistor 11 and transistor 121 are cascode connected. That is, the source electrode of the transistor 11 and the drain electrode of the transistor 121 are connected at the node 24. The drain electrode of the transistor 11 is connected to a load, and the gate electrode of the transistor 11 is connected to the source electrode of the transistor 121 through the internal resistance 14. Note that the source electrode of the transistor 121 is connected to the terminal 23, and a ground potential is supplied to the terminal 23, for example.

The resistance value of the internal resistor 14 may be variable. In this case, for example, the resistance value may be adjusted by a combination of a plurality of types of resistance elements (switching between connections of a plurality of types of resistance elements).

Note that the normally-on transistor 11 is in an on state when the gate voltage is 0, and is turned off when the gate voltage exceeds the threshold voltage (the potential of the gate electrode is negative). The normally-off

transistors

121 and 122 are in an off state when the gate voltage is 0, and are turned on when the gate voltage exceeds a threshold voltage (positive as the potential of the gate electrode).

(Detailed configuration of switching circuit)
FIG. 2 shows the configuration of the transistor 121 of the switching circuit 12. As shown in FIG. 2, the transistor 121 includes a plurality of normally-off transistors 12a (subtransistors) connected in parallel to each other. Consists of. Here, the electrode 21 x corresponds to the gate electrode of the transistor 121, the electrode 24 x corresponds to the drain electrode of the transistor 121, and the electrode 23 x corresponds to the source electrode of the transistor 121.

FIG. 3 shows a configuration of the transistor 122 of the switching circuit 12. As shown in FIG. 3, the transistor 122 is a transistor group 12Y composed of a plurality of normally-off transistors 12a (subtransistors) connected in parallel to each other. Consists of. Here, the electrode 21 y corresponds to the gate electrode of the transistor 122, the electrode 24 y corresponds to the drain electrode of the transistor 122, and the electrode 23 y corresponds to the source electrode of the transistor 122.

FIG. 4 is a plan view of the switching circuit 12. The switching circuit 12 includes a plurality of transistors 12a arranged in a matrix on one semiconductor chip SC. The transistor 121 is formed in the first region 121R of the semiconductor chip SC, and 32 transistors (columns) × 6 (stages) of transistors 12a are connected in parallel. The transistor 122 is formed in the second region 122R of the semiconductor chip SC, and the transistors 12a are connected in parallel by 8 (columns) × 6 (stages). Note that the gate widths of the

transistors

121 and 122 correspond to the number of transistors 12a connected in parallel. In FIG. 4, the ratio of the gate widths of the

transistors

121 and 122 is 4: 1. However, the

transistors

121 and 122 are not limited to this configuration.

Note. The manufacturing processes of the transistor 121 and the transistor 122 are the same, and the gate length size is the same, and the gate width size is different.

<Description of Cascode Circuit of Reference Example>
FIG. 10 is a circuit diagram showing a configuration of the cascode circuit 201 of the reference example. As shown in FIG. 10, the cascode circuit 201 includes a normally-on transistor 211 and a normally-off transistor 212. Here, an internal resistor 214 is connected between the gate electrode of the transistor 211 and the source electrode of the transistor 212. Further, the gate electrode of the transistor 212 is connected to the terminal 21 via the internal resistor 215. The drain electrode of the transistor 211 is connected to the terminal 22. The source electrode of the transistor 212 is connected to the terminal 23. The source electrode of the transistor 211 and the drain electrode of the transistor 212 are connected to each other at the node 24.

FIG. 11 is a circuit diagram showing a configuration when the cascode circuit 201 is operated. As shown in FIG. 11, the cascode circuit 201 operates by being incorporated into a part of an inductive load circuit (hereinafter referred to as L load circuit) 301. Here, the L load circuit 301 includes an inductive load 311 constituted by an inductance, a freewheeling diode 312, and a DC power supply 313. The inductive load 311 and the freewheeling diode 312 are connected in parallel, one end of the circuit connected in parallel is connected to the terminal 22, and the other end is connected to the plus electrode of the DC power supply 313. Further, the negative electrode of the DC power supply 313 is connected to the ground GND.

The cascode circuit 201 is switched when the terminal 23 is connected to the ground GND and a rectangular pulse signal (input signal) P is input to the terminal 21.

FIG. 12 is a graph showing voltage / current waveforms when the cascode circuit 201 is operated. FIG. 12A shows a voltage (gate voltage) waveform 300 applied to the gate electrode of the normally-off transistor 212. b) shows a voltage (drain voltage) waveform 310 applied to the terminal 22, (c) shows a current (drain current) waveform 320 flowing from the terminal 22 to the terminal 23, and (d) is applied to the node 24. A voltage (intermediate voltage) waveform 330 is shown.

The threshold voltage Vth is a gate voltage (potential difference between the gate and the source) when the drain current of the normally-off transistor 212 rises. The reference voltage Vref is a reference voltage value in the cascode circuit 201, for example, a voltage value (ground potential) applied to the terminal 23 connected to the ground GND.

Also, the time Toff is the time when the period 400 ends and the time when the period 410 starts. The time Ton is the time when the period 410 ends and the time when the period 420 starts.

As shown in FIG. 12A, in the period 400, the gate voltage of the normally-off transistor 212 is higher than the threshold voltage Vth, and the normally-off transistor 212 is turned on. In the period 410, the gate voltage is substantially lower than the threshold voltage Vth and becomes the reference voltage Vref, and the normally-off transistor 212 is turned off. In the period 420, the value of the gate voltage is generally higher than the threshold voltage Vth again, and the normally-off transistor 212 is turned on. That is, the normally-off transistor 212 is generally periodically turned on / off by periodically supplying a rectangular pulse signal P to the gate electrode via the terminal 21.

As shown in FIG. 12B, in the period 400, the supply voltage to the terminal 22 is the reference voltage Vref. In the period 410, the supply voltage to the terminal 22 is higher than the reference voltage Vref. In the period 420, the supply voltage to the terminal 22 becomes the reference voltage Vref again.

As shown in FIG. 12C, the value of the current flowing from the terminal 22 to the terminal 23 is larger than 0 in the period 400, becomes 0 in the period 410, and becomes larger than 0 again in the period 420. .

As shown in FIG. 12D, in the period 400, the supply voltage to the node 24 is the reference voltage Vref. In the period 410, the supply voltage to the node 24 is higher than the reference voltage Vref. In addition, in the period 420, the supply voltage to the node 24 is approximately the reference voltage Vref again.

However, the cascode circuit of the reference example has a problem that the potential of the cascode connection point excessively rises. FIG. 13 is a graph in which the voltage waveform 330 shown in the range A in FIG. As shown in FIG. 13, the value of the voltage applied to the node 24 which is the cascode connection point is the time Toff (the gate voltage of the normally-off transistor 212 is generally lower than the threshold voltage Vth and becomes the reference voltage Vref. However, before it converges to a steady value, that is, in the transition period of the turn-off operation of the normally-off transistor 212, it overshoots (overshoot) as shown by the waveform shown in the range B. is doing. Further, when the potential of the cascode connection point is excessively increased, a voltage exceeding the breakdown voltage (high voltage stress) is applied between the drain electrode and the source electrode of the normally-off transistor 212, and the reliability as the transistor is increased. May decrease.

<Effect of this cascode circuit>
FIG. 5 is a graph showing a voltage waveform 30 of the intermediate voltage of the cascode circuit 1 shown in FIG. Note that the ratio between the gate width of the normally-off transistor 121 and the gate width of the normally-off transistor 122 is 9: 1. As shown in FIG. 5, the voltage waveform 30 is delayed as compared with the voltage waveform 330 shown in FIG. 13, and the overshoot is reduced. This is considered to be because the turn-off timing of the transistor 122 is delayed from that of the transistor 121 due to the gate resistance of each of the transistors 121 and 122 (internal resistance of the gate electrode).

As described above, according to the first embodiment, an excessive increase in the intermediate potential can be suppressed, and deterioration due to high voltage stress can be effectively prevented.

Embodiment 1 has been described with respect to an application to an N-channel transistor, but the present invention is not limited to this, and can also be applied to a P-channel transistor. In this case, the configuration of each semiconductor layer of the P-channel transistor is not particularly limited, and a conventionally known P-channel transistor can be used.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted. FIG. 6 is a circuit diagram of a cascode circuit (transistor circuit) 1a according to the second embodiment. As shown in FIG. 6, by providing a resistor Ca between the gate electrode of the transistor 121 and the gate electrode of the transistor 122 and further delaying the turn-off timing of the transistor 122, the voltage waveform 30 is further lowered as shown in FIG. A voltage waveform 30a is obtained.

Note that the resistance value of the resistor Ca in FIG. 6 may be variable. In this case, for example, the resistance value may be adjusted by a combination of a plurality of types of resistance elements (switching between connections of a plurality of types of resistance elements).

[Embodiment 3]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

In the cascode circuit 1 of FIG. 1 and the cascode circuit 1a of FIG. 6, the threshold voltage Vth of the transistor 121 may be different from the threshold voltage Vth of the transistor 122 (see FIGS. 7A and 7B). Specifically, the threshold voltage Vth of the transistor 122 is set higher than that of the transistor 121. Thereby, for example, in the configuration of FIG. 7A, as shown in FIG. 9, a voltage waveform 30b in which the overshoot voltage is reduced is obtained from the voltage waveform 30a when the threshold voltage is the same.

[Other configurations]
The other structure of this invention is demonstrated. For convenience of explanation, members having the same functions as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and description thereof is omitted.

FIG. 14 is a circuit diagram showing a configuration when the cascode circuit 1 is operated. As shown in FIG. 14, the cascode circuit 1 operates by being incorporated in a part of the L load circuit 101. In the cascode circuit 1, the terminal 23 is connected to the ground GND, and the rectangular pulse signal P is supplied to the terminal 21. As a result, the input signal is supplied to the gate electrode of the transistor 121 and switched.

[Summary]
The transistor circuit (cascode circuit 1 · 1a) according to the first aspect of the present invention includes a normally-on type first transistor (transistor 11) and normally-off type second and third transistors (transistors 121 and 121). The first transistor and the second transistor are cascode-connected, and one of the two conductive electrodes (source electrode) of the second transistor and one of the two conductive electrodes of the third transistor (source electrode) And the other of the two conductive electrodes of the second transistor (drain electrode) and the other of the two conductive electrodes of the third transistor (drain electrode) are connected.

In the transistor circuit according to aspect 2 of the present invention, in the aspect 1, the control electrode (gate electrode) of the second transistor and the control electrode (gate electrode) of the third transistor are connected directly or via a resistor. It may be.

In the transistor circuit according to aspect 3 of the present invention, in the above aspect 1 or 2, the second and third transistors may be formed on one semiconductor chip SC.

In the transistor circuit according to aspect 4 of the present invention, in any one of the aspects 1 to 3, the threshold voltage Vth of the third transistor may be higher than the threshold voltage Vth of the second transistor.

In the transistor circuit according to aspect 5 of the present invention, in any one of the aspects 1 to 4, the gate width of the control electrode of the second transistor may be larger than the gate width of the control electrode of the third transistor. Good.

In the transistor circuit according to aspect 6 of the present invention, in any one of the aspects 1 to 5, the turn-off timing of the second transistor and the turn-off timing of the third transistor may be different.

In the transistor circuit according to Aspect 7 of the present invention, in any one of Aspects 1 to 6, each of the second and third transistors includes a plurality of normally-off subtransistors (normally off) connected in parallel. Type transistor 12a).

In the transistor circuit according to aspect 8 of the present invention, in the aspect 7, the number of sub-transistors constituting the second transistor may be larger than the number of sub-transistors constituting the third transistor.

In the transistor circuit according to Aspect 9 of the present invention, in any one of Aspects 1 to 8, an input signal (pulse signal P) may be supplied to the control electrode of the second transistor.

In the transistor circuit according to aspect 10 of the present invention, in any one of the aspects 1 to 9, the first transistor may be connected to a load.

The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge or combinations thereof are also included in the embodiments of the present invention.

The present invention can be used for semiconductor devices.

1 Cascode circuit (transistor circuit)
1a Cascode circuit (transistor circuit)
11 Normally-on transistor (first transistor)
121 Normally-off transistor (second transistor)
122 Normally-off transistor (third transistor)
12a Normally-off transistor (subtransistor)
Ca resistance P Pulse signal (input signal)
SC semiconductor chip Toff time (turn-off timing)
Vth threshold voltage

Claims

A normally-on type first transistor; and normally-off type second and third transistors;
The first transistor and the second transistor are cascode-connected,
One of the two conducting electrodes of the second transistor is connected to one of the two conducting electrodes of the third transistor, the other of the two conducting electrodes of the second transistor and the two conducting electrodes of the third transistor. A transistor circuit connected to the other electrode.
The transistor circuit according to claim 1, wherein the control electrode of the second transistor and the control electrode of the third transistor are connected directly or via a resistor.
3. The transistor circuit according to claim 1, wherein the second and third transistors are formed on one semiconductor chip.
4. The transistor circuit according to claim 1, wherein the turn-off timing of the second transistor is different from the turn-off timing of the third transistor.
The transistor circuit according to any one of claims 1 to 4, wherein each of the second and third transistors includes a plurality of normally-off type sub-transistors connected in parallel.