JP2010028522A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of effectively utilizing a conventional semiconductor manufacturing process when making a semiconductor device that includes a through-current preventing function into one chip on a semiconductor substrate. <P>SOLUTION: This semiconductor device comprises: a transistor QN5 diode-connected between gate and source terminals of a transistor QN2 constituting a low-side switch; and a transistor QN6 diode-connected between gate and source terminals of a transistor QN4 constituting a low-side switch. Then, a threshold voltage of the transistor QN5 is made relatively lower than a threshold voltage of the transistor QN2. Furthermore, a threshold voltage of the transistor QN6 is made relatively lower than a threshold voltage of the transistor QN4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device applicable to a motor drive circuit or the like.

Conventionally, as this type of semiconductor device, for example, the one shown in FIG. 5 is known (see Patent Document 1).
As shown in FIG. 5, this semiconductor device includes an H bridge circuit 2 for driving a load 1 and pre-driver circuits 3 for driving N-type MOS transistors (switching elements) QN1 to QN4 constituting the H bridge circuit 2. 6 are provided.

The pre-driving circuits 3 and 5 shown in FIG. Further, the predriver circuits 4 and 6 are configured in the same manner, and a configuration example of the predriver circuit 4 is shown in FIG.
As shown in FIG. 6, the pre-driver circuit 4 includes a first CMOS inverter including a P-type MOS transistor QP41 and an N-type MOS transistor QN41, and a P-type MOS transistor QP42 and an N-type MOS transistor QN42. A second CMOS inverter is connected in cascade.
Here, the input signal IN input to the gates of the MOS transistors QP41 and QN41 is an on / off signal for performing the on / off operation of the MOS transistor QN2 of the H bridge circuit 2, or a control signal for performing the conduction control of the MOS transistor QN2. It is.

In the semiconductor device of FIG. 5, a case where, for example, a motor is connected as the load 1 connected to the output terminals 7 and 8 and the motor is driven will be described.
Now, when the MOS transistors QN3 and QN2 are turned on, a current flows through the load 1 from the output terminal 8 toward the output terminal 7. At this time, the potential of the output terminal 8 becomes the high-potential power supply voltage VBB, and the potential of the output terminal 7 becomes almost 0 [V], which is a low potential.
Here, when the MOS transistors QN3 and QN2 are on, the gate voltage Vg of the MOS transistor QN2 is the same as the output voltage VREG of the pre-driver circuit 4 (see FIGS. 6 and 7A), and the drain of the MOS transistor QN2 The voltage Vd is approximately 0 [V] (see FIG. 7B).

Next, a case where the MOS transistors QN3 and QN2 are switched from on to off will be described.
In this case, the gate voltage Vg of the MOS transistor QN2 rapidly decreases from the state of the output voltage VREG of the pre-driver circuit 4 as shown in FIG. However, at this time, the load 1, specifically, the inductor load such as a motor or the like, continues to flow current from the output terminal 8 toward the output terminal 7.
By this current regeneration operation, the energy stored in the inductor component of the load 1 is returned to the power supply via the parasitic diode between the source and drain of the MOS transistors QN1 and QN4. At this time, the potential of the output terminal 8 becomes 0 [V] or less, and the potential of the output terminal 7, that is, the drain voltage Vd of the MOS transistor QN2 becomes higher than the power supply voltage VBB (see FIG. 7B).

  Here, in the MOS transistor QN2, as shown in FIG. 5, a parasitic capacitance Cgd1 exists between the gate and the drain. For this reason, in the process in which the drain voltage Vd of the MOS transistor QN2 increases and changes to the power supply voltage VBB (see FIG. 7B), the gate voltage Vg of the MOS transistor QN2 starts to decrease and then decreases again. (See FIG. 7A). When gate voltage Vg of MOS transistor QN2 rises above threshold voltage Vth1 of MOS transistor QN2, MOS transistor QN2 is temporarily turned on, and a through current flows from the drain to the source. This through current may cause unnecessary heat generation or destruction of the MOS transistor QN2.

The troubles related to the MOS transistor QN2 as described above can occur in the MOS transistor QN4 as well.
By the way, such a through current can be prevented by connecting a diode (such as a Zener diode or a Schottky barrier diode) between the gate and source of the MOS transistors QN2 and QN4 (see, for example, Patent Document 2). . Such a diode can be easily added when the semiconductor device shown in FIG. 5 is configured by discrete components (individual components).

However, in the case where the semiconductor device shown in FIG. 5 is formed on a semiconductor substrate as a single chip and the prevention of through current is achieved by adding a diode, the following problems can be considered. That is, in this case, for example, it is necessary to newly add a production process of a Zener diode having desired characteristics or to add a production process of a Schottky barrier diode.
As a result, when a semiconductor device including a function of preventing overcurrent such as a through current is formed on a semiconductor substrate, a conventional semiconductor manufacturing process cannot be used, and a Zener diode or a Schottky barrier diode can be used. It is necessary to add a new production process.
JP 2007-60862 A Japanese Patent Laid-Open No. 6-318678

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which a conventional semiconductor manufacturing process can be utilized when a semiconductor device including a function for preventing an overcurrent such as a through current is formed on a semiconductor substrate. It is to provide.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
According to a first aspect of the present invention, a first high side switch and a first low side switch connected in series between a high potential power source and a low potential power source, and a series connection between the high potential power source and the low potential power source. An H-bridge circuit including a second high-side switch and a second low-side switch; a second transistor diode-connected between a gate electrode and a source electrode of the first transistor constituting the first low-side switch; A fourth transistor diode-connected between the gate electrode and the source electrode of the third transistor constituting the low-side switch, wherein the threshold voltage of the second transistor is higher than the threshold voltage of the first transistor And the threshold voltage of the fourth transistor is lower than that of the third transistor. It is relatively lower than that.

  According to a second aspect of the present invention, a first high side switch and a first low side switch connected in series between a high potential power source and a low potential power source, and a series connection between the high potential power source and the low potential power source. An H-bridge circuit including a second high-side switch and a second low-side switch; a second transistor that can be diode-connected between a gate electrode and a source electrode of the first transistor constituting the first low-side switch; A fourth transistor that can be diode-connected between the gate electrode and the source electrode of the third transistor constituting the low-side switch, a first control circuit that controls the diode connection of the second transistor, and the diode of the fourth transistor A second control circuit for controlling connection, wherein a threshold voltage of the second transistor is the second control circuit. Than the threshold voltage of the transistor has become relatively low and the threshold voltage of the fourth transistor is made relatively lower than the threshold voltage of the third transistor.

In a third aspect based on the second aspect, each of the first control circuit and the second control circuit has two transmission gates.
In a fourth aspect based on the second aspect, each of the first control circuit and the second control circuit has a transmission gate and a resistor.
According to the present invention having such a configuration, a conventional semiconductor manufacturing process can be utilized when a semiconductor device including a function of preventing an overcurrent such as a through current is formed on a semiconductor substrate.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an H bridge circuit (H bridge type output circuit) 2 that drives a load 1 and an N type MOS that constitutes the H bridge circuit 2. Pre-driver circuits 3 to 6 for driving transistors (power transistors) QN1 to QN4 and N-type MOS transistors QN5 and QN6 for preventing through current are provided.
In addition, the semiconductor device according to the first embodiment generates an H bridge circuit 2, pre-driver circuits 3 to 6, MOS transistors QN5 and QN6, and a logic circuit that generates input signals to be supplied to the pre-driver circuits 3 to 6 (FIG. (Not shown) is formed as a single chip on a semiconductor substrate.

Here, since the first embodiment of FIG. 1 has the same components as those of the conventional apparatus of FIG. 5, the same components are denoted by the same reference numerals, and the description thereof is omitted as much as possible.
MOS transistors QN1 and QN3 function as high-side switches, and MOS transistors QN2 and QN4 function as low-side switches. MOS transistor QN1 and MOS transistor QN2 are connected in series between a high-potential power supply to which power supply voltage VBB is supplied and a low-potential power supply to which power supply voltage VCOM is supplied. MOS transistor QN3 and MOS transistor QN4 are connected in series between a high-potential power supply to which power supply voltage VBB is supplied and a low-potential power supply to which power supply voltage VCOM is supplied.

MOS transistor QN2 has a parasitic capacitance Cgd1 between its gate and drain. Similarly, the MOS transistor QN4 has a parasitic capacitance Cgd2 between the gate and the drain.
The MOS transistor QN5 is diode-connected between the gate electrode and the source electrode (between the electrodes on the input side) of the MOS transistor QN2. That is, the gate and drain of MOS transistor QN5 are connected to the gate of MOS transistor QN2, and the source of MOS transistor QN5 is connected to the source of MOS transistor QN2.
Further, threshold voltage Vth2 of MOS transistor QN5 is set (created) relatively lower than threshold voltage Vth1 of MOS transistor QN2. That is, there is a relationship of Vth1> Vth2.

Specifically, the MOS transistor QN2 is a power transistor, and the threshold voltage Vth1 is about 2 [V], for example. The MOS transistor QN5 is a transistor having a smaller driving capability than the MOS transistor QN2 (for example, the above-mentioned MOS transistor for a logic circuit), and the threshold voltage Vth2 is about 1 [V], for example.
Similarly, the MOS transistor QN6 is diode-connected between the gate electrode and the source electrode (between the input electrodes) of the MOS transistor QN4. The threshold voltage Vth2 of the MOS transistor QN6 is set (created) relatively lower than the threshold voltage Vth1 of the MOS transistor QN4.

Next, an operation example of the first embodiment having such a configuration will be described with reference to FIGS. 1 and 2.
For example, when the MOS transistors QN3 and QN2 are turned on, a current flows through the load 1 from the output terminal 8 toward the output terminal 7. At this time, the potential of the output terminal 8 becomes the high-potential power supply voltage VBB, and the potential of the output terminal 7 (the drain voltage Vd of the MOS transistor QN2) becomes almost 0 [V] (see FIG. 2B). .
When the MOS transistors QN3 and QN2 are switched from on to off, the gate voltage Vg of the MOS transistor QN2 is suddenly changed from the state of the output voltage VREG of the pre-driver circuit 4 as shown in FIG. It goes down. However, at this time, the load 1, specifically, the inductor load such as a motor or the like, continues to flow current from the output terminal 8 toward the output terminal 7.

By this current regeneration operation, the energy stored in the inductor component of the load 1 is returned to the power supply via the parasitic diode between the source and drain of the MOS transistors QN1 and QN4. At this time, the potential of the output terminal 8 becomes 0 [V] or less, and the potential of the output terminal 7, that is, the drain voltage Vd of the MOS transistor QN2 becomes higher than the power supply voltage VBB (see FIG. 2B).
Incidentally, the MOS transistor QN2 has a parasitic capacitance Cgd1 between the gate and the drain. Therefore, when the MOS transistor QN5 is not diode-connected between the gate and drain electrodes of the MOS transistor QN2, the drain voltage Vd of the MOS transistor QN2 rises and changes to the power supply voltage VBB. As shown by the solid line in FIG. 2A, the gate voltage Vg starts to decrease and then decreases again. When the gate voltage Vg of the MOS transistor QN2 rises above the threshold voltage Vth1 of the MOS transistor QN2, the MOS transistor QN2 is temporarily turned on, and a through current flows from the drain to the source. .

However, in the first embodiment, the MOS transistor QN5 is diode-connected between the gate and drain electrodes of the MOS transistor QN2, and the threshold voltage Vth2 of the MOS transistor QN5 is higher than the threshold voltage Vth1 of the MOS transistor QN2. Is also relatively low.
For this reason, in the process in which the drain voltage Vd of the MOS transistor QN2 increases and changes to the power supply voltage VBB, the gate voltage Vg of the MOS transistor QN2 changes from a decrease to an increase as shown by the broken line in FIG. However, when the gate voltage Vg rises to the threshold voltage Vth2, the MOS transistor QN5 is turned on, and a current flows from the drain of the MOS transistor QN2 to the ground via the parasitic capacitance Cgd1 and the MOS transistor QN5. As a result, the maximum value of the gate voltage Vg of the MOS transistor QN2 is suppressed to the threshold voltage Vth1 or less (broken line in FIG. 2A), so that the MOS transistor QN2 is turned on and a through current flows from the drain toward the source. (Overcurrent) can be prevented from flowing.

The above description has been given of the case where the MOS transistor QN5 prevents the through current flowing through the MOS transistor QN2 when the MOS transistors QN3 and QN2 are switched from on to off. However, even when the MOS transistors QN1 and QN4 are switched from on to off, the through-current flowing through the MOS transistor QN4 can be prevented by the MOS transistor QN6 by the same operation as described above.
As described above, in the first embodiment, in order to prevent the through current flowing in the MOS transistors QN2 and QN4, the threshold voltage is higher than that of the MOS transistors QN2 and QN4 between the gate and source electrodes of the MOS transistors QN2 and QN4. The relatively low MOS transistors QN5 and QN6 are diode-connected.
For this reason, according to the first embodiment, when a semiconductor device including a function of preventing through current is formed on a semiconductor substrate as a single chip, a conventional semiconductor manufacturing process can be used, for example, reduction in manufacturing cost. Can be realized.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention is based on the configuration shown in FIG. 1, and the MOS transistors QN5 and QN6 in FIG. 1 are replaced with the MOS transistor QN7 and the control circuit 9 in FIG.
In addition, the semiconductor device according to the second embodiment includes an H bridge circuit 2, predriver circuits 3 to 6, a MOS transistor QN7, a control circuit 9, and a logic circuit that generates input signals to be supplied to the predriver circuits 3 to 6 (Not shown) is formed as one chip on the semiconductor substrate.
Here, except for the above points, the configuration of the other parts of the second embodiment is the same as the configuration shown in FIG.

FIG. 3 shows an example in which the MOS transistor QN5 of FIG. 1 is replaced with a MOS transistor QN7 and a control circuit 9, and the MOS transistor QN6 of FIG. 1 can be similarly replaced.
In the second embodiment, in order to prevent a through current (overcurrent) that flows when the MOS transistor QN2 switches from on to off, the MOS circuit QN7 is turned on by the control circuit 9 while the MOS transistor QN2 is off. A diode can be connected between the gate electrode and the source electrode of the transistor QN2 (between the electrodes on the input side).
In other words, the MOS transistor QN7 can be diode-connected (connected freely) between the gate electrode and the source electrode of the MOS transistor QN2. The control circuit 9 connects the MOS transistor QN7 to a diode between the gate electrode and the source electrode of the MOS transistor QN2 when diode connection is necessary.

Specifically, the drain of the MOS transistor Q7 is connected to the gate of the MOS transistor QN2, and the source of the MOS transistor Q7 is connected to the source of the MOS transistor QN2. The threshold voltage Vth3 of the MOS transistor QN7 is set (created) relatively lower than the threshold voltage Vth1 of the MOS transistor QN2. That is, there is a relationship of Vth1> Vth3.
As shown in FIG. 3, the control circuit 9 includes two transmission gates 91 and 92 and an inverter 93.

Transmission gate 91 is connected between the gate and drain terminals of MOS transistor QN7. The transmission gate 92 is connected between the gate and source terminals of the MOS transistor QN7. The transmission gates 91 and 92 are turned on and off by an input signal IN of the pre-driver circuit 4 and a signal obtained by inverting the input signal IN by the inverter 93, and operate so that when one is turned on, the other is turned off.
Here, the MOS transistor QN7, the transmission gates 91 and 92, and the inverter 93 are constituted by, for example, the above-described MOS transistors for the logic circuit.

Next, an operation example of the second embodiment having such a configuration will be described with reference to FIG.
Now, when the MOS transistor QN2 is on, the input signal IN of the pre-driver circuit 4 is at a high level, so that the transmission gate 91 of the control circuit 9 is off and the transmission gate 92 is on. For this reason, the MOS transistor QN7 is in the off state while the MOS transistor QN2 is on.
Thereafter, when the MOS transistor QN2 is switched from on to off, the input signal IN of the pre-driver circuit 4 changes from high level to low level, so that the transmission gate 91 of the control circuit 9 is switched from off to on, and the transmission gate 92 Goes from on to off. Therefore, during the period when MOS transistor QN2 is off, MOS transistor QN7 is diode-connected between the gate electrode and the source electrode of MOS transistor QN2. This corresponds to a state in which the MOS transistor QN5 is diode-connected between the gate and source electrodes of the MOS transistor QN2 as shown in FIG.

For this reason, in the second embodiment, the MOS transistor QN7 can prevent a through current flowing in the MOS transistor QN2 when the MOS transistor QN2 switches from on to off.
As described above, the second embodiment includes the MOS transistor QN7 and the control circuit 9, which can be configured by MOS transistors.
Therefore, according to the second embodiment, when a semiconductor device including a function for preventing a through current is formed on a semiconductor substrate as a single chip, a conventional semiconductor manufacturing process can be used, for example, a reduction in manufacturing cost. Can be realized.

(Third embodiment)
The semiconductor device according to the third embodiment of the present invention is obtained by replacing the control circuit 9 in the second embodiment of FIG. 3 with a control circuit 9A as shown in FIG.
Specifically, the transmission gate 92 of the control circuit 9 in FIG. 3 is replaced with the resistor 94 of the control circuit 9A in FIG.
According to the third embodiment having such a configuration, as in the second embodiment, the MOS transistor QN7 is diode-connected between the gate electrode and the source electrode of the MOS transistor QN2 while the MOS transistor QN2 is off. become.
Therefore, in the third embodiment, the MOS transistor QN7 can prevent a through current flowing in the MOS transistor QN2 when the MOS transistor QN2 switches from on to off.

(Other)
In the above embodiment, the MOS transistor (for example, the MOS transistor QN5) that is diode-connected to the low-side switch (for example, the transistor QN2) for protecting the through current is created when the chip is formed on the semiconductor substrate. The case where a transistor equivalent to that used in a logic circuit is used has been described.
However, in the present invention, it is only necessary that the threshold voltage of the diode-connected MOS transistor is relatively lower than the threshold voltage of the low-side switch. Therefore, when a pre-driver circuit created when a single chip is formed on a semiconductor substrate includes a thin film high voltage transistor, it can be used as a diode-connected transistor.

Here, the thin film high withstand voltage transistor has a voltage VGS applied between the gate and the source equal to that of the low withstand voltage transistor, for example, 10 [V], and the voltage VDS applied between the drain and the source during the off operation. Is equivalent to a high voltage transistor such as 50 [V].
Therefore, the thin film high breakdown voltage transistor has a gate film structure similar to that of the low breakdown voltage transistor and relatively thin, but the drain structure is as high as the drain structure of the high breakdown voltage transistor. The one with a breakdown voltage structure.

1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor device of the present invention. FIG. 2 is a waveform diagram showing an example of a voltage waveform at each part of a MOS transistor QN2 of FIG. It is a circuit diagram of the principal part of the structure of 2nd Embodiment of the semiconductor device of this invention. It is a circuit diagram of the principal part of a structure of 3rd Embodiment of the semiconductor device of this invention. It is a circuit diagram which shows the structural example of a conventional apparatus. It is a circuit diagram which shows the structural example of the conventional predriver circuit. FIG. 6 is a waveform diagram showing an example of a voltage waveform at each part of the MOS transistor QN2 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Load, 2 ... H bridge circuit, 3-6 ... Pre-driver circuit, 7, 8 ... Output terminal, 9, 9A ... Control circuit, QN2, QN4 ... MOS transistor , QN5 to QN7 ... MOS transistors

Claims (4)

A first high-side switch and a first low-side switch connected in series between a high-potential power supply and a low-potential power supply; a second high-side switch connected in series between the high-potential power supply and the low-potential power supply; An H-bridge circuit including a second low-side switch;
A second transistor diode-connected between a gate electrode and a source electrode of the first transistor constituting the first low-side switch;
A fourth transistor diode-connected between a gate electrode and a source electrode of a third transistor constituting the second low-side switch,
The threshold voltage of the second transistor is relatively lower than the threshold voltage of the first transistor, and the threshold voltage of the fourth transistor is the threshold voltage of the third transistor. A semiconductor device characterized by being relatively lower than the above. A first high-side switch and a first low-side switch connected in series between a high-potential power supply and a low-potential power supply; a second high-side switch connected in series between the high-potential power supply and the low-potential power supply; An H-bridge circuit including a second low-side switch;
A second transistor capable of diode connection between a gate electrode and a source electrode of the first transistor constituting the first low-side switch;
A fourth transistor capable of diode connection between a gate electrode and a source electrode of a third transistor constituting the second low-side switch;
A first control circuit for controlling the diode connection of the second transistor;
A second control circuit for controlling the diode connection of the fourth transistor,
The threshold voltage of the second transistor is relatively lower than the threshold voltage of the first transistor, and the threshold voltage of the fourth transistor is the threshold voltage of the third transistor. A semiconductor device characterized by being relatively lower than the above.   The semiconductor device according to claim 2, wherein each of the first control circuit and the second control circuit has two transmission gates.   The semiconductor device according to claim 2, wherein each of the first control circuit and the second control circuit has a transmission gate and a resistor.

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