JP5130896B2 - Semiconductor device drive circuit - Google Patents

Description

  The present invention relates to a drive circuit for a semiconductor element.

For example, a drive circuit 41 shown in FIG. 5 is used as a drive circuit for switching the semiconductor element.
In FIG. 5, the IC 12 generates a signal that varies the on period and the off period of the drive signal, and outputs the generated signal to the gates of the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2. The drain of the p-channel MOS transistor Q1 is connected to the gate of the p-channel MOS transistor Q3 and one end of the resistor R41. The source of the p-channel MOS transistor Q1 supply voltage _{V D} is supplied.

The drain of n-channel MOS transistor Q2 is connected to the gate of n-channel MOS transistor Q4 and the other end of resistor R41, and the source is grounded.
p-channel MOS transistor Q3 and the n-channel MOS transistor Q4 is connected in cascade, the source of the p-channel MOS transistor Q3 is connected to the power supply voltage _{V D} through a resistor R42. The voltage at the connection point between the MOS transistors Q3 and Q4 is output to the gate of the MOS transistor to be controlled (not shown). The source of the MOS transistor Q4 is grounded through a resistor R43.

FIG. 6 is a diagram showing operation waveforms of the IC 12 and the MOS transistors Q1 to Q4.
When the output of the IC 12 changes from the low level to the high level, the MOS transistor Q1 is turned off and the MOS transistor Q2 is turned on. When the output of the IC 12 is at a low level, the power supply voltage V _D is applied to the gate of the MOS transistor Q3. Therefore, even if the MOS transistor Q1 changes to the OFF state, the gate voltage of the MOS transistor Q3 is a positive constant value. The MOS transistor Q3 maintains an off state until it rises.

On the other hand, since the power supply voltage V _D has been applied to the gate of the MOS transistor Q4, the gate voltage of the MOS transistor Q4 does not immediately fall below the predetermined voltage even if the MOS transistor Q2 is turned on. It turns off after a lapse of time.

  Therefore, there is a period in which both MOS transistors Q3 and Q4 are turned on as shown in FIG. Since the resistors R42 and R43 are designed to have a small value in order to increase the output current of the drive circuit 41, a large through current flows when the MOS transistors Q3 and Q4 are simultaneously turned on.

In addition, it is desirable that the output of the IC 12 be at a low level until the power supply voltage V _D reaches a certain value at the time of starting the power supply. However, in practice, the IC 12 does not reach the voltage at which the IC 12 operates normally. Output is indefinite, and the voltage applied to the power supply terminal of the IC 12 may be output as it is as a high level signal. As a result, there is a possibility that a signal for turning on the semiconductor element is output from the drive circuit 11 when the power supply is started.

In Patent Document 1, in an inverter connected to a dependent power supply circuit that obtains a power supply voltage depending on the ON operation of the second switching element, the first is continued until the voltage of the dependent power supply circuit rises to a predetermined value or more. It is described that a circuit for prohibiting the ON operation of the switching element is provided.
Japanese Patent Laid-Open No. 1-114374

  An object of the present invention is to prevent the drive circuit from turning on until the power supply voltage of the drive circuit rises to a predetermined value or more, and to prevent a through current from flowing through the transistor in the output stage of the drive circuit that performs switching operation of the semiconductor element It is.

The present invention is a driving circuit for generating a drive signal for the semiconductor element is a switching operation, a first transistor output IC for generating a signal for determining the ON period and OFF period of the driving signal is applied to the gate , connected in cascade with said first transistor, consists of a second transistor an output of the IC is applied via a Zener diode to the gate, the first and second transistors comprises a MOS transistor, wherein a third MOS transistor having a gate connected to the drain or source of the first MOS transistor, one end to the drain or the source of the second MOS transistor is connected, a second connected other end to the power supply voltage a resistor, the second one end of the resistor, and a fourth MOS transistor having a gate connected.

According to this drive circuit, the drive circuit can be prevented from being turned on until the power supply voltage of the drive circuit rises to a predetermined value or more.
Further, with this configuration, the drive circuit can be prevented from being turned on until the power supply voltage of the drive circuit rises to a predetermined value or more.
In the driving circuit, the first and second MOS transistors are connected in cascade via a first resistor, the source of the third MOS transistor is connected to one end of a third resistor, and the drain is connected to the first resistor. The other end of the third resistor is connected to the power supply voltage, the source of the fourth MOS transistor is grounded via a fourth resistor, and the first resistor is connected to the drain of the fourth MOS transistor. The value of is larger than the values of the third resistor and the fourth resistor.

With this configuration, the value of the first resistor can be made larger than the values of the third resistor and the fourth resistor, and the first MOS transistor and the second MOS transistor The flowing through current can be set to a value that causes no problem in operation.
In the above driving circuit, wherein the gate of the first MOS transistor, a first diode and the first zener diode is connected in series, the gate of said second MOS transistor, a second diode And a second Zener diode are connected in series.

  With this configuration, the drive circuit can be prevented from being turned on until the power supply voltage of the drive circuit rises to a predetermined value or more, and the transistors in the output stage of the drive circuit can be prevented from being turned on at the same time.

  According to the present invention, it is possible to prevent the drive circuit from being turned on until the power supply voltage of the drive circuit rises to a predetermined value or more, and to prevent the transistors in the output stage of the drive circuit from being turned on simultaneously.

  Hereinafter, preferred embodiments of the present invention will be described. FIG. 1 is a circuit diagram of the drive circuit 11 according to the first embodiment. In the first embodiment, the drive circuit 11 is not turned on until the power supply voltage of the drive circuit 11 rises to a predetermined value or more.

  The drive circuit 11 is a circuit that generates a drive signal for switching the semiconductor element, for example, the MOS transistor Q5. The IC 12 is a dedicated semiconductor integrated circuit for signal generation, and outputs a signal that determines an on period and an off period of the drive signal. The output of the IC 12 is applied to the gate of the p-channel MOS transistor Q1 and the cathode of the Zener diode ZD2. The anode of the zener diode ZD2 is connected to the gate of the n-channel MOS transistor Q2 and one end of the resistor R5, and the other end of the resistor R5 is grounded (or a common potential, hereinafter described as ground).

The source of the MOS transistor Q1 is connected to power supply voltage _{V D,} the drain is connected to the gate of the p-channel MOS transistors Q3, one end of the resistor R1. The drain of the MOS transistor Q2 is connected to the other end of the resistor R1 and the gate of the n-channel MOS transistor Q4. The gate of the MOS transistor Q4 resistor R6 is connected, the other end of the resistor R6 is connected to the power supply voltage V _D.

The source of the MOS transistor Q3 is connected to one end of the resistor R2, and the drain is connected to the drain of the n-channel MOS transistor Q4. The other end of the resistor R2 is connected to the power supply voltage V _D. The source of the n-channel MOS transistor Q4 is grounded via a resistor R3.

  The connection point between the MOS transistor Q3 and the MOS transistor Q4 is connected to the gate of the n-channel MOS transistor Q5 to be controlled, and the output voltages of the MOS transistors Q3 and Q4 are output as drive signals to the gate of the MOS transistor Q5. . A resistor R4 is connected to the gate of the MOS transistor Q5, and the other end of the resistor R4 is grounded.

In the drive circuit 11 of FIG. 1, when the output of the IC 12 is at a low level, the p-channel MOS transistor Q1 is turned on and the n-channel MOS transistor Q2 is turned off.
When MOS transistor Q1 is in the ON state, the power supply voltage _{V D} to the gate of the p-channel MOS transistor Q3 is applied, the MOS transistor Q3 is turned off. When MOS transistor Q2 is off, the gate of the n-channel MOS transistor Q4, since the power supply voltage _{V D} is applied via a resistor R6, the MOS transistor Q4 is turned on.

  When the output of the IC 12 changes from the low level to the high level, the MOS transistor Q1 changes to the off state when the output voltage, that is, the gate voltage of the MOS transistor Q1 becomes equal to or higher than a certain voltage (the voltage at which the MOS transistor Q1 is turned off). To do. At this time, if the output voltage of the IC 12 is less than the Zener voltage of the Zener diode ZD2, the MOS transistor Q2 maintains the OFF state.

That is, when the output voltage of the IC 12 is less than the Zener voltage of the Zener diode ZD2, the MOS transistor Q2 is turned off.
When MOS transistor Q2 is off, the gate of the p-channel MOS transistor Q3, the power supply voltage _{V D} through a resistor R6, R1 is applied, the p-channel MOS transistor Q3 is kept off.

On the other hand, the power supply voltage _{V D} through a resistor R6 to the gate of the MOS transistor Q4 is applied, the MOS transistor Q4 is maintained in an ON state. Thereby, MOS transistor Q5 can be turned off.

That is, when the power supply voltage V _D of the drive circuit 11 is low and the output voltage of the IC 12 is less than the Zener voltage of the Zener diode ZD2, the MOS transistor Q2 can be turned off and the MOS transistor Q4 can be turned on. Output of a signal for turning on the element can be prevented.

According to the first embodiment described above, the Zener diode ZD2 is inserted between the output of the IC 12 and the gate of the MOS transistor Q2, and the power supply voltage V _D is applied to the gate of the MOS transistor Q4 via the resistor R6. Thus, it is possible to prevent the drive circuit 11 from outputting a signal for turning on the MOS transistor Q5 until the power supply voltage V _D of the drive circuit 11 becomes equal to or higher than a predetermined value.

  In the circuit of FIG. 1, the circuit for limiting the voltage at which the MOS transistor Q2 is turned on (or off) is not limited to the one using a zener diode, and a voltage limiting circuit having another configuration may be used. good.

  Next, FIG. 2 is a circuit diagram of the drive circuit 21 according to the second embodiment. In the second embodiment, the malfunction of the drive circuit 21 at the time of starting the power supply is prevented, and the transistors in the output stage of the drive circuit 21 are prevented from being simultaneously turned on at the time of switching. In the following, the same elements as those in FIG.

2, the gate of the p-channel MOS transistor Q1 is connected to power supply voltage _{V D} through a resistor R21, and is further connected to the output of IC12 via a Zener diode ZD1 and the diode D1. The cathode of the diode D1 is connected to the output of the IC 12, and the cathode of the Zener diode ZD1 is connected to the gate.

  The gate of the n-channel MOS transistor Q2 is connected to the output of the IC 12 through a Zener diode ZD2 and a diode D2, and is further grounded through a resistor R5. The anode of the diode D2 is connected to the output of the IC 12, and the anode of the Zener diode ZD2 is connected to the gate.

  The operation of the drive circuit 21 will be described with reference to the waveform diagram of FIG. When the output of the IC 12 is at a low level, a voltage obtained by adding the Zener voltage of the Zener diode ZD1 and the forward voltage of the diode D1 is applied to the gate of the p-channel MOS transistor Q1, and the MOS transistor Q1 is turned on. Yes.

On the other hand, the voltage applied to the gate of the MOS transistor Q2 is almost 0 V because the output of the IC 12 is at a low level, and the MOS transistor Q2 is in the off state.
When the output voltage of the IC 12 changes from low level to high level and the output voltage becomes equal to or higher than the Zener voltage of the Zener diode ZD2, the MOS transistor Q2 is turned on.

On the other hand, even if the output of the IC 12 becomes high level, no current flows from the IC 12 to the gate of the MOS transistor Q1 due to the diode D1, and current flows from the power supply voltage V _D through the path of the resistor R21. The MOS transistor Q1 is kept on for a certain time until reaching the value (off voltage).

  That is, as shown in FIG. 3, the MOS transistor Q2 is turned on immediately when the output of the IC 12 changes to a high level, but the MOS transistor Q1 remains on for a certain time until the gate voltage reaches a certain value. maintain. Accordingly, during that time, the MOS transistors Q1 and Q2 are simultaneously turned on (period in which both Q1 and Q2 in FIG. 3 are on). When the MOS transistors Q1 and Q2 are simultaneously turned on, a through current flows through the MOS transistors Q1 and Q2, but the value of the resistor R1 is designed to be larger than the values of the resistors R2 and R3 in the output stage. Therefore, the through current flowing through the transistors Q1 and Q2 can be set to a value that causes no problem in operation.

When MOS transistor Q1 is in the ON state, the power supply voltage _{V D} to the gate of the MOS transistor Q3 is applied, the MOS transistor Q3 is kept between the off state.
Even if the MOS transistor Q2 changes to the ON state, the MOS transistor Q4 maintains the ON state until the gate voltage of the MOS transistor Q4 becomes a certain value or less (period in which Q4 in FIG. 3 is ON).

  That is, the drive circuit 21 in FIG. 3 simultaneously turns on the MOS transistors Q1 and Q2 for a certain period after the output of the IC 12 changes from the low level to the high level, thereby turning the MOS transistor Q3 off. be able to. As a result, it is possible to prevent MOS transistors Q3 and Q4 from being simultaneously turned on and a through current from flowing therethrough.

  When a certain time passes and the gate charge of the MOS transistor Q4 is released and the gate voltage becomes less than a certain value, the MOS transistor Q4 changes to an off state (timing when Q4 in FIG. 3 changes to off). After that, when the gate voltage of the MOS transistor Q1 becomes a certain value or more and the MOS transistor Q1 changes to an off state (timing when Q1 in FIG. 3 changes to off), the gate voltage of the MOS transistor Q3 gradually decreases, and after a certain time The MOS transistor Q3 changes to the ON state (timing when Q3 in FIG. 3 changes to ON). At this time, the output voltage Vout at the connection point between the MOS transistors Q3 and Q4 becomes a positive voltage, and a drive signal for turning on the semiconductor element is output.

Next, the operation at the time of power activation will be described. Even if the IC 12 malfunctions when the power supply rises and a high level signal (for example, a signal having a voltage value substantially equal to the power supply voltage V _D at that time) is output, the output voltage of the IC 12 is the zener voltage of the zener diode ZD2 (diode When the voltage is less than (including the forward voltage of D2), the MOS transistor Q2 remains off.

When MOS transistor Q2 is off, the gate of the MOS transistor Q4, since the power supply voltage _{V D} via the resistor R6 is applied, the MOS transistor Q4 is turned on.

  Therefore, the output voltage Vout of the drive circuit 21 becomes the ground potential, and the semiconductor element (for example, the n-channel MOS transistor Q5) can be kept in the off state. As a result, even when a high level signal is output due to a malfunction of the IC 12 at the time of power activation, the output voltage Vout of the drive circuit 21 can be set to the ground potential, and the semiconductor element to be controlled can be turned off.

  According to the second embodiment described above, it is possible to prevent the MOS transistors Q3 and Q4 in the output stage of the drive circuit 21 from being turned on simultaneously when the output of the IC 12 changes. Further, even when the IC 12 malfunctions when the power is turned on and a signal (for example, a high level signal) for turning on an external semiconductor element is output, the gate voltage is limited by the Zener diode ZD2, so that the semiconductor circuit is driven from the drive circuit 21. Output of a signal for turning on the element can be prevented.

  Next, FIG. 4 is a circuit diagram of the drive circuit 31 according to the third embodiment. The third embodiment is an example in which the drive circuit 31 is composed of bipolar transistors Q 1 and Q 2, and the transistors Q 1 and Q 2 correspond to the transistors at the output stage of the drive circuit 31.

The output of the IC 12 is input to the base of the transistor Q1 via the Zener diode ZD3 and the resistor R11. The output of the IC 12 is input to the base of the transistor Q2 through the resistor R12. The collector of the transistor Q1 is connected to power supply voltage V _D through a resistor R13, the emitter of the emitter and the transistor Q2 of the transistor Q1 is connected, the collector of the transistor Q2 is grounded (or reference potential). A driving voltage Vout for driving a semiconductor element (not shown) is output from a connection point between the transistors Q1 and Q2.

  When the output of the IC 12 is at a low level, the transistor Q1 is off and the transistor Q2 is on. When the output of the IC 12 changes from the low level to the high level, the transistor Q2 changes to the off state. Keep it off until Thereby, it is possible to prevent the transistors Q1 and Q2 at the output stage of the drive circuit 31 from being turned on simultaneously when the output of the IC 12 changes.

The present invention is not limited to the embodiment described above, and may be configured as follows, for example.
The transistor used in the drive circuit is not limited to a MOS transistor, and may be another semiconductor element such as a bipolar transistor. Further, the drive circuit is not limited to a circuit in which two cascade-connected transistors are connected, but may be a circuit having a single-stage configuration as shown in FIG. 4 or a circuit having three or more stages.

FIG. 3 is a circuit diagram of a drive circuit according to the first embodiment. FIG. 6 is a circuit diagram of a drive circuit according to a second embodiment. It is a figure which shows the operation | movement waveform of 2nd Embodiment. FIG. 6 is a circuit diagram of a drive circuit according to a third embodiment. It is a circuit diagram of the conventional drive circuit. It is a figure which shows the operation | movement waveform of the conventional drive circuit.

Explanation of symbols

11, 21, 31, 41 Drive circuit 12 IC
ZD1, ZD2, ZD3 Zener diodes Q1-Q5 transistors

Claims (2)

A drive circuit for generating a drive signal for switching a semiconductor element,
A first transistor output IC for generating a signal for determining the ON period and OFF period of the driving signal is applied to the gate,
The cascade connected to the first transistor consists of a second transistor an output of the IC is applied to the gate via a Zener diode,
The first and second transistors are MOS transistors,
A third MOS transistor having a gate connected to the drain or source of the first MOS transistor;
One end to the drain or the source of the second MOS transistor is connected, and a second resistor connected other end to the power supply voltage,
To one end of said second resistor, it possesses a fourth MOS transistor having a gate connected,
The first and second MOS transistors are cascaded through a first resistor,
The source of the third MOS transistor is connected to one end of a third resistor, the drain is connected to the drain of the fourth MOS transistor,
The other end of the third resistor is connected to the power supply voltage,
The source of the fourth MOS transistor is grounded via a fourth resistor;
A drive circuit for a semiconductor element , wherein a value of the first resistor is larger than values of the third resistor and the fourth resistor . Wherein the gate of the first MOS transistor, a first diode and the first zener diode is connected in series,
Wherein the gate of the second MOS transistor, the second diode and drive circuit in accordance with claim 1, wherein the second zener diode are connected in series.

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