JP4066231B2 - Switching regulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the boost strap type DC / DC switching converter in which switching of the output transistor is performed at a drive voltage higher than the input power supply voltage in order to perform regulation with a high input power supply voltage and a low control power supply voltage, switching The present invention relates to a switching regulator that has been improved to improve the operation speed.
[0002]
[Prior art]
Due to diversification of devices that require a DC power source such as a portable personal computer, a DC / DC converter using a switching regulator is used to efficiently convert a voltage to obtain a predetermined voltage.
[0003]
In particular, in portable devices, MOSFET transistors are used as switching transistors in order to reduce power loss in switching transistor drivers and improve switching speed and response speed. Drive with high gate voltage. In this case, for example, the power supply voltage of the control circuit is 5V, and the output circuit obtains a high output voltage by switching a high input power supply voltage such as 10V to 30V.
[0004]
FIG. 3 shows a schematic circuit example of a switching regulator employing a conventional level shift circuit. This switching regulator includes a control circuit 1, a level shift circuit 2, a boost strap switching circuit 3, and a smoothing circuit 4. A control power supply is input to VDD, and an input power supply is input to VIN, and a predetermined output voltage is output from VO.
[0005]
The control circuit 1 feeds back the output voltage VO, compares it with a predetermined reference voltage Vref1, amplifies the difference and outputs the error amplifier 1a, and generates a control pulse PL having a duty according to the difference. And a signal generation circuit 1b. The control circuit is supplied with power by a control power supply VDD.
[0006]
The level shift circuit 2 receives the control pulse PL and converts it into a high voltage control pulse PH by a circuit composed of a constant current source 2a, NPN bipolar transistors Q31 and Q32, and a resistor R, and outputs it to the next stage. Output.
[0007]
The boost strap switching circuit 3 includes a driver circuit Dr1 on the Hi side that receives a high voltage control pulse PH and supplies a switching signal, an NMOS transistor Tr1 that turns on / off the input power source VIN by the switching signal, and an inverter 3a. A Lo-side driver circuit Dr2 that receives the inverted low voltage control pulse PL and supplies a switching signal, an NMOS transistor Tr2 that is complementarily turned on / off by the switching signal by the switching signal, and a Schottky diode SD1 It is constituted by a boost strap circuit that generates the voltage VIN of the input power supply or higher at the connection point n1 using the capacitor C.
[0008]
The smoothing circuit 4 includes an L-type smoothing filter including a Schottky diode SD2, an inductor L, and a capacitor CO, and improves output voltage ripple.
[0009]
Next, the operation of the level shift circuit 2 and the boost strap switching circuit 3 will be specifically described. When the Hi-side transistor Tr1 is turned off and the Lo-side transistor Tr2 is complementarily turned on, a charging current flows into the capacitor C from, for example, + 5V VDD via the Schottky diode SD1, and 5V is charged. . Next, when the transistor Tr1 is turned on and the transistor Tr2 is complementarily turned off, the voltage at the connection point n2 at the other end of the capacitor C becomes the same as the voltage VIN of the input power source, for example, + 25V, and the voltage at the connection point n1. In this case, 5V charged in the capacitor C rises by the voltage of the connection point n2, that is, + 25V and becomes + 30V. The voltage +30 V generated at the connection point n1 is supplied to the Hi-side driver circuit Dr1 of the boost strap switching circuit 3 and the collector of the transistor Q32 of the level shift circuit 2 via the resistor R.
[0010]
The collector of the transistor Q31 of the level shift circuit 2 is connected to the control power supply VDD via the constant current source 2a, and its emitter is grounded. The collector of the transistor Q32 is connected to the node n1 boosted through the resistor R as described above, and the output from the collector is input to the driver circuit Dr1 on the Hi side. Grounded. For this reason, the + 5V control pulse PL input to the base of the transistor Q31 is converted into a + 30V control pulse PH and output from the transistor Q32 to the driver circuit Dr1 on the Hi side.
[0011]
As a result, a high voltage control pulse having a Lo level of +25 V and a Hi level of +30 V is supplied as the gate voltage of the transistor Tr1 from the driver circuit Dr1 on the Hi side. Since this gate voltage is higher than the voltage of the input power supply, the transistor Tr1 can be driven at a high speed and its ON resistance can be reduced. Further, since the transistor Tr2 is driven on the low potential side, the voltage may be low. Similarly to the control circuit 1, the Lo side driver circuit Dr2 is also operated by the control power supply VDD of + 5V, and the + 5V switching signal is sent to the transistor Tr2 in the next stage. Supply to the gate.
[0012]
[Problems to be solved by the invention]
However, in the level shift circuit 2 composed of the transistors Q31 and Q32 as described above, when the transistor Q31 is turned off, the transistor Q32 is saturated due to the minority carrier accumulation effect. A significant delay occurs when the voltage at the connection point of the collector and the resistor R changes from the LOW level to the HIGH level. For this reason, the operation of the Hi side driver circuit Dr1 is delayed and the voltage stabilization operation is delayed.
[0013]
There is also a problem that the through current due to the level shift circuit is large and the current consumption is large.
[0014]
The present invention has been made to solve the above-described problems, and the voltage stabilization operation speed can be increased by greatly reducing the delay at the rise and fall of the control pulse PH as in the prior art. A switching regulator that is fast and consumes less power is provided.
[0015]
[Means for solving problems]
  In order to achieve the above object, in the present invention,In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
SaidA control circuit that operates at a control power supply voltage lower than the voltage of the input power supply and generates a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply; and boosting up the input power supplySaidGenerate boost voltage higher than input power supplybootStrap circuit,SaidA level shift circuit that uses a boost voltage as a power source and generates a second control pulse having a HIGH level higher than that of the first control pulse in response to the first control pulse;,Input power sourceofVoltageIs input at one endMOSFET transistorWhen,Said second control pulseIs enteredMOSFET transistorA drive circuit that directly drives the gate of
  The level shift circuit includes the first control pulse.At the gate of the first MOS transistor, the first control pulseThe first and second currents of the constant current source flow complementarily according to the result of comparing and comparing the voltage of the first control pulse with the intermediate level between the HIGH level and the LOW level as a reference. And the drain of the second MOS transistor is connected to the drain, and the drain is connected to the drain of the first MOS transistor.The source is connected to the boost voltageA third MOS transistor, a gate connected to the drain of the first MOS transistor, and a drain connected to the drain of the second MOS transistor;The source is connected to the boost voltageThe fourth MOS transistor and the third MOS transistor are connected in parallel, and the gate and drain thereof are connected to the drain of the third MOS transistor.The source is connected to the boost voltageThe fifth MOS transistor is connected in parallel to the fourth MOS transistor, and its gate and drain are connected to the drain of the fourth MOS transistor.The source is connected to the boost voltageWith the sixth MOS transistorAndA positive feedback connection is made to rapidly raise the HIGH level voltage of the output voltage of the drain of the second MOS transistor to a voltage higher than the HIGH level of the first control pulse.The second control pulseA switch circuit;Consist ofIt is characterized by that.
[0016]
  Furthermore, in the present invention,In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
SaidA control circuit that operates at a control power supply voltage lower than the voltage of the input power supply and generates a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply; and boosting up the input power supplySaidGenerate boost voltage higher than input power supplybootStrap circuit,SaidA level shift circuit that uses a boost voltage as a power source and generates a second control pulse having a HIGH level higher than that of the first control pulse in response to the first control pulse;,Of the input power sourceVoltage is input at one endMOSFET transistorWhen,Said second control pulseIs enteredMOSFET transistorA drive circuit that directly drives the gate of
  The level shift circuit includes first and second inverters.ThroughIn response to the level of the first control pulse input in a complementary manner, the first and second inverters supply the constant current to the first and second MOS transistors, respectively. The first and second current mirror circuits for suppressing the rise and fall delays of the control pulse respectively.With the first and second MOS transistors respectivelyMake up3And second4MOS transistor and the first3And second4The control voltage is always applied to the gate of each MOS transistor upstream or downstream of each of the MOS transistors.3And second4Suppresses voltage fluctuations in MOS transistors5And second6MOS transistor and the first6The gate of the MOS transistor is connected to the drain of the MOS transistor5The drain is connected to the drain of the MOS transistor7MOS transistor and the first5The gate of the MOS transistor is connected to the drain of the MOS transistor6The drain is connected to the drain of the MOS transistor8MOS transistor and the first7Connected in parallel to the MOS transistor of FIG.7Connected to the drain of the MOS transistor9MOS transistor and the first8Connected in parallel to the MOS transistor of FIG.8Connected to the drain of the MOS transistor10With MOS transistorsAndPositive feedback connected6A switch circuit that raises the HIGH level voltage of the output voltage of the drain of the MOS transistor to a voltage higher than the HIGH level of the first control pulse, and a source connected to the boost voltage;The drains are connected to the sources of the seventh to tenth MOS transistors,Depending on the current that flowsSaidSupply the voltage dropped from the boost voltage by the threshold to the switch circuit from the drain,SaidThe transition to HIGH level in the switch circuit11MOS transistor and the first5And second6A through-current suppressing circuit configured by a plurality of MOS transistors that receives an output voltage from the drain of the MOS transistor and suppresses a through-current caused by overlapping timings of the output voltages from flowing into the circuit;And an inverter circuit that receives the output voltage from the through current suppression circuit and outputs the output voltage as the second control pulse.It is characterized by that.
[0017]
  In the present invention,In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
Operating at a control power supply voltage lower than the voltage of the input power supply,A control circuit for generating a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply;A bootstrap circuit that boosts up the input power source to generate a boost voltage higher than the input power source, and uses the boost voltage as a power source in response to the first control pulse.A level shift circuit for generating a second control pulse whose HIGH level is higher than the first control pulse;A MOSFET transistor to which the voltage of the input power supply is input at one end, and a drive circuit for directly driving the gate of the MOSFET transistor by receiving the second control pulse,
  The level shift circuit includes:Connected to a voltage higher than the input power supplyThe high-potential side terminals are commonly connected and the low-potential side terminals are commonly connected,Input to the circuit connected to the terminal on the low potential sideA first switch circuit including a first transistor that is turned on / off in accordance with a level of the first control pulse, and a second transistor that is turned on / off in a complementary manner with the first transistor;Connected to a voltage higher than the input power supplyThe high-potential side terminals are commonly connected and the low-potential side terminals are commonly connected,According to the level of the first control pulse input to the circuit connected to the low potential side terminalA second switch circuit configured by a third transistor that is turned ON / OFF in a complementary manner with the first transistor and a fourth transistor that is turned ON / OFF in a complementary manner with the third transistor; The input terminal of the first transistor is connected to the low potential side terminal of the third transistor, the input terminal of the third transistor is connected to the low potential side terminal of the first transistor, and the second transistor And the input terminal of the fourth transistor are commonly connected to the low potential side terminals of the respective transistors, so that the second transistor is connected to the first and third transistors.RespectivelyComplementarilyTransition speed when turning from ON to OFF or from OFF to ONTheThan when there is no second and fourth transistor.Expedite the secondswitchcircuitTerminal on the low potential side ofFromVia the second switch circuitHigher than its voltage in response to the first control pulse.And higher voltage than the input powerA second control pulse is output.
[0018]
According to the above configuration, a low voltage control pulse is converted into a high voltage rising and falling control pulse with a level shift circuit, and the MOS transistor in the output stage is switched via the Hi side driver circuit. The switching operation becomes faster with respect to the regulation of the high input voltage, the regulation operation is stabilized, and a switching regulator with a small ON resistance and low power consumption can be provided.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 1 is a schematic circuit diagram of a switching regulator in which a level shift circuit according to an embodiment of the present invention is represented by a simplified circuit.
[0020]
The switching regulator of FIG. 1 includes a control circuit 1, a level shift circuit 2, a boost strap switching circuit 3, and a smoothing circuit 4. A control power supply is input to VDD, and an input power supply is input to VIN, and a predetermined output voltage is output from VO. Circuits other than the level shift circuit 2 are the same as the configuration of the circuit of FIG. 3 described as the prior art, and the description of the configuration and operation is omitted. Here, the level shift circuit 2 according to the embodiment of the present invention is omitted. The explanation will be focused on.
[0021]
The level shift circuit 2 according to the present invention shown in FIG. 1 is configured as a comparator 2e by operating NMOS transistors Q10 ′ and Q12 ′ as differential transistors, and the source thereof is connected through a common constant current source 2a through which a current value I flows. Is grounded. Therefore, the gate of the transistor Q12 'is grounded via the reference voltage generation circuit 2d that generates the reference voltage Vref, and the gate of the transistor Q10' receives a PWM signal that is a control pulse via the terminal Pulse. The PMOS transistors Q15 to Q18 constitute a switch circuit 2f with positive feedback connection, and the source of each transistor is connected to the connection point n1 via the terminal BST, and the boosted voltage via the terminal BST, for example, + 30V is supplied. The gates of the transistors Q16 and Q18 are respectively connected to the drain of the transistor Q12 'and input to the Hi side driver circuit Dr1 via the inverters 2b and 2c. The gates of the transistors Q17 and Q15 are connected to the drain of the transistor Q10 ', respectively. As a power source for the inverters 2b and 2c, for example, + 30V is supplied via the terminal BST, and for example + 25V is supplied via the terminal SW.
[0022]
Here, the reference voltage generation circuit 2d and the transistors Q10 ′ and Q12 ′ operate as a comparator that compares the PWM signal input to the gate of the transistor Q10 ′ to turn on / off, and the reference voltage Vref of the reference voltage generation circuit 2d. Is set to an intermediate level between the HIGH level (hereinafter “H”) and the LOW level (hereinafter “L”) at the control power supply voltage VDD, for example, + 5V, for example, + 2.5V.
[0023]
When the PWM signal transitions from “L” to “H”, the transistor Q10 ′ is turned on and the transistor Q12 ′ is turned off at the intermediate level at the time of transition. Conversely, when the PWM signal transitions from “H” to “L”, the transistor Q10 ′ is turned off and the transistor Q12 ′ is turned on at the intermediate level at the time of transition. By this method, whether the PWM signal exceeds or falls below the reference voltage, the HIGH level (hereinafter “Hbst”) and the LOW level (hereinafter “Lbst”) at the voltage +30 V of the terminal BST, for example, from the drain of the transistor Q12 ′. ) And the rise and fall of the output can be made faster than in the conventional circuit.
[0024]
Further, for example, when the PWM signal transitions from “L” to “H”, the transistor Q15 is also turned on almost simultaneously with the turning on of the transistor Q10 ′, so that the current I flowing through the constant current source 2a flows to Q15 and voltage drop occurs. appear. Since this voltage drop is larger than the threshold value of the gate of the transistor Q17, the transistor Q17 is turned on more quickly than when the transistor Q15 is not provided. At the same time, the voltage drop of Q18 due to the current I that has been flowing through the transistor Q18 disappears, and the transistor Q16 is immediately turned off. Therefore, “Hbst” that has been level-converted to a high voltage is output from the drain of the transistor Q17. On the other hand, when the PWM signal transitions from “H” to “L”, the transistor Q18 is turned on almost simultaneously with the turning on of the transistor Q12 ′, so that the current I flowing through the constant current source 2a flows to Q18, causing a voltage drop. appear. Since this voltage drop is larger than the threshold value of the gate of the transistor Q16, the transistor Q16 is immediately turned on. At the same time, when the current I flowing in Q15 disappears and the voltage drop due to Q15 disappears, the transistor Q17 is immediately turned OFF, and “Lbst” is output from the drain of Q17. That is, with this configuration, Q15 'or Q18's drain voltage rises, so that Q15 or Q18 operates so as to accelerate. Therefore, the configuration with only Q16 and Q17 is more delayed than when each is turned on. is decreasing. The transistors Q15 and Q18 can be resistors, but in this case, a high resistance is required and the influence of parasitic capacitance is likely to occur. In this way, by using MOS transistors for Q15 and Q18, the waveform at the time of transition between “Hbst” and “Lbst” can be speeded up, and furthermore, overvoltage is applied to the gates of the transistors Q16 and Q17. It can also be prevented from being applied.
[0025]
The voltage thus converted to a high voltage and outputted from the drain of the transistor Q12 ′ is supplied to the driver circuit Dr1 on the Hi side via the inverters 2b and 2a, and the transistor Tr1 in the final stage is made higher than the voltage of the input power supply. It turns ON / OFF complementarily with Tr2 at a high voltage.
[0026]
FIG. 2 is another specific circuit using CMOS of the level shift circuit 2 of the switching regulator described in FIG. The basic operation of the circuit is the same as that described with reference to FIG. 1, but the following is a supplementary explanation thereof.
[0027]
The terminals VDD, Pulse, BST, OUT, and SW shown in FIG. 2 correspond to the terminals having the same symbols shown in FIG. The terminal GND means a ground terminal. The PMOS transistor Q1 and the NMOS transistor Q2 constitute an inverter. Similarly, the transistors Q3 and Q4, Q5 and Q6, and Q7 and Q8 also constitute an inverter. Therefore, the transistors Q9 and Q11 are complementarily turned ON / OFF by the PWM signal input from the terminal Pulse. That is, the transistor Q9 is turned on when the PWM signal is “H”, and the transistor Q11 is turned on when the PWM signal is “L”. Here, resistors R1 and R2 provided between transistors Q5 and Q6, Q7 and Q8, respectively, are used to set a current flowing through transistors Q9 and Q11. Transistor Q9 forms a current mirror circuit with Q10, and transistor Q11 forms a current mirror circuit with Q12. Therefore, when the pulse signal at the Pulse terminal receives an “H” PWM signal, a current proportional to the current flowing through the transistor Q9 flows through the transistor Q10, and when an “L” PWM signal is received, the current through the transistor Q11 flows through the transistor Q12. A current proportional to the current flows.
[0028]
Each of the gates of the transistors Q13 and Q14 is supplied with + VDD, and a channel is always formed, so that voltage fluctuations at the time of ON / OFF of Q10 and Q12 are suppressed. That is, as described above, by driving the current corresponding to the current flowing through each inverter composed of the transistors Q5 and Q6, Q7 and Q8, and by limiting the current by the transistors Q13 and Q14, The delay of the rise and fall of the level-shifted signal when the transistors Q10 and Q12 are turned ON / OFF is reduced, and the transistors Q10 ′ and Q12 ′ of the simple circuit of this embodiment described with reference to FIG. In addition to playing the same role as the comparator, the withstand voltage of the level shift circuit is improved and the power consumption is reduced.
[0029]
The operations of the transistors Q15 to Q18 are the same as those of the switch circuit 2f including the transistors denoted by the same reference numerals described with reference to FIG. A current flowing through Q10 or Q12 always flows through the transistor Q19, and a voltage drop corresponding to a threshold value is generated between the drain / source. In other words, ON / OFF switching of Q16 and Q17 is performed at a boosted voltage supplied via BST, for example, a voltage lower than + 30V by a voltage drop of Q19, and is generated on the drain side of Q13 and Q14. The voltage at “Hbst” is lower than the voltage Vbst of the terminal BST by a voltage drop, which contributes to shortening of the signal rise and fall times. In other words, the transistor Q19 has an effect of restricting an overcurrent from flowing to a downstream circuit and preventing an overvoltage from being applied to the gates of the transistors Q16 and Q17.
[0030]
The levels output from the drain sides of Q13 and Q14 are complementary, but since the through current flows through the inverter at the moment when the levels overlap, the through current suppression circuit composed of transistors Q20 to Q25 is large. The output is made so that no through current flows. Transistors Q26 and Q27, Q28 and Q29 each constitute an inverter, and outputs a control pulse PH having a higher voltage to the driver circuit on the Hi side via the terminal OUT than the inverter at the final stage.
[0031]
In the present embodiment, a specific configuration example of the level shift circuit 2 has been described using a CMOS circuit. However, the present invention is not limited to this, and the level shift circuit 2 may be configured using other circuits based on the schematic circuit shown in FIG. Good. Further, the configuration examples of the circuits other than the level shift circuit 2 are for explanation of the present invention, and do not limit the scope of the present invention.
[0032]
【The invention's effect】
As described above, according to the switching regulator using the level shift circuit of the present invention, a low voltage PWM signal is converted into a control pulse with a high voltage rising and falling fast by the level shift circuit, and the Hi side Since the MOS transistor in the output stage is switched through the driver circuit, the switching operation becomes faster with respect to the regulation of the high input voltage, the regulation operation is stabilized, and a switching regulator with low ON resistance and low power consumption is provided. be able to.
[Brief description of the drawings]
FIG. 1 is a schematic circuit diagram of a switching regulator in which a level shift circuit according to an embodiment of the present invention is represented by a simplified circuit.
FIG. 2 is another specific circuit diagram of the level shift circuit using CMOS.
FIG. 3 is a schematic circuit example of a switching regulator employing a conventional level shift circuit.
[Explanation of symbols]
1 Control circuit
1a Error amplifier
2 Level shift circuit
2a Constant current source
2b, 2c inverter
2d reference voltage generation circuit
2e Comparator
2f switch circuit
3 Boost strap switching circuit
3a inverter
4 Smoothing circuit
BST terminal
C, CO capacitor
Dr1, Dr2 driver circuit
GND terminal
I current
L inductor
n1, n2 connection point
OUT terminal
PH High voltage control pulse
PL Low voltage control pulse
Pulse terminal
Q10 ', Q12', Q1-Q29, Q31, Q32 transistors
R, R1, R2 resistance
SW terminal
Tr1, Tr2 transistors
VDD Power supply voltage for control
VIN Input power supply voltage
VO output voltage
Vref, Vref1 reference voltage
SD1, SD2 Schottky diode

Claims (3)

In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
A control circuit which operates at a control power supply voltage lower than the voltage of the input power supply and generates a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply;
A bootstrap circuit which generates a higher boost voltage than the input power to boost up the input power,
A level shift circuit for generating said second control pulse is higher than the HIGH level is said first control pulse in response to the boost voltage as a power supply of the first control pulse,
A MOSFET transistor in which the voltage of the input power supply is input to one end ;
A drive circuit for directly driving the gate of the MOSFET transistor by receiving the second control pulse ;
The level shift circuit includes:
By receiving the first control pulse at the gate of the first MOS transistor , the intermediate level between the HIGH level and the LOW level of the first control pulse is used as a reference and the voltage of the first control pulse. First and second MOS transistors through which the current of the constant current source flows complementarily according to the comparison result,
A third MOS transistor having a gate connected to the drain of the second MOS transistor, a drain connected to the drain of the first MOS transistor, and a source connected to the boost voltage; and the first MOS transistor A fourth MOS transistor having its gate connected to the drain of the transistor, its drain connected to the drain of the second MOS transistor, and its source connected to the boost voltage, and connected in parallel to the third MOS transistor A fifth MOS transistor whose gate and drain are connected to the drain of the third MOS transistor and whose source is connected to the boost voltage; and a gate connected to the fourth MOS transistor in parallel; The drain of the fourth MOS transistor Connected said sixth MOS transistor from a Rutotomoni positive feedback connected first the HIGH level voltage of the drain of the output voltage of said second MOS transistor of the control pulse the source connected to the boosted voltage switching regulator and switching circuit for rapidly pulling up the hIGH higher level voltage and said second control pulse, in that it consists characterized. In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
A control circuit which operates at a control power supply voltage lower than the voltage of the input power supply and generates a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply;
A bootstrap circuit which generates a higher boost voltage than the input power to boost up the input power,
A level shift circuit for generating said second control pulse is higher than the HIGH level is said first control pulse in response to the boost voltage as a power supply of the first control pulse,
A MOSFET transistor in which the voltage of the input power supply is input to one end ;
A drive circuit for directly driving the gate of the MOSFET transistor by receiving the second control pulse ;
The level shift circuit includes:
A constant current is supplied from the first and second inverters to the first and second MOS transistors, respectively, according to the level of the first control pulse that is complementarily input via the first and second inverters. by a third constituting together with the first control pulse rise and fall delay of the first suppressing respectively the second current mirror circuit and each of the first second MOS transistor input A fourth MOS transistor;
The fifth and sixth MOS transistors suppress the voltage fluctuations of the third and fourth MOS transistors by always applying a control voltage to the gates of the third and fourth MOS transistors, respectively, upstream or downstream. A MOS transistor;
A seventh MOS transistor whose drain to the drain of the sixth MOS gate thereof to the drain of the transistor is connected said fifth MOS transistor is connected, a gate connected to the drain of the fifth MOS transistor an eighth MOS transistor having its drain connected to the drain of the sixth MOS transistor, the seventh connected the gate and drain in parallel with the MOS transistor is connected to the drain of said seventh MOS transistor ninth and MOS transistor, said eighth MOS transistor is connected in parallel its gate and drain is 10 Rutotomoni positive feedback connection such from the MOS transistor connected to the drain of the MOS transistor of the eighth of the the drain of the output of the sixth MOS transistor A switching circuit to raise the HIGH level voltage of voltage to a higher voltage than the HIGH level of the first control pulse,
Said boost voltage source connected to the drain thereof to the sources of the seventh to tenth MOS transistor is connected, the voltage dropped the threshold amount from the boosted voltage by a current flowing through the switching circuit from the drain supplied, the eleventh MOS transistor for transition to HIGH level at the switching circuit,
A through current suppression circuit configured by a plurality of MOS transistors that receive output voltages from the drains of the fifth and sixth MOS transistors and suppress a through current due to overlapping timings of the output voltages from flowing into the circuit ;
An inverter circuit that receives an output voltage from the through current suppression circuit and outputs the output voltage as the second control pulse . In a switching regulator that controls the voltage of the input power supply so that the output voltage becomes the target voltage,
A control circuit which operates at a control power supply voltage lower than the voltage of the input power supply and generates a first control pulse having a predetermined pulse width having a voltage whose HIGH level is lower than that of the input power supply;
A bootstrap circuit that boosts up the input power to generate a boost voltage higher than the input power;
A level shift circuit that uses the boost voltage as a power source and generates a second control pulse having a HIGH level higher than the first control pulse in response to the first control pulse ;
A MOSFET transistor in which the voltage of the input power supply is input to one end;
A drive circuit for directly driving the gate of the MOSFET transistor by receiving the second control pulse;
The level shift circuit includes:
The high potential side terminals connected to a voltage higher than that of the input power source are commonly connected, and at the same time, the low potential side terminals are commonly connected, and are input to the circuit connected to the low potential side terminals. A first switch circuit including a first transistor that is turned on / off according to the level of the control pulse, and a second transistor that is turned on / off in a complementary manner to the first transistor;
The high potential side terminals connected to a voltage higher than that of the input power source are commonly connected, and at the same time, the low potential side terminals are commonly connected, and are input to the circuit connected to the low potential side terminals . The second transistor is configured by a third transistor that is complementarily turned on / off with the first transistor in accordance with the level of the control pulse, and a fourth transistor that is complementarily turned on / off with the third transistor. And a switch circuit of
The input terminal of the first transistor is connected to the low potential side terminal of the third transistor, the input terminal of the third transistor is connected to the low potential side terminal of the first transistor, and the second transistor When the fourth input terminal of the transistor by being commonly connected to the low potential side terminal of the respective transistors, the second transistor is the first and the third transistor is OFF or OFF from complementarily ON respectively from faster than when there is no second and fourth transistors the transition speed at which turns ON, the said second switching circuit and the low potential side terminal from said first through said second switching circuit switching regulator and outputs a second control pulse of high rather and higher than the input supply voltage than that voltage in response to a control pulse.

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