JP6919920B2 - Adaptive controller for voltage converter - Google Patents

Description

No reference to related applications.

A switched mode DC-DC boost converter generally includes at least two semiconductor devices as switches, such as a transistor as a switch and a diode or transistor as a synchronous switch. Switching the semiconductor switch on and off even more efficiently can advantageously increase the efficiency of the DC-DC boost converter as a whole.

Systems and methods for reducing time fluctuations to switch off a DC-DC boost converter are disclosed herein. In one embodiment, the DC-DC converter comprises an input voltage node, an inductor, and a switch coupled to the inductor and the input voltage node. More specifically, the switch has an on-state and an off-state, during which the current flowing through the inductor increases, and in the off-state, the current flowing through the inductor through the driver coupled to the switch. Leads to a reduction in The driver includes multiple transistors and an adaptive voltage node so that the voltage level at the adaptive voltage node fluctuates according to the current flowing through the inductor so as to reduce the variation in the amount of time to switch off. Is.

In another embodiment, the DC-DC converter is attached to the first switch coupled to the input voltage node and the inductor, the second switch coupled to the inductor and the output voltage node, and the first and second switches. Includes a driver that is coupled and configured to alternately turn the first and second switches on and off. More specifically, while the first switch is on, the first switch is configured to increase the current flowing through the inductor. While the second switch is on, the second switch is configured to reduce the current flowing through the inductor. While the first switch is off, the driver provides an adaptive voltage node with a voltage level that reduces the variation in time to turn off the first switch. It is inversely proportional to the current flowing through.

In a further embodiment, one method uses the main switch of the DC-DC converter to reduce the current flowing through the inductor coupled to the input voltage node and the main switch, based on the current flowing through the inductor. Determining the amount of time to turn off the main switch based on turning it off, providing a voltage level at the adaptive voltage node that is inversely proportional to the current flowing through the inductor, and the voltage level at the adaptive voltage node. Including that.

References are made to the accompanying drawings for a detailed description of the exemplary embodiments of the invention.

A block diagram for illustrating a DC-DC boost converter including an adaptive controller according to various embodiments is shown.

Further illustrations of adaptive controllers according to various embodiments are shown.

A method for determining the amount of time to switch off the main switch of a DC-DC boost converter according to various embodiments is shown. Notation and terms

Certain terms are used to refer to specific system components throughout the description and claims below. As will be appreciated by those skilled in the art, a company may refer to a component with a different name. The present specification is not intended to distinguish between components with different names rather than functions. In the following description and in the claims, the terms "inclusion" and "comprising" are used in a non-limiting form, and thus "including, but not limited to ...". It should be interpreted as meaning. Also, the term "couple or couples" is intended to mean either indirect or direct connection. Therefore, when the first device is coupled to the second device, the connection may be via a direct connection or through another device and an indirect connection via the connection.

Subsequent description is directed to various embodiments of the present invention. One or more of these examples may be preferred, but the disclosed examples should not be used in any interpretation or other manner to limit the scope of the present disclosure, including the claims. Also, those skilled in the art will appreciate that the following description has a wide range of uses, and that the description of any embodiment is intended only to be an example of that embodiment, and the scope of the present disclosure, including the claims, is such. It will be found that it is not intended to imply that it is limited to the examples.

Boost converters are used to generate higher output voltages based on lower input voltage sources. Thus, for example, an input voltage source from a battery can be received by a direct current (DC / DC) boost converter and is required to power various electrical components that require a particular regulated voltage. Can be boosted to the voltage of.

Generally, a switched mode boost converter includes at least two semiconductor devices (diodes and / or transistors, etc.) and at least one energy storage element (capacitors, inductors, etc.). In the boost converter, the semiconductor device may be configured as a switch to alternately turn on and off to regulate the input voltage to the desired output voltage. More specifically, turning the switch on and off can be controlled via a driver or controller coupled to the switch.

In one example, the boost converter acts as a low-side switch, a first transistor (eg, a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT), etc.) and a second transistor that functions as a high-side switch. It is preferable to include a transistor. The low-side switch is coupled to the inductor and ground, and the high-side switch is coupled to the output (preferably the load of the converter) and the inductor. Typically, the low-side and high-side switches are controlled via a pulse width modulation (PWM) signal provided by a controller coupled to the switch. The PWM signal is a time-varying square wave that alternates between low and high levels. As a result of this alternating transition, the low-side switch and the high-side switch are switched on and off alternately.

Continuing in the above example, the low-side switch can be on while the PWM signal is at a high level, and the PWM signal transition forms a high level at a low level, which remains on until the low-side switch is turned off. could be. At the same time, the high side switch is on while the low side switch is off. More specifically, when the low-side switch is on, the input voltage source uses an inductor and a low-side switch to form a short circuit to ground. Therefore, a current flows through the inductor, which becomes the energy stored in the inductor by generating a magnetic field. When the low-side switch is off, the magnetic field disappears and the stored energy in the inductor flows through the high-side switch to the load of the voltage converter (such as the output capacitor coupled at the output voltage node). Ideally, if the low-side and high-side switches are switching fast enough, the switching loss can be ignored, the voltage converter can keep the voltage level at the output voltage node constant, and the voltage at the output voltage node. The level is higher than the input voltage.

However, in practice, switching loss due to "Miller time" can unfavorably cause power loss, especially while switches such as low-side switches are switched on and off, in terms of efficiency, etc. of voltage converters. It can affect performance. In general, the mirror time results from the unintended discharge path of the switch. For example, when a MOSFET is mounted as a switch, the MOSFET contains a parasitic capacitance between the drain and gate terminals of the MOSFET. As such, this parasitic capacitance induces leakage or gate currents, which can increase the amount of time required for the switch to turn on or off. Traditionally, the circuit is coupled to a switch and configured to adjust (eg, reduce) the mirror time. However, such conventional circuits generally include a fixed voltage node coupled to the gate terminal of the MOSFET switch, which can cause the mirror time to vary significantly according to the fluctuating inductor current. In other words, there can be large fluctuations in the mirror time due to the inductor current. Fluctuations in mirror time while the high side switch is off can be particularly significant and are undesirable.

As described below, embodiments of the present invention are directed to DC-DC converters that include an adaptive controller coupled to a switch in the DC-DC converter. The adaptive controller further includes an adaptive voltage node that can be used to provide an adaptive voltage level that varies with the magnitude of the inductor current. By implementing an adaptive controller, fluctuations in the mirror time that change with the inductor current can be reduced while the low-side switch is switched off. Also, a shorter amount of time to switch off the low-side switch can be advantageously achieved by implementing the disclosed adaptive controller in a DC-DC converter. DC-DC converters, preferably DC-DC boost converters according to the present disclosure, operate with adaptive controllers illustrated and disclosed as described below in connection with FIG. Other architectures are possible.

FIG. 1 shows a top level block diagram illustrating a DC-DC boost converter 100 according to various embodiments. Boost converter 100 includes input voltage source _{V in,} the inductor _{L 1,} the output voltage node _{V out,} an output capacitor _{C 1,} the adaptive controller 102, and two switches _{M 1} and _{M 2.} More specifically, the adaptive controller 102 is _{configured to receive a feedback signal (such as V fb ) from the output voltage node V out} and is based on the feedback signal (such as a current and / or voltage signal). Provides a PWM signal 101 to alternately switch on and off switches M ₁ and M _2. In a preferred embodiment, the switch M ₁ is referred to as a low-side switch and the switch M ₂ is referred to as a high-side switch that operates temporally exclusively with the low-side switch M _1. In other words, while switch M ₁ is on, switch M ₂ is generally off and vice versa, and both of these switches are not on at the same time.

As described above, while the low-side switch _{M 1} is turned on, the input voltage source _{V in,} the inductor _{L 1,} and the switch _{M 1} forms a short circuit. Accordingly, energy, the inductor L ₁ inside begins to store the current flowing through the inductor L ₁ is increased. While the switch M ₁ is off, _{the energy stored inside the inductor L 1} begins to discharge and current _{flows through the inductor L 1} to the load of the boost converter 100 (output capacitance C ₁ etc.) and the inductor. This leads to a reduction in current.

Referring again to FIG. 1, while the switch M ₁ is turned off via the PWM signal, depending on the current flowing through the inductor L _1, switch M ₁ is immediately turned off due to the influence of the mirror time It may not be done. In this regard, adaptive controller 102, so as to actually turn off the switch M ₁ in a shorter time period, to adjust the speed for turning on and off with respect to the current flowing through the inductor L ₁ (i.e., mirror Includes a circuit for changing the time). In one example, the amount of time for turning off the switch M ₁ may be inversely proportional to the load current (i.e., current flowing through the inductor L _1). That is, as the load current is low, the amount of time for turning off the switch M ₁ is prolonged. Moreover, large variations in the amount of time for turning off the switch M ₁ may be present. As such, this may be undesirable for the boost converter 100 under low current conditions and / or wide range load current conditions. More specifically, when only the boost converter 100 a low level of current that is to operate under favorable conditions are intended, boost converter, while the switch M ₁ is a transition from on to off, the efficiency problems Can suffer.

FIG. 2 shows an exemplary circuit element 200 of the boost converter 100 according to various embodiments. As shown in FIG. 2, the adaptive controller 102 further includes two blocks 202 and 204. More specifically, the block 202 is configured to receive the feedback signal V _{fb from the output voltage node V out to further control the switches M 1} and M ₂ based on the feedback signal and the inductor current. The PWM signal 201 is provided to provide the block 204 with an adaptive current i- _{adp 203 proportional to.} Based on adaptive current 203, block 204 is coupled to block 202 is configured to provide an adaptive voltage node _{V adp,} adaptive voltage node _{V adp,} the speed for turning off the switch _{M 1} (i.e., It is useful for controlling the mirror time). Further, circuitry 200 further includes a sensing controller _{M S} that is coupled to high-side switch _{M 2.} Sensing controller _{M S} is configured to sense a high-side switch _{M 1} and the low-side switch _{M 2} connected to the common node voltage / current level at _{V SW (such} as _{V sns).}

According to a preferred embodiment, as shown in circuit element 200, the boost converter 100 further includes a voltage divider (ie, R ₀ and R ₁ ), for the voltage divider to _divide the voltage level at the output voltage node V out. , And the feedback signal V _fb is used to equalize the divided signal. That is, V _fb is less than the voltage level at the output voltage node V _{out and} is based on the register voltage divider ratio (R ₁ / (R ₀ + R _1, etc.). In an alternative embodiment, to implement the boost converter 200. If the absence of a voltage divider may be desired by the user, the feedback signal V _fb is equal to the voltage level at the output voltage node V _out.

Further referring to FIG. 2, the block 202 further includes an error amplifier 206, a comparator 208, and a control logic 210. The error amplifier 206 includes two input terminals configured to receive signals forming a _{V fb} and a reference voltage V _{REF, respectively.} With a capacitor C ₀ which is coupled to the output of the error amplifier, the error amplifier 206 is configured to provide an adaptive current i _dap proportional to the inductor current. As shown in FIG. 2, the adaptive current preferably flows through each of the _{transistors M 14} and M _13. In addition, the comparator 208 causes the coupled control logic 210 to generate a corresponding PWM signal with a duty cycle to synchronously control the switching behavior of _{switches M 1} and M _{2 , V out} and V _sns. Is configured to compare.

Continuing to refer to FIG. 2, block 204 further high coupled constant voltage node _{V x,} the sample and hold circuit coupled to the constant voltage node _{V x} (such as SW ₀ and SW _1), the high-side switch _{M 2} including side driver 204-HS, and a low-side driver 204-LS is coupled to the low side switch _{M 1.} The drivers 204-LS and 204-HS are configured to buffer the received PWM signal and increase the drive speed of the low-side and high-side switches, respectively. Preferably, the M ₄ and the M ₅ connected in series function as the first inverter of the high-side driver 204-HS, and the M ₃ together with the M ₆ is a second inverter connected in series with the first inverter. Functions as. Similarly, in the low-side driver 204-LS, M ₇ and M ₉ form a first inverter, and M ₈ and M ₁₀ form a second inverter connected in series with the first inverter. In a preferred implementation, M _{1 to} M ₁₀ are MOSFETs. In a further preferred embodiment, the low-side driver 204-LS may further _include a MOSFET M _10A that is coupled to _{M 10.} As shown in FIG. 2, the gate terminal of M _10A is connected to the voltage node V _1, the voltage node V ₁ was, is connected to the gate terminal of the low-side switch M _1.

More specifically, the low-side driver 204-LS further includes an adaptive drive circuit coupled to the first and second inverters, which comprises two transistors M ₁₁ and M ₁₂ and a switch M ₁ . include. As shown in the circuit element 200, the drain terminal _{of the transistor M 11 is connected to the gate terminal of the switch M 1} , and the gate terminal of the transistor M ₁₁ is coupled to the output voltage node V _out via the transistor M ₈ . The transistor M ₁₂ is connected in series with the source terminal of the transistor M ₁₁ , and the gate terminal of the _{transistor M 12 is connected to the adaptive voltage node V adp} .

に等しく、この式において、Ｖ_ｔｈはスイッチＭ_１の閾値電圧であり、Ｋは比例定数である。また、トランジスタＭ_１１のゲート端子は、ほぼ一定の出力電圧ノードＶ_ｏｕｔに結合されるので、ほぼ一定値の導通抵抗Ｒ_{ｏｎ_Ｍ１１}となる。一方、トランジスタＭ_１２のゲート端子は、インダクタ電流ｉ_Ｌに従って変化するアダプティブ電圧ノードＶ_ａｄｐに結合されるため、導通抵抗Ｒ_{ｏｎ＿Ｍ１２}は、

として導出され得る。好ましい一実施例において、アダプティブ電圧ノードＶ_ａｄｐは、定電圧ノードＶ_ｘに接続される抵抗Ｒ_４の値を選択することを介して制御され得、即ち、Ｖ_ａｄｐ＝Ｖ_ｘ−Ｋｉ_ＬＲ_４である。 According to a preferred embodiment, all of the inductor current (ie, i _L as shown in 200) flows to ground through the switch M _{1 while the switch M 1 is turned off.} More specifically, the switch M ₁ is because it is preferable to operate in the saturation region of the MOSFET, the conductance current i _D that varies slightly exists. Therefore, based on the law of current, i _L = i _D + i _G , and _{how fast the current goes to zero via M 1} (that is, the _{speed at which switch M 1} is turned off) fluctuates in _{i G.} largely dependent obtained, _{i G,} via the parasitic capacitance _{C gd} of the switch _{M 1,} a discharge current flowing through the transistor _{M 11} and _{M 12} are connected in series. Transistors M ₁₁ and M ₁₂ preferably operate in the linear region of the MOSFET. Further, the discharge current i _G can _{be derived as V gs_M1} / (R _{on_M11} + R _{on_M12} ), and in this equation, V _{gs_M1} , R _{on_M11} , and R _{on_M12} are voltage drops between the gate and source terminals of the switch M _{1, respectively.} , Represents the conduction resistance to the transistors M ₁₁ and M _12. During the switching-off of the switch _{M 1, V gs_M1} is

In this equation, V _th is the threshold voltage of switch M ₁ and K is a constant of proportionality. Further, since the gate terminal of the _{transistor M 11 is coupled to the output voltage node V out} which is substantially constant, the conduction resistance R _{on_M 11 has} a substantially constant value. On the other hand, since the gate terminal of the _{transistor M 12} is coupled to the adaptive voltage node V _{adp which changes according to the inductor current i L} , the conduction resistor R _{on_M 12} is set.

Can be derived as. In one preferred embodiment, the adaptive voltage node _{V adp} may be controlled through the selection of the value of the resistor _{R 4} is connected to a constant voltage node _{V x, i.e., V adp = V x -Ki L} R 4 Is.

Also, while the switch M ₁ is turned off, in particular, to operate the switch M ₁ in a saturated mode, if the voltage level at the voltage node V ₁ higher than the voltage level at the gate terminal of the low-side switch M _1, M ₁₀ and M _10A can increase the rate at which i _{L is discharged.} More specifically, when the voltage level to reduce the gate terminal of the switch M _1, while the M ₁ and M _10A can be switched to the saturation region from the linear region, to obtain takes over the function of M ₁₂ discharges the inductor current i _L ..

In summary, via the user to select the value of the resistor R ₄ in accordance with the inductor current to operate the boost converter 100 is intended, the variation of velocity which varies with the inductor current can be optimized. The amount of time for switching off the switch M ₁ can be reduced by optimized values of the resistor R _4. Once _{the value of R 4} is determined, the voltage level at the adaptive voltage node V _adp is determined according to _{the inductor current i L.} Based on the above equation V _{gs_M1} / (R _{on_M11} + R _{on_M12} ), the speed and velocity variation can be optionally adjusted by the user for suitable application.

With further reference to the circuit element 200, SW ₀ and SW ₁ samples the voltage level, so as to generate an adaptive voltage _V x _-Ki L _{R 4} and holds the voltage level sampled, at the same time switched on and off It is configured to. More specifically, when these switches are on, SW ₀ and SW ₁ are coupled to the constant voltage node V _x. When these switches are off, SW ₀ and SW ₁ are coupled to the adaptive voltage node V _adp. Since the switches SW ₀ and SW ₁ are integrated with the capacitor C ₁ , undesired DC current consumption can be avoided while the switch M _{1 is off.}

3, according to various embodiments, the switch M ₁ of the boost converter 100 shows a flowchart 300 for determining the amount of time to switch off. The flowchart 300 starts by turning off the main switch (that is, the low side switch M _{1) of the boost converter 100 in the block 302.} In a preferred embodiment, turning off the main switch can be controlled by a PWM signal provided by the adaptive controller 102. While the switch M ₁ is turned off, the inductor current flows to ground through the switch M ₁ and combined low-side driver 204-LS, combined low-side driver 204-LS is preferably a current i _G Acts as a discharge path for.

Flowchart 300 continues by providing in _{block 304 the voltage level V adp} at the adaptive voltage node that should be inversely proportional to the inductor current. The adaptive voltage node is preferably coupled to the gate of the transistor in the low-side driver 204-LS. As described above, it is preferable that the conduction resistance _{of the transistor M 12} , which is one of the parameters for determining the amount of time for switching off the _{main switch M 1, also changes with the inductor current.}

In block 306, based on the voltage level of an adaptive voltage node V _adp, the amount of time for switching off the main switch M ₁ is to keep the gate terminal of the transistor M _11, the voltage level at the output voltage node V _out Determined by. As described above, _{the conduction resistance of the transistor M 11} is a very slight change even if it changes with the inductor current. In a preferred example, the amount of time to switch off the _{main switch M 1 is primarily how fast the current i G} goes to zero (ie, how much current i _G is in the discharge path containing the _{transistors M 11} and M _12). It depends on whether it passes through). More specifically, transistor characteristics (M such ₁₂₎ (conduction resistance, etc.), varies with the voltage level of an adaptive voltage node. Therefore, providing an adaptive voltage node whose voltage level changes according to the inductor current can advantageously determine the speed for switching off the main switch M1.

The above description is meant to illustrate the principles of the invention and various examples. A number of changes and variations will be apparent to those skilled in the art if the above disclosure is fully understood. The claims described below are intended to be construed to include such changes and modifications.

Claims (20)

It ’s a circuit,
With switch nodes
A first switch having a control terminal, a first terminal coupled to the switch node, and a second terminal coupled to a ground terminal.
A second switch having a control terminal, a first terminal coupled to the switch node, and a second terminal coupled to the output voltage node.
A control circuit including a high-side driver coupled to a control terminal of the second switch and a low-side driver, wherein the low-side driver is
An adaptive voltage node that receives an adaptive voltage and whose adaptive voltage changes according to a current flowing from the switch node to the first switch.
A first transistor having a first terminal coupled to a control terminal of the first switch and a second terminal,
A second transistor having a control terminal coupled to the adaptive voltage node, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the ground terminal. When,
With the control circuit including
Including the circuit. The circuit according to claim 1.
The first transistor includes a first NMOS transistor having a drain terminal as the first terminal and a source terminal as the second terminal.
A circuit in which the second transistor includes a second NMOS transistor having a gate terminal as the control terminal, a drain terminal as the first terminal, and a source terminal as the second terminal. The circuit according to claim 1.
A circuit in which the first transistor further comprises a control terminal configured to receive an output voltage during the off time of a pulse width modulation (PWM) signal. The circuit according to claim 3.
The low-side driver
A third terminal having a control terminal configured to receive a PWM signal, a first terminal coupled to the output voltage node, and a second terminal coupled to the control terminal of the first transistor. With a transistor
Control of the control terminal coupled to the second terminal of the third transistor, the first terminal coupled to the output voltage node, the first terminal of the first transistor, and the first switch. A fourth transistor having a second terminal coupled to the terminal,
Further included, circuit. The circuit according to claim 4.
The low-side driver
A fifth transistor having a first terminal coupled to the output voltage node and a second terminal,
A voltage having a first resistor coupled between the second terminal of the fifth transistor and a divider node and a second resistor coupled between the divider node and the ground terminal. A voltage divider that is a divider and whose divider node is selectively coupled to the adaptive voltage node based on the PWM signal.
A circuit that further includes. The circuit according to claim 5.
The low-side driver further adds a third switch coupled between the divider node and the adaptive voltage node and a fourth switch coupled between the divider node and the second resistor. Including
A circuit in which the PWM signal is configured to alternately open and close the third and fourth switches. The circuit according to claim 1.
An adaptive current circuit coupled to the switch node and configured to provide an adaptive current proportional to the current.
An adaptive voltage circuit coupled to the adaptive current circuit and configured to provide the adaptive voltage according to the adaptive current.
A circuit that further includes. The circuit according to claim 7.
The adaptive current circuit includes a sensing controller coupled to the switch node and a current circuit coupled to the sensing controller to provide the adaptive current.
Wherein and a adaptive voltage circuit a constant voltage node and the sample-and-hold circuit, the sample-hold circuit, a capacitor coupled between said ground terminal the adaptive voltage node, the said constant voltage node capacitor A circuit comprising a first MOS switch coupled between and a second MOS switch coupled between the constant voltage node and the current circuit. The circuit according to claim 8.
The current circuit has a first MOS transistor coupled between the sensing controller and the ground terminal, and a second MOS transistor coupled between the second MOS switch and the ground terminal. A circuit comprising, wherein the first MOS transistor has a gate terminal coupled to the gate terminal of the second MOS transistor. The circuit according to claim 9.
With input voltage terminals configured to be coupled to the input voltage source,
An inductor coupled between the input voltage terminal and the switch node,
A PWM signal circuit configured to provide a PWM signal to the high-side driver and the low-side driver, wherein the PWM signal is based on an output voltage.
Including
The low-side driver
A third transistor having a control terminal for receiving the PWM signal, a first terminal coupled to the output voltage node, and a second terminal coupled to the control terminal of the first transistor.
A control terminal coupled to the second terminal of the third transistor, a first terminal coupled to the output voltage node, and a second terminal coupled to the control terminal of the first switch. The fourth transistor that has
A circuit that further includes. The circuit according to claim 10.
A circuit in which the first and second MOS switches are configured to switch ON and OFF at the same time according to the PWM signal. A control circuit for controlling the first and second switches of a voltage converter.
A first driver that drives the first switch coupled between a common node and a reference voltage node in response to a pulse width modulation (PWM) signal, the control terminal of the first switch and the said. The first driver, which includes an adaptive drive circuit coupled to and from a reference voltage node, wherein the adaptive drive circuit functions as a discharge circuit based on the adaptive voltage.
A second driver that drives the second switch coupled between the voltage output node and the common node in response to the PWM signal.
A first adaptive voltage generator coupled to the voltage output node that generates the adaptive voltage in response to the PWM signal and provides the adaptive voltage to the adaptive voltage node coupled to the adaptive drive circuit. A first resistor having the terminal, a third switch coupled between the second terminal of the first resistor and the adaptive voltage node, the adaptive voltage node and the reference voltage node. With the adaptive voltage generator, including a capacitor coupled between
Including the control circuit. The control circuit according to claim 12.
The adaptive drive circuit is coupled between a first transistor having a first terminal coupled to a control terminal of the first switch, a second terminal of the first transistor, and a reference voltage node. A control circuit comprising a second transistor to be coupled, wherein the second transistor has a control terminal coupled to the adaptive voltage node. The control circuit according to claim 13.
A control circuit having a control terminal in which the first transistor is coupled to the voltage output node. The control circuit according to claim 14.
The first driver is configured to buffer the PWM signal in the control terminal of the first switch.
A control circuit in which the second driver buffers the PWM signal in the control terminal of the second switch. The control circuit according to claim 14.
A second inverter in which the first driver is coupled between a first inverter having an input terminal for receiving the PWM signal, an output terminal of the first inverter, and a control circuit of the first switch. A control circuit that further includes. The control circuit according to claim 16.
The second inverter has a third transistor coupled between the voltage output node and the control terminal of the first switch, and a first terminal coupled to the control terminal of the first switch. The fourth transistor includes a fifth transistor coupled between the second terminal of the fourth transistor and the reference voltage node, and the fifth transistor controls the first switch. A control circuit having a control terminal coupled to the terminal. The control circuit according to claim 17.
The voltage converter comprises an inductor coupled between the voltage source and the common node.
A control circuit in which the adaptive voltage is proportional to the inductor current flowing through the first switch. The control circuit according to claim 12.
A fourth switch in which the adaptive voltage generator has a first terminal coupled to a second terminal of the first resistor, a second terminal of the fourth switch, and a reference voltage node. Further includes a second resistor coupled between
A control circuit in which the third and fourth switches are simultaneously controlled by the PWM signal. The control circuit according to claim 19.
The voltage converter comprises an inductor coupled between the voltage source and the common node.
A control circuit in which the adaptive voltage is proportional to the inductor current flowing through the first switch.

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