JP6626267B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a cascode circuit, and more particularly to a nitride semiconductor device.

  In recent years, power semiconductors are important in the fields of IT equipment such as servers and personal computers, white goods such as air conditioners, power conditioners used in solar power generation systems, electric vehicles such as hybrid vehicles, trains and power transmission systems. Plays a role.

  Above all, devices using GaN (gallium nitride) are expected to have significantly higher withstand voltage, lower resistance and higher frequency than Si devices of current materials due to the superior properties of GaN.

  One of the features of the GaN transistor is to increase the frequency. One reason that the switching frequency can be improved is that the mobility of electrons serving as carriers is high. Generally, a GaN transistor employs a “HEMT (High Electron Mobility Transistor) structure” in which an AlGaN layer and a GaN layer are joined, and a “two-dimensional electron gas” is generated near an interface between the two layers. Since electrons can move at a high speed in the “two-dimensional electron gas”, the switching speed can be increased.

  Therefore, applications of the GaN transistor to switching power supply devices and the like are rapidly expanding. However, since the GaN transistor is mainly a normally-on type switching element, a gate drive circuit (a gate drive for a normally-off operation) for driving a normally-off type switching element generally used in a switching power supply or the like. Circuit) cannot be applied.

  Therefore, when the normally-on switching element is to be normally off, the cascode circuit is configured by connecting the drain of the normally-off switching element to the source of the normally-on switching element. Can be considered. When such a cascode circuit is configured, the normally-on type switching element is turned off similarly to the normally-off type switching element when it is turned off by a normally-off operation gate drive circuit. The gate drive circuit for normally-off operation can be applied as it is.

  By the way, when the power semiconductor is used in an inverter circuit or the like, the transistor element may be short-circuited due to abnormal fluctuation of a load or a power supply depending on a use environment. Therefore, in the case of the power semiconductor, it is required that the transistor does not break even in the short-circuit state during the time (short-circuit time) until the protection circuit operates in the short-circuit state.

  However, at the time of the short circuit, a large current flows in a state where a high voltage is applied to the transistor, so that energy of voltage × current is applied. There is a problem of causing destruction.

  In particular, as described above, the GaN transistor can have a significantly higher breakdown voltage and lower resistance than the Si device due to its superior material properties, and the short-circuit time increases as the chip area decreases. Is a major issue. Therefore, suppression of heat generation during a short circuit has become important.

  As a circuit capable of suppressing heat generation at the time of the short circuit, a saturation current limiting circuit of a power transistor disclosed in US Patent Application Publication No. 2014/0055192 (Patent Document 1) and US Pat. No. 8,624,662 (Patent Document 2) 3) discloses a semiconductor electronic structure and circuit.

  FIG. 5 is a circuit diagram showing a circuit configuration disclosed in Patent Document 1. This circuit illustrates a part of a specific circuit of the power transistor 1 that limits the saturation current.

  The power transistor 1 includes a normally-on GaN transistor M1 having a first drain D1, a first source S1, and a first gate G1. The power transistor 1 includes a normally-off MOS transistor M2 having a second drain D2, a second source S2, and a second gate G2. The first source S1 of the normally-on transistor M1 and the second drain D2 of the normally-off transistor M2 are connected, and the normally-on transistor M1 and the normally-off transistor M2 are connected in series.

A current limiting circuit 2 is connected between the first terminal T1 connected to the first gate G1 and the second terminal T2 connected to the second source S2. The current limiting circuit 2 comprises at least one passive circuit element such as a resistor and / or at least one active circuit element having a maximum steady state voltage V _GS (gate-source voltage) lower than 0V. As an example, it is composed of a diode 3. Thus, the normally-on transistor M1 and the normally-off transistor M2 are cascode-connected.

  FIG. 6 is a circuit diagram showing a circuit configuration disclosed in Patent Document 2. This circuit has a circuit configuration for driving a load 5, and similarly to the circuit configuration disclosed in Patent Document 1, a high-voltage depletion mode GaN transistor (normally on transistor) 7 connected in series with each other. A low voltage enhancement mode MOS transistor (normally off transistor) 8. The gate of the depletion mode transistor 7 and the source of the enhancement mode transistor 8 are connected via a negative bias power supply 9. As described above, the normally-on transistor 7 and the normally-off transistor 8 are cascode-connected, and the negative bias power supply 9 is connected between the gate of the normally-on transistor 7 and the source of the normally-off transistor 8. This limits the saturation current.

  Generally, as shown in FIG. 7, the cascode circuit 11 has, for example, an external drain terminal Dc, an external source terminal Sc, and an external gate terminal Gc as external terminals. In the cascode circuit 11, a normally-on first transistor Q11 and a normally-off second transistor Q12 are cascode-connected, and the gate G12 of the second transistor Q12 and the external gate terminal Gc are connected to each other. It is connected via a resistor Rg. Further, the gate G11 of the first transistor Q11 and the external source terminal Sc are connected via the resistor R11.

Here, a power supply and a load are connected to the external drain terminal Dc, and the external source terminal Sc is fixed to the GND potential. When an ON input signal is input to the external gate terminal Gc, if the current flowing through the transistor Q11 and the transistor Q12 is ID, the gate-source voltage of the GaN transistor Q11 is Vgs, the threshold voltage is Vth, Assuming that the transconductance in the saturation region is gm, the current ID can be experimentally represented by the following equation.
ID ≒ gm × (Vgs−Vth)

  First, the gate-source voltage Vgs will be considered. The potential of the gate G11 of the GaN transistor Q11 is 0V, and when the ON resistance of the MOS transistor Q12 is sufficiently low, the potential of the source S11 of the GaN transistor Q11 becomes substantially 0V, and Vgs ≒ 0V.

Therefore, the current ID is
ID ≒ gm × (−Vth)
Assuming that the threshold voltage of the normally-on type GaN transistor Q11 is, for example, -6V, the current ID becomes
ID ≒ 6 x gm
Is calculated.

On the other hand, for example, in the circuit configuration disclosed in Patent Document 1 shown in FIG. 5, the gate-source voltage V _{GS of the} normally-on transistor M1 is negatively biased by the current limiting circuit 2. Similarly, in the circuit configuration disclosed in Patent Document 2 shown in FIG. 6, the power supply 9 causes the gate-source voltage V _{GS of the} normally-on transistor 7 to be a negative bias.

Here, the gate-source voltage Vgs in the circuit configurations disclosed in Patent Document 1 and Patent Document 2 is, for example, -2V. Then, the saturation current flowing through the normally-on transistor M1 and the normally-off transistor M2 in Patent Document 1 and the saturation current Idsat flowing through the normally-on transistor 7 and normally-off transistor 8 in Patent Document 2 are:
Idsat ≒ gm × (Vgs−Vth) = gm × (−2 + 6) = 4 × gm
Is calculated by

  That is, it can be seen that the saturation current can be reduced by about 30% in the circuit configurations disclosed in Patent Document 1 and Patent Document 2 as compared with the general cascode circuit shown in FIG.

  Therefore, in the cascode circuit having the circuit configuration in Patent Documents 1 and 2, the saturation current can be reduced by applying a negative bias as the gate-source voltage Vgs in the normally-on GaN transistor. .

US Patent Application Publication No. 2014/0055192 U.S. Pat. No. 8,624,662

  However, the conventional circuit configurations disclosed in Patent Documents 1 and 2 have the following problems.

  That is, in the cascode circuits disclosed in Patent Documents 1 and 2, a negative bias is always applied as the gate-source voltage Vgs of the normally-on GaN transistor during the switching operation. Therefore, there is a problem that the ON resistance of the GaN transistor always increases.

Generally, when a normally-on GaN transistor and a normally-off MOS transistor are cascode-connected, the on-resistance of the GaN transistor is Ron (GaN), and the on-resistance of the MOS transistor is Ron (MOS).
Ron (GaN) >> Ron (MOS)
(For example, Ron (GaN) is about 3 to 10 times Ron (MOS)).

  Therefore, when a cascode circuit is formed, the ratio of the cascode connection of the GaN transistor and the MOS transistor to the entire on-resistance is mostly a GaN transistor, and the ratio of the MOS transistor is small. The reason is as follows.

That is, since a high voltage is applied to the GaN transistor, it is necessary to design the drift length to be long to achieve a high breakdown voltage. However, for a GaN transistor which is a lateral device, an increase in the drift length is directly reflected in an increase in the on-resistance and an increase in the number of chips. On the other hand, the MOS transistor can be designed to have a short drift length because no high voltage is applied, and the chip area can be reduced by using a vertical structure or the like. as a result,
Ron (GaN) >> Ron (MOS)
It becomes.

  In the circuit configurations of Patent Literature 1 and Patent Literature 2, it is possible to reduce the saturation current. However, as described above, the on-resistance of the GaN transistor, which has a high proportion of the on-resistance of the entire cascode connection, always increases during the switching operation. As a result, the on-resistance of the entire cascode connection increases during the switching operation. There is a problem that it always grows.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of suppressing the increase in on-resistance to a minimum, reducing the saturation current and suppressing the heat generation during the short-circuit time, and greatly increasing the short-circuit time. To provide.

In order to solve the above problems, a semiconductor device according to the present invention includes:
A normally-on type first switching element having a source, a drain, and a gate;
A normally-off type second switching device having a source, a drain, and a gate, wherein the drain is electrically connected to the source of the first switching device to form a cascode circuit with the first switching device; Element,
An overcurrent detection circuit connected in parallel with the second switching element and detecting an overcurrent flowing through the cascode circuit;
The overcurrent detection circuit is characterized in that when the value of the current flowing through the cascode circuit is equal to or greater than a predetermined overcurrent value, the current flowing through the cascode circuit is limited. I do.

In one embodiment of the semiconductor device,
The overcurrent detection circuit,
A normally-off type third switching element which is connected in parallel with the second switching element and has a source, a drain, and a gate;
An overcurrent detection resistor connected between the source of the third switching element and the source of the second switching element;
A normally-off type fourth switching element having a source, a drain, and a gate;
The drain of the fourth switching element is commonly connected to the gate of the third switching element and the gate of the second switching element;
The gate of the fourth switching element is commonly connected to the source of the third switching element and one end of the overcurrent detection resistor;
The source of the fourth switching element is commonly connected to the other end of the overcurrent detection resistor and the source of the second switching element;
The gate width W3 of the third switching element is set to be 1 / n (n> 1) times the gate width W2 of the second switching element.

In one embodiment of the semiconductor device,
An external gate terminal commonly connected to the gate of the third switching element, the gate of the second switching element, and the drain of the fourth switching element;
The overcurrent detection circuit,
A gate resistor is connected between the external gate terminal and the drain of the fourth switching element.

In one embodiment of the semiconductor device,
The second switching element, the third switching element, and the fourth switching element are formed on the same chip.

In one embodiment of the semiconductor device,
The first switching element, the second switching element, the third switching element, and the fourth switching element are included in the same package.

  As is clear from the above, the semiconductor device according to the present invention is configured such that when the overcurrent detection circuit detects that the current value flowing through the cascode circuit has become equal to or greater than a predetermined overcurrent value set in advance. The on-resistance of the cascode circuit is increased, and the flowing current is limited. Therefore, the amount of heat generated during the short circuit time can be significantly reduced.

  In that case, the overcurrent detection circuit increases the on-resistance of the cascode circuit to limit the flowing current only when the current value flowing through the cascode circuit is equal to or greater than the overcurrent value. Therefore, the ON resistance of the cascode circuit does not increase during normal operation.

  That is, according to the semiconductor device of the present invention, it is possible to suppress the amount of heat generated during the short-circuit time by reducing the saturation current while minimizing the increase in the on-resistance, and to significantly increase the short-circuit time. .

FIG. 1 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to a third embodiment of the present invention. FIG. 4 is a diagram showing a time change of a current flowing through the nitride semiconductor device of FIGS. 2 and 3. FIG. 5 is a circuit diagram of a conventional saturation current limiting circuit of a power transistor. FIG. 6 is a circuit diagram of a conventional semiconductor electronic circuit. FIG. 7 is a circuit diagram of a general cascode circuit.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

[First Embodiment]
FIG. 1 is a circuit diagram of a nitride semiconductor device 21 as the semiconductor device of the first embodiment.

  This nitride semiconductor device 21 has, for example, an external drain terminal Dc, an external source terminal Sc, and an external gate terminal Gc as external terminals.

  The nitride semiconductor device 21 is generally composed of a normally-on type first transistor Q1, a normally-off type second transistor Q2, and an overcurrent detection circuit 22. The normally-on type first transistor Q1 is, for example, a GaN transistor. The normally-off second transistor Q2 is, for example, a MOS transistor. The first transistor Q1 and the second transistor Q2 are examples of the first switching element and the second switching element.

  An external drain terminal Dc is connected to the drain D1 of the first transistor Q1. The source S1 of the first transistor Q1 is connected to the drain D2 of the second transistor Q2, and the external source terminal Sc is connected to the source S2 of the second transistor Q2. Further, a resistor R1 is connected between the gate G1 of the first transistor Q1 and the source S2 of the second transistor Q2. Thus, a cascode circuit is formed by the first transistor Q1 and the second transistor Q2 connected in series. The overcurrent detection circuit 22 is connected in parallel with the second transistor Q2.

  Further, the gate G2 of the second transistor Q2 is connected to the external gate terminal Gc via the overcurrent detection circuit 22.

  Hereinafter, an example of an operation in which the flowing current is limited when an overcurrent flows in the nitride semiconductor device 21 having the above configuration will be described. Here, it is assumed that a power supply (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed at the GND potential. Further, when an ON input signal is input to the external gate terminal Gc, a current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is defined as ID.

  The overcurrent detection circuit 22 is connected to the drain D2 and the source S2 of the second transistor Q2, and can detect the current ID flowing through the second transistor Q2. When the detected current value of the current ID becomes equal to or more than the preset overcurrent value, the overcurrent detection circuit 22 lowers the potential of the ON signal from the external gate terminal Gc to reduce the potential of the second transistor Q2. To the gate G2.

  Thus, the overcurrent detection circuit 22 reduces the potential of the gate G2 of the second transistor Q2 when the current value of the current ID flowing through the cascode circuit becomes equal to or greater than a predetermined overcurrent value. Is controlled. As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 decreases.

  On the other hand, the overcurrent detection circuit 22 does not perform the control operation in a normal operation in which the current value of the current ID flowing through the cascode circuit is smaller than a predetermined overcurrent value. The ON resistance of the second transistor Q2 does not increase. Therefore, the on-resistance of the entire cascode connection does not increase.

  As described above, in the first embodiment, in the nitride semiconductor device 21 having the cascode circuit in which the normally-on GaN first transistor Q1 and the normally-off MOS second transistor Q2 are connected in series. An overcurrent detection circuit 22 for detecting a current ID flowing through the second transistor Q2 is connected in parallel with the second transistor Q2.

  The overcurrent detection circuit 22 reduces the potential of the gate G2 of the second transistor Q2 when the current value of the current ID flowing through the nitride semiconductor device 21 becomes equal to or greater than a preset overcurrent value. Is controlled. Therefore, the on-resistance of the second transistor Q2 increases, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 21 of the first embodiment, the amount of heat generated during the short circuit time can be significantly improved.

  In this case, the saturation current is limited only when the predetermined overcurrent is detected by the overcurrent detection circuit 22. Therefore, the ON resistance of the entire cascode connection does not increase during normal operation.

  That is, according to the nitride semiconductor device 21 of the first embodiment, while suppressing the increase in the on-resistance to a minimum, the saturation current is reduced to suppress the heat generation during the short-circuit time, and the short-circuit time length is significantly increased. The increase can be achieved.

[Second embodiment]
FIG. 2 is a circuit configuration diagram of a nitride semiconductor device 31 as a semiconductor device according to a second embodiment of the present invention.

  The nitride semiconductor device 31 according to the second embodiment relates to a specific configuration of the overcurrent detection circuit 22 according to the first embodiment. Therefore, in the first embodiment, the same members as those shown in FIG. 1 are denoted by the same reference numerals as in the first embodiment, and detailed description is omitted.

  The overcurrent detection circuit 32 in the nitride semiconductor device 31 includes a normally-off third transistor Q3 and a fourth transistor Q4. The third and fourth transistors Q3 and Q4 are, for example, MOS transistors. Here, the third transistor Q3 and the fourth transistor Q4 are examples of the third switching element and the fourth switching element.

  The third transistor Q3 is connected in parallel with the second transistor Q2 via an overcurrent detection resistor Rgs4, and the drain D3 of the third transistor Q3 is commonly connected to the drain D2 of the second transistor Q2. . Further, the gate G3 of the third transistor Q3 and the gate G2 of the second transistor Q2 are commonly connected to an external gate terminal Gc. Here, the gate width W3 of the third transistor Q3 is 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

  The drain D4 of the fourth transistor Q4 is commonly connected to the gate G3 of the third transistor Q3 and the gate G2 of the second transistor Q2. The drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to an external gate terminal Gc. Further, the source S3 of the third transistor Q3 and the gate G4 of the fourth transistor Q4 are connected.

  One end of the overcurrent detection resistor Rgs4 is connected to the source S3 of the third transistor Q3 and the gate G4 of the fourth transistor Q4, while the other end of the overcurrent detection resistor Rgs4 is connected to the source S4 of the fourth transistor Q4. And the source S2 of the second transistor Q2. Thus, the other end of the overcurrent detection resistor Rgs4, the source S4 of the fourth transistor Q4, and the source S2 of the second transistor Q2 are connected to the external source terminal Sc.

  Hereinafter, the operation of limiting the current when an overcurrent flows in nitride semiconductor device 31 having the above configuration will be described. Here, it is assumed that a power supply (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed at the GND potential. When an ON input signal is input to the external gate terminal Gc, the current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is ID, and the current flowing through the third transistor Q3 is ID3. The current flowing through the fourth transistor Q4 is ID4.

For example, when the magnification n of the gate width W2 of the second transistor Q2 with respect to the gate width W3 of the third transistor Q3 is n = 1000, the gate width W3 of the third transistor Q3 is equal to the gate width W2 of the second transistor Q2. 1/1000 of the above. Therefore, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n = ID / 1000
It becomes.

In that case, the potential of the source S3 of the third transistor Q3 is lifted by the overcurrent detection resistor Rgs4,
ID3 × Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 × Rgs4
When this voltage reaches the threshold voltage of the fourth transistor Q4, the fourth transistor Q4 turns on. At that time, the voltage Vg of the drain D4 of the fourth transistor Q4 is limited by the product of the on-resistance Ron4 of the fourth transistor Q4 and the current ID4, and the gate potential of the second transistor Q2 becomes
Ron4 × ID4
Will be limited to

  As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 decreases.

  That is, as shown in FIG. 4, when the overcurrent detection circuit 32 according to the present embodiment is provided, the current value of the current ID flowing through the cascode circuit becomes a predetermined overcurrent value when a short circuit occurs. When the voltage becomes equal to or larger than ID (max), the gate voltage of the second transistor Q2 is limited, and the current ID of the nitride semiconductor device 31 is limited.

Note that the value of the overcurrent detection resistor Rgs4 is the threshold voltage of the fourth transistor Q4 when the ratio of the gate width W3 of the third transistor Q3 to the gate width W2 of the second transistor Q2 is (1 / n). Vth4,
Vth4 = (ID (max) / n) × Rgs4
What is necessary is just to design.

  On the other hand, when the current value of the current ID flowing through the cascode circuit is smaller than a predetermined overcurrent value during normal operation, the overcurrent detection circuit 32 does not perform the control operation. The on-resistance of the two transistors Q2 does not increase. Therefore, the on-resistance of the entire cascode connection does not increase.

  As described above, in the second embodiment, the normally-off type of the overcurrent detection circuit 32 of the first embodiment is connected in parallel via the second transistor Q2 and the overcurrent detection resistor Rgs4. It comprises three transistors Q3 and a fourth transistor Q4 connected between the gate G3 of the third transistor Q3 and the source S2 of the second transistor Q2.

  The gate G4 of the fourth transistor Q4 is connected to the source S3 of the third transistor Q3. Further, the drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to the external gate terminal Gc. Further, the gate width W3 of the third transistor Q3 is set to 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

Then, the current ID3 flowing through the third transistor Q3 becomes
ID3 ≒ ID / n
And the potential of the source S3 is
ID3 × Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 × Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth transistor Q4, the fourth transistor Q4 turns on. That is,
ID3 × Rgs4 = (ID / n) × Rgs4 ≧ Vth4
So, rearranging this equation,
ID ≧ (Vth4 × n) / Rgs4
Then, the fourth transistor Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is equal to or more than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second transistor Q2 becomes
Ron4 × ID4
Is limited to

  As a result, the potential of the gate G2 of the second transistor Q2 decreases and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 31 of the second embodiment, the amount of heat generated during the short circuit time can be significantly improved.

  In this case, the overcurrent detection circuit 32 limits the saturation current only when the current ID becomes equal to or more than the overcurrent value ID (max). Therefore, the ON resistance of the entire cascode connection does not increase during normal operation.

  That is, it is possible to reduce the amount of heat generated during the short-circuit time by reducing the saturation current while minimizing the increase in the on-resistance, and to significantly increase the length of the short-circuit time.

[Third embodiment]
FIG. 3 is a circuit configuration diagram of a nitride semiconductor device 41 as a semiconductor device according to a third embodiment of the present invention.

  The nitride semiconductor device 41 of the third embodiment relates to a specific configuration different from that of the overcurrent detection circuit 32 of the second embodiment. Therefore, the same members as those of the second embodiment shown in FIG. 2 are denoted by the same reference numerals as those of the second embodiment, and detailed description is omitted.

  The overcurrent detection circuit 42 in the nitride semiconductor device 41 includes a normally-off type third transistor Q3 and a fourth transistor Q4 as in the case of the second embodiment. The third and fourth transistors Q3 and Q4 are, for example, MOS transistors. Further, an overcurrent detection resistor Rgs4 is connected between the source S3 of the third transistor Q3 and the source S2 of the second transistor Q2.

  The overcurrent detection circuit 42 in the nitride semiconductor device 41 of the third embodiment has a gate resistance Rg between the external gate terminal Gc and the drain D3 of the fourth transistor Q4. It is different from the current detection circuit 32.

  Hereinafter, the operation of limiting the current when an overcurrent flows through the nitride semiconductor device 41 having the above configuration will be described. Here, it is assumed that a power supply (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed at the GND potential. When an ON input signal is input to the external gate terminal Gc, the current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is defined as ID, and the current flowing through the third transistor Q3 is defined as ID3. And the current flowing through the fourth transistor Q4 is ID4.

For example, when the magnification n of the gate width W2 of the second transistor Q2 with respect to the gate width W3 of the third transistor Q3 is n = 1000, the gate width W3 of the third transistor Q3 is equal to the gate width W2 of the second transistor Q2. 1/1000 of the above. Therefore, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n = ID / 1000
It becomes.

In that case, the potential of the source S3 of the third transistor Q3 is lifted by the overcurrent detection resistor Rgs4,
ID3 × Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 × Rgs4
When this voltage reaches the threshold voltage of the fourth transistor Q4, the fourth transistor Q4 turns on. At this time, the voltage Vg of the drain D4 of the fourth transistor Q4 is a partial voltage of the gate resistance Rg and the on-resistance Ron4 of the fourth transistor Q4, where VG is the voltage of the external gate terminal Gc. It is represented by (1).
Vg = {Ron4 / (Rg + Ron4)} × VG (1)

Therefore, the voltage Vg of the drain D4 of the fourth transistor Q4 is limited by the above equation (1), and the gate potential of the second transistor Q2 becomes
{Ron4 / (Rg + Ron4)} × VG
Will be limited to

  As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 decreases.

  That is, as shown in FIG. 4, when there is the overcurrent detection circuit 42 shown in this embodiment, the current value of the current ID flowing through the cascode circuit becomes a predetermined overcurrent value when a short circuit or the like occurs. When the voltage becomes equal to or more than ID (max), the gate voltage of the second transistor Q2 is limited, and the current ID of the nitride semiconductor device 41 is limited.

Note that the value of the overcurrent detection resistor Rgs4 is the threshold voltage of the fourth transistor Q4 when the ratio of the gate width W3 of the third transistor Q3 to the gate width W2 of the second transistor Q2 is (1 / n). Vth4,
Vth4 = (ID (max) / n) × Rgs4
What is necessary is just to design. In addition, the gate resistance Rg may be adjusted to the voltage Vg that provides an appropriate current ID according to the above equation (1).

  On the other hand, when the current value of the current ID flowing through the cascode circuit is a normal operation that is smaller than a predetermined overcurrent value set in advance, the overcurrent detection circuit 42 does not perform the control operation. The on-resistance of the two transistors Q2 does not increase. Therefore, the on-resistance of the entire cascode connection does not increase.

  As described above, in the third embodiment, the overcurrent detection circuit 42 is connected in parallel via the second transistor Q2 and the overcurrent detection resistor Rgs4, similarly to the overcurrent detection circuit 32 in the second embodiment. And a fourth transistor Q4 interposed between the gate G3 of the third transistor Q3 and the source S2 of the second transistor Q2. .

  The gate G4 of the fourth transistor Q4 is connected to the source S3 of the third transistor Q3. Further, the drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to the external gate terminal Gc. Further, the gate width W3 of the third transistor Q3 is set to 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

  Further, a gate resistor Rg is provided between the external gate terminal Gc and the drain D3 of the fourth transistor Q4.

Then, the current ID3 flowing through the third transistor Q3 becomes
ID3 ≒ ID / n
And the potential of the source S3 is
ID3 × Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 × Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth transistor Q4, the fourth transistor Q4 turns on. That is,
ID3 × Rgs4 = (ID / n) × Rgs4 ≧ Vth4
So, rearranging this equation,
ID ≧ (Vth4 × n) / Rgs4
Then, the fourth transistor Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second transistor Q2 becomes
{Ron4 / (Rg + Ron4)} × VG
Is limited to

  As a result, the potential of the gate G2 of the second transistor Q2 decreases and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 41 of the third embodiment, the amount of heat generated during the short circuit time can be significantly improved.

  In this case, the overcurrent detection circuit 42 limits the saturation current only when the current ID becomes equal to or more than the overcurrent value ID (max). Therefore, the ON resistance of the entire cascode connection does not increase during normal operation.

  That is, it is possible to reduce the amount of heat generated during the short-circuit time by reducing the saturation current while minimizing the increase in the on-resistance, and to significantly increase the length of the short-circuit time.

Further, as described above, the potential of the gate G2 of the second transistor Q2 when the current ID becomes equal to or more than the overcurrent value ID (max) is
{Ron4 / (Rg + Ron4)} × VG
Limited to. Therefore, the potential of the gate G2 of the second transistor Q2 can be reduced by the voltage divided into the gate resistance Rg as compared with the case of the second embodiment in which there is no gate resistance Rg (Rg = 0). Therefore, the saturation current value of the first transistor Q1 can be further reduced as compared with the case of the second embodiment.

  Here, it is desirable that the second, third and fourth transistors Q2, Q3 and Q4 in the first to third embodiments are formed on the same chip. This makes it possible to easily form the normally-off second, third, and fourth transistors Q2, Q3, and Q4 with MOS transistors in the same process.

  Further, it is desirable that the first transistor Q1 to the fourth transistor Q4 be built in the same package. This makes it possible to obtain a small-sized semiconductor device in which the first transistor Q1 to the fourth transistor Q4 are incorporated in the same package and the amount of heat generated during the short-circuit time is greatly reduced.

  Further, in the first to third embodiments, as a countermeasure against oscillation of the drain current due to repetition of ON / OFF of the second transistor Q2, a stable operation may be performed by performing phase compensation by a phase compensation circuit.

  In the first to third embodiments, the first transistor Q1 is constituted by a GaN transistor, but is not limited to a nitride semiconductor device such as a GaN transistor. However, in the case of a GaN transistor, a great effect can be obtained by reducing the on-resistance.

  Although the specific embodiments of the present invention have been described, the present invention is not limited to the above-described first to third embodiments, and various modifications can be made within the scope of the present invention. For example, a combination of the contents described in the first to third embodiments may be adopted as an embodiment of the present invention.

Summarizing the above, the semiconductor devices 21, 31, 41 of the present invention are:
A normally-on type first switching element Q1 having a source S1, a drain D1, and a gate G1,
A normally cascode circuit having a source S2, a drain D2, and a gate G2, wherein the drain D2 is electrically connected to the source S1 of the first switching element Q1 to form a cascode circuit with the first switching element; An off-type second switching element Q2,
An overcurrent detection circuit connected to the second switching element in parallel with the second switching element and detecting an overcurrent flowing through the cascode circuit;
The overcurrent detection circuits 22, 32, and 42 limit the current flowing through the cascode circuit when the value of the current flowing through the cascode circuit is equal to or greater than a predetermined overcurrent value. It is characterized by having.

  According to the above configuration, when the overcurrent detection circuits 22, 32, and 42 detect that the current flowing through the cascode circuit has become equal to or greater than a predetermined overcurrent value, the second The on-resistance of the switching element Q2 is increased, and the flowing current is limited. Therefore, the amount of heat generated during the short circuit time can be significantly reduced.

  In this case, the overcurrent detection circuits 22, 32, and 42 increase the on-resistance of the second switching element Q2 and reduce the flowing current only when the current value flowing through the cascode circuit is equal to or greater than the overcurrent value. I try to limit it. Therefore, the ON resistance of the cascode circuit does not increase during normal operation.

  That is, while suppressing the increase in the on-resistance to a minimum, the amount of heat generated during the short-circuit time can be suppressed by reducing the saturation current, and the length of the short-circuit time can be significantly increased.

Further, in the semiconductor device 31 of one embodiment,
The overcurrent detection circuit 32 includes:
A normally-off type third switching element Q3 connected in parallel with the second switching element Q2 and having a source S3, a drain D3, and a gate G3;
An overcurrent detection resistor Rgs4 connected between the source S3 of the third switching element Q3 and the source S2 of the second switching element Q2;
A normally-off fourth switching element Q4 having a source S4, a drain D4 and a gate G4;
The drain D4 of the fourth switching element Q4 is commonly connected to the gate G3 of the third switching element Q3 and the gate G2 of the second switching element Q2,
The gate G4 of the fourth switching element Q4 is commonly connected to the source S3 of the third switching element Q3 and one end of the overcurrent detection resistor Rgs4,
The source S4 of the fourth switching element Q4 is commonly connected to the other end of the overcurrent detection resistor Rgs4 and the source S2 of the second switching element Q2,
The gate width W3 of the third switching element Q3 is set to be 1 / n (n> 1) times the gate width W2 of the second switching element Q2.

According to this embodiment, assuming that the current flowing through the cascode circuit is ID and the overcurrent detection resistor is Rgs4, the current ID3 flowing through the third switching element Q3 is
ID3 ≒ ID / n
And the potential of the source S3 of the third switching element Q3 is determined with reference to the potential of the source S2 of the second switching element Q2.
ID3 × Rgs4
It becomes. Therefore, the gate-source voltage of the fourth switching element Q4 is
ID3 × Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth switching element Q4, the fourth switching element Q4 is turned on. That is, when ID ≧ (Vth4 × n) / Rgs4, the fourth switching element Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second switching element Q2 becomes
Ron4 × ID4
Is limited to

  As a result, the potential of the gate G2 of the second switching element Q2 decreases, and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first switching element Q1 increases, and the gate overdrive voltage of the normally-on type first switching element Q1 decreases. Therefore, the value of the current flowing through the first switching element Q1 can be reduced, and the current flowing through the cascode circuit can be limited.

Further, in the semiconductor device 41 of one embodiment,
An external gate terminal Gc commonly connected to the gate G3 of the third switching element Q3, the gate G2 of the second switching element Q2, and the drain D4 of the fourth switching element Q4;
The overcurrent detection circuit 42 includes:
A gate resistor Rg is connected between the external gate terminal Gc and the drain D4 of the fourth switching element Q4.

  According to this embodiment, with the potential of the source S2 of the second switching element Q2 as a reference, the current flowing through the cascode circuit is ID, the overcurrent detection resistor is Rgs4, and the voltage of the external gate terminal Gc is Is VG, and the on-resistance of the fourth switching element Q4 is Ron4. Similarly to the above-described embodiment, when ID ≧ (Vth4 × n) / Rgs4, the fourth switching element Q4 is turned on. .

At this time, the voltage Vg of the drain D4 of the fourth switching element Q4 is a voltage division of the gate resistance Rg and the on-resistance Ron4 of the fourth switching element Q4.
{Ron4 / (Rg + Ron4)} × VG
It becomes.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second switching element Q2 becomes
{Ron4 / (Rg + Ron4)} × VG
Is limited to

  As a result, similarly to the case of the above-described embodiment, the value of the current flowing through the first switching element Q1 can be reduced, and the current ID flowing through the cascode circuit can be limited.

Further, as described above, the potential of the gate G2 of the second switching element Q2 when the current ID is equal to or more than the overcurrent value ID (max) is
{Ron4 / (Rg + Ron4)} × VG
Limited to. Therefore, compared to the above-described embodiment without the gate resistance Rg (Rg = 0), the voltage can be reduced by the partial pressure to the gate resistance Rg. That is, the current flowing through the cascode circuit can be further limited as compared with the case of the above-described embodiment.

Further, in the semiconductor devices 21, 31, 41 according to one embodiment,
The second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are formed on the same chip.

  According to this embodiment, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are formed on the same chip. Therefore, the normally-off type second switching element Q2 to fourth switching element Q4 can be easily formed of MOS transistors in the same process.

Further, in the semiconductor devices 21, 31, 41 according to one embodiment,
The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are built in the same package.

  According to this embodiment, it is possible to obtain a small-sized semiconductor device in which the first switching element Q1 to the fourth switching element Q4 are incorporated in the same package and the amount of heat generated during short-circuit time is greatly reduced.

21, 31, 41: nitride semiconductor devices 22, 32, 42: overcurrent detection circuit Dc: external drain terminal (external terminal)
Sc: External source terminal (external terminal)
Gc: External gate terminal (external terminal)
Q1 a normally-on type first transistor S1 source of the first transistor D1 drain G1 of the first transistor gate of the first transistor Q2 normally-off type second transistor S2 source D2 of the second transistor Drain G2 of second transistor ... Gate Q3 of second transistor ... Normal-off type third transistor S3 ... Source D3 of third transistor ... Drain G3 of third transistor ... Gate Q4 of third transistor ... Normal-off type Fourth transistor S4 Source of the fourth transistor D4 Drain of the fourth transistor G4 Gate of the fourth transistor R1 Resistance Rgs4 Overcurrent detection resistance Rg Gate resistance

Claims (5)

A normally-on type first switching element having a source, a drain, and a gate;
A normally-off type second switching element having a source, a drain, and a gate, wherein the drain is electrically connected to the source of the first switching element, and forms a cascode circuit together with the first switching element; When,
An overcurrent detection circuit connected in parallel with the second switching element and detecting an overcurrent flowing through the cascode circuit ;
An external gate terminal connected to the gate of the second switching element ;
The overcurrent detection circuit,
Reducing the potential of an ON signal supplied from the external gate terminal to the gate of the second switching element when a value of a current flowing through the cascode circuit is equal to or greater than a predetermined overcurrent value. , the semiconductor, characterized in that said second by increasing the on-resistance of the switching element is configured to win suppress the heating value of the first switching element in a state in which current flows in the cascode circuit apparatus. The semiconductor device according to claim 1,
The overcurrent detection circuit,
A normally-off type third switching element which is connected in parallel with the second switching element and has a source, a drain, and a gate;
An overcurrent detection resistor connected between the source of the third switching element and the source of the second switching element;
Having a normally-off type fourth switching element having a source, a drain, and a gate,
The drain of the fourth switching element is commonly connected to the gate of the third switching element and the gate of the second switching element;
The gate of the fourth switching element is commonly connected to the source of the third switching element and one end of the overcurrent detection resistor;
The source of the fourth switching element is commonly connected to the other end of the overcurrent detection resistor and the source of the second switching element;
A semiconductor device, wherein the gate width W3 of the third switching element is set to be 1 / n (n> 1) times the gate width W2 of the second switching element. The semiconductor device according to claim 2,
The external gate terminal is
Commonly connected to the gate of the third switching element, the gate of the second switching element, and the drain of the fourth switching element ;
The overcurrent detection circuit,
A semiconductor device having a gate resistance connected between the external gate terminal and the drain of the fourth switching element. The semiconductor device according to claim 2 or 3,
A semiconductor device, wherein the second switching element, the third switching element, and the fourth switching element are formed on the same chip. The semiconductor device according to any one of claims 2 to 4,
A semiconductor device, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are contained in a same package.

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