JPH0787351B2 - Input transition detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input transition detection circuit that detects a change in rising or falling of an input signal and generates a desired pulse.

Prior Art FIG. 3 shows an example of a conventional input transition detection circuit. In FIG. 3, 20 is a delay circuit, 22 and 24 are N-channel MOSFEs.
T and 26 are P-channel MOSFETs, X ₀ is an input signal, X ₁ is an inverted signal obtained by delaying X ₀ , and Z is an output signal in which the rising edge of X ₀ is detected. FIG. 4 is an operation waveform diagram of the circuit of FIG.

Before time t ₁₁ , since X ₀ is “L”, X ₁ is “H” and the FET 24 is in the conducting state, but the FET 22 is in the non-conducting state and Z is in the non-conducting state with the ground line. On the other hand, since the FET 26 is normally conductive, Z becomes "H". At time t ₁₁ , since X ₀ changes from “L” to “H”, both FETs 22 and 24 become conductive, and at time t ₁₂ , Z changes from “H” to “L” at time t ₁₃ . X ₁ by the delay circuit 20 is "H"
Changes from "L" to "L", so FET24 becomes non-conductive,
Since the FET26 of Z is conductive, the potential starts rising,
Then, at time t ₁₄ , Z changes from "L" to "H". Time t
_{At 15} , even if X ₀ changes from “H” to “L”, both FETs 22 and 24 are in the non-conduction state, so Z holds “H”, and at time t ₁₆ , X ₁ changes from “L” to “H”. However, since the FET 22 is non-conductive, Z holds "H".

Here, when the ON resistance Rp of the FET 26 is increased, the rise time of Z becomes long, and the pulse width of Z changes greatly due to variations in the manufacturing process, so it is difficult to generate a signal with a predetermined pulse width. On the other hand, in order to reduce the rise time of Z, the ON resistance Rp of the FET 26 may be decreased, but the “L” level of Z is equal to the on resistance R _N of the FETs 22 and 24 in series.
Since the ON resistance Rp of the FET 26 can be compared, if Rp is made small, the "L" level of Z rises and the through current becomes large.

Problems to be Solved by the Invention In a conventional input transition detection circuit, a P channel MO for load is used.
When the on resistance of the SFET is reduced, the “L” level of the detection signal rises and the shoot-through current increases. On the other hand, when the on resistance is increased, the rise time of the detection signal increases and the variation in the manufacturing process causes It becomes difficult to generate a detection signal having a pulse width of.

The present invention has been made in view of the above points, and provides an input transition detection circuit that has low power consumption, is capable of high-speed response, and obtains a detection signal having a predetermined pulse width.

Means for Solving the Problems In order to solve the above problems, the present invention increases the on-resistance of a load P-channel MOSFET and provides a P-channel MOSFET connected in parallel with the P-channel MOSFET to provide a gate input. Is used as an inversion delay signal of the input signal so that it becomes conductive when the detection signal rises.

Effect The present invention, with the above configuration, can easily obtain an edge detection signal having a predetermined pulse width, and can also reduce the power consumption of the input transition detection circuit.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of an input transition detection circuit for detecting a change in rising edge of an input signal and generating a desired pulse according to the present invention. FIG. 2 is an operation waveform diagram for explaining the operation of the circuit of FIG. In FIGS. 1 and 2, 2 and 4 are N-channel MOSFETs, and 6 and 8 are P-channel MOSFs.
ET and 10 are delay circuits, X ₀ is an input signal, X ₁ is an inverted signal obtained by delaying the input signal, and Y is an output signal in which the rising edge of the input signal is detected. Before the time t ₁ , the input signal X ₀ is “L”, and therefore X ₁ is “H” because it is a signal obtained by delaying and inverting X ₀ . At this time, as for the output signal Y, since the FET 4 is in the conductive state and the FET 2 is in the non-conductive state, the Y and the ground line are in the non-conductive state, and the FET 6 is in the normal conductive state, so that the Y and the power supply line are in the conductive state. And becomes "H".

At time t ₁ , X ₀ changes from “L” to “H”, but X ₁ is X ₀
Since there is a delay time with respect to the change of, it becomes “H” at t ₁ . Therefore, at time t ₁ , both FETs 2 and 4 become conductive, so that Y starts to change from “H” to “L” and becomes “L” at time t ₂ .

At time t ₃ , the delay circuit 10 changes X ₁ from “H” to “L” with respect to the rise of X ₀ . The delay amount of the delay circuit 10 is given by (t ₃ −t ₁ ). When X ₁ changes from “H” to “L”, FET 4 becomes non-conductive and FET 8 becomes conductive, so Y starts changing from “L” to “H”, and at time t ₄ , Y becomes "H". At time t ₅ , X ₀ changes from “H” to “L”, but FETs 2 and 4 are also non-conducting, Y holds “H”, and at time t ₆ , X ₁ is “L”.
Changes from "H" to "H", FET4 becomes conductive,
Since FET2 is non-conducting, Y holds "H".

As a result, FIG. 1 constitutes an input transition detection circuit for detecting the rising edge of the input signal X ₀ .

Here, the on-resistance Rp ₆ of FET ₆ is the on-resistance R _N2 , R _N4 of FETs ₂ and _4.
By satisfying the relation of Rp ₆ >> R _N2 + R _N4 as compared with, Y is caused to fall at a high speed with respect to the rise of X ₀ ,
The pulse width of Y can be freely set by the delay circuit 10, and Y is raised at a high speed by making the FET 8 conductive at the fall of X ₁ . As a result, the detection signal of the input transition having the pulse width set by the delay circuit 10 is generated at high speed. Further, by increasing the on-resistance of the FET 6, it is possible to reduce a through current, reducing the parasitic capacitance of the X ₀ by using only the input of the gate and delay circuit 10 of the input signals X ₀ FET2 Therefore, the generation of the detection signal can be speeded up.

In FIG. 1, the case of rising edge detection has been described, but in the case of falling edge detection, the input signal is inverted to
You can see that it can be easily done by connecting to X ₀ .

As described above, according to the present invention, the load capacitance of an input signal can be reduced, a detection signal with a predetermined pulse width can be easily generated, and the rise time and fall time of the detection signal can be shortened. Thus, it is possible to provide an edge detection circuit with less through current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input transition detection circuit in one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the circuit, and FIG. 3 is a circuit diagram showing a conventional input transition detection circuit. ,
FIG. 4 is a waveform diagram for explaining the operation of the circuit. 2,4 …… N-channel MOSFET, 6,8 …… P-channel MOSF
ET, 10 ... delay circuit, X ₀ ... input signal, X ₁ ... delay circuit output signal, Y ... detection signal.

Claims (1)

[Claims] 1. A first N-channel MOSFET having delay means for inverting and delaying an input signal, wherein the output of the delay means is a first N-channel MOSFET.
And a gate input of a first P-channel MOSFET, the input signal is a gate input of a second N-channel MOSFET, and a source of the first N-channel MOSFET is grounded,
The drain is connected to the source of the second N-channel MOSFET, the drain of the second N-channel MOSFET, the first P-channel MOSFET and the second P-channel MO.
The drain of the SFET is commonly connected to serve as a detection signal,
P-channel MOSFET and second P-channel MOSFET
Of the second P-channel MOSF by connecting the source of the
An input transition detection circuit in which the gate of ET is grounded and the ON resistance of the second P-channel MOSFET is sufficiently larger than the ON resistances of the first and second N-channel MOSFETs.